makefiles.txt 39 KB

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  1. Linux Kernel Makefiles
  2. This document describes the Linux kernel Makefiles.
  3. === Table of Contents
  4. === 1 Overview
  5. === 2 Who does what
  6. === 3 The kbuild files
  7. --- 3.1 Goal definitions
  8. --- 3.2 Built-in object goals - obj-y
  9. --- 3.3 Loadable module goals - obj-m
  10. --- 3.4 Objects which export symbols
  11. --- 3.5 Library file goals - lib-y
  12. --- 3.6 Descending down in directories
  13. --- 3.7 Compilation flags
  14. --- 3.8 Command line dependency
  15. --- 3.9 Dependency tracking
  16. --- 3.10 Special Rules
  17. --- 3.11 $(CC) support functions
  18. === 4 Host Program support
  19. --- 4.1 Simple Host Program
  20. --- 4.2 Composite Host Programs
  21. --- 4.3 Defining shared libraries
  22. --- 4.4 Using C++ for host programs
  23. --- 4.5 Controlling compiler options for host programs
  24. --- 4.6 When host programs are actually built
  25. --- 4.7 Using hostprogs-$(CONFIG_FOO)
  26. === 5 Kbuild clean infrastructure
  27. === 6 Architecture Makefiles
  28. --- 6.1 Set variables to tweak the build to the architecture
  29. --- 6.2 Add prerequisites to archprepare:
  30. --- 6.3 List directories to visit when descending
  31. --- 6.4 Architecture-specific boot images
  32. --- 6.5 Building non-kbuild targets
  33. --- 6.6 Commands useful for building a boot image
  34. --- 6.7 Custom kbuild commands
  35. --- 6.8 Preprocessing linker scripts
  36. === 7 Kbuild Variables
  37. === 8 Makefile language
  38. === 9 Credits
  39. === 10 TODO
  40. === 1 Overview
  41. The Makefiles have five parts:
  42. Makefile the top Makefile.
  43. .config the kernel configuration file.
  44. arch/$(ARCH)/Makefile the arch Makefile.
  45. scripts/Makefile.* common rules etc. for all kbuild Makefiles.
  46. kbuild Makefiles there are about 500 of these.
  47. The top Makefile reads the .config file, which comes from the kernel
  48. configuration process.
  49. The top Makefile is responsible for building two major products: vmlinux
  50. (the resident kernel image) and modules (any module files).
  51. It builds these goals by recursively descending into the subdirectories of
  52. the kernel source tree.
  53. The list of subdirectories which are visited depends upon the kernel
  54. configuration. The top Makefile textually includes an arch Makefile
  55. with the name arch/$(ARCH)/Makefile. The arch Makefile supplies
  56. architecture-specific information to the top Makefile.
  57. Each subdirectory has a kbuild Makefile which carries out the commands
  58. passed down from above. The kbuild Makefile uses information from the
  59. .config file to construct various file lists used by kbuild to build
  60. any built-in or modular targets.
  61. scripts/Makefile.* contains all the definitions/rules etc. that
  62. are used to build the kernel based on the kbuild makefiles.
  63. === 2 Who does what
  64. People have four different relationships with the kernel Makefiles.
  65. *Users* are people who build kernels. These people type commands such as
  66. "make menuconfig" or "make". They usually do not read or edit
  67. any kernel Makefiles (or any other source files).
  68. *Normal developers* are people who work on features such as device
  69. drivers, file systems, and network protocols. These people need to
  70. maintain the kbuild Makefiles for the subsystem they are
  71. working on. In order to do this effectively, they need some overall
  72. knowledge about the kernel Makefiles, plus detailed knowledge about the
  73. public interface for kbuild.
  74. *Arch developers* are people who work on an entire architecture, such
  75. as sparc or ia64. Arch developers need to know about the arch Makefile
  76. as well as kbuild Makefiles.
  77. *Kbuild developers* are people who work on the kernel build system itself.
  78. These people need to know about all aspects of the kernel Makefiles.
  79. This document is aimed towards normal developers and arch developers.
  80. === 3 The kbuild files
  81. Most Makefiles within the kernel are kbuild Makefiles that use the
  82. kbuild infrastructure. This chapter introduces the syntax used in the
  83. kbuild makefiles.
  84. The preferred name for the kbuild files are 'Makefile' but 'Kbuild' can
  85. be used and if both a 'Makefile' and a 'Kbuild' file exists, then the 'Kbuild'
  86. file will be used.
  87. Section 3.1 "Goal definitions" is a quick intro, further chapters provide
  88. more details, with real examples.
  89. --- 3.1 Goal definitions
  90. Goal definitions are the main part (heart) of the kbuild Makefile.
  91. These lines define the files to be built, any special compilation
  92. options, and any subdirectories to be entered recursively.
  93. The most simple kbuild makefile contains one line:
  94. Example:
  95. obj-y += foo.o
  96. This tells kbuild that there is one object in that directory, named
  97. foo.o. foo.o will be built from foo.c or foo.S.
  98. If foo.o shall be built as a module, the variable obj-m is used.
  99. Therefore the following pattern is often used:
  100. Example:
  101. obj-$(CONFIG_FOO) += foo.o
  102. $(CONFIG_FOO) evaluates to either y (for built-in) or m (for module).
  103. If CONFIG_FOO is neither y nor m, then the file will not be compiled
  104. nor linked.
  105. --- 3.2 Built-in object goals - obj-y
  106. The kbuild Makefile specifies object files for vmlinux
  107. in the $(obj-y) lists. These lists depend on the kernel
  108. configuration.
  109. Kbuild compiles all the $(obj-y) files. It then calls
  110. "$(LD) -r" to merge these files into one built-in.o file.
  111. built-in.o is later linked into vmlinux by the parent Makefile.
  112. The order of files in $(obj-y) is significant. Duplicates in
  113. the lists are allowed: the first instance will be linked into
  114. built-in.o and succeeding instances will be ignored.
  115. Link order is significant, because certain functions
  116. (module_init() / __initcall) will be called during boot in the
  117. order they appear. So keep in mind that changing the link
  118. order may e.g. change the order in which your SCSI
  119. controllers are detected, and thus your disks are renumbered.
  120. Example:
  121. #drivers/isdn/i4l/Makefile
  122. # Makefile for the kernel ISDN subsystem and device drivers.
  123. # Each configuration option enables a list of files.
  124. obj-$(CONFIG_ISDN) += isdn.o
  125. obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
  126. --- 3.3 Loadable module goals - obj-m
  127. $(obj-m) specify object files which are built as loadable
  128. kernel modules.
  129. A module may be built from one source file or several source
  130. files. In the case of one source file, the kbuild makefile
  131. simply adds the file to $(obj-m).
  132. Example:
  133. #drivers/isdn/i4l/Makefile
  134. obj-$(CONFIG_ISDN_PPP_BSDCOMP) += isdn_bsdcomp.o
  135. Note: In this example $(CONFIG_ISDN_PPP_BSDCOMP) evaluates to 'm'
  136. If a kernel module is built from several source files, you specify
  137. that you want to build a module in the same way as above.
  138. Kbuild needs to know which the parts that you want to build your
  139. module from, so you have to tell it by setting an
  140. $(<module_name>-objs) variable.
  141. Example:
  142. #drivers/isdn/i4l/Makefile
  143. obj-$(CONFIG_ISDN) += isdn.o
  144. isdn-objs := isdn_net_lib.o isdn_v110.o isdn_common.o
  145. In this example, the module name will be isdn.o. Kbuild will
  146. compile the objects listed in $(isdn-objs) and then run
  147. "$(LD) -r" on the list of these files to generate isdn.o.
  148. Kbuild recognises objects used for composite objects by the suffix
  149. -objs, and the suffix -y. This allows the Makefiles to use
  150. the value of a CONFIG_ symbol to determine if an object is part
  151. of a composite object.
  152. Example:
  153. #fs/ext2/Makefile
  154. obj-$(CONFIG_EXT2_FS) += ext2.o
  155. ext2-y := balloc.o bitmap.o
  156. ext2-$(CONFIG_EXT2_FS_XATTR) += xattr.o
  157. In this example, xattr.o is only part of the composite object
  158. ext2.o if $(CONFIG_EXT2_FS_XATTR) evaluates to 'y'.
  159. Note: Of course, when you are building objects into the kernel,
  160. the syntax above will also work. So, if you have CONFIG_EXT2_FS=y,
  161. kbuild will build an ext2.o file for you out of the individual
  162. parts and then link this into built-in.o, as you would expect.
  163. --- 3.4 Objects which export symbols
  164. No special notation is required in the makefiles for
  165. modules exporting symbols.
  166. --- 3.5 Library file goals - lib-y
  167. Objects listed with obj-* are used for modules, or
  168. combined in a built-in.o for that specific directory.
  169. There is also the possibility to list objects that will
  170. be included in a library, lib.a.
  171. All objects listed with lib-y are combined in a single
  172. library for that directory.
  173. Objects that are listed in obj-y and additionally listed in
  174. lib-y will not be included in the library, since they will
  175. be accessible anyway.
  176. For consistency, objects listed in lib-m will be included in lib.a.
  177. Note that the same kbuild makefile may list files to be built-in
  178. and to be part of a library. Therefore the same directory
  179. may contain both a built-in.o and a lib.a file.
  180. Example:
  181. #arch/i386/lib/Makefile
  182. lib-y := checksum.o delay.o
  183. This will create a library lib.a based on checksum.o and delay.o.
  184. For kbuild to actually recognize that there is a lib.a being built,
  185. the directory shall be listed in libs-y.
  186. See also "6.3 List directories to visit when descending".
  187. Use of lib-y is normally restricted to lib/ and arch/*/lib.
  188. --- 3.6 Descending down in directories
  189. A Makefile is only responsible for building objects in its own
  190. directory. Files in subdirectories should be taken care of by
  191. Makefiles in these subdirs. The build system will automatically
  192. invoke make recursively in subdirectories, provided you let it know of
  193. them.
  194. To do so, obj-y and obj-m are used.
  195. ext2 lives in a separate directory, and the Makefile present in fs/
  196. tells kbuild to descend down using the following assignment.
  197. Example:
  198. #fs/Makefile
  199. obj-$(CONFIG_EXT2_FS) += ext2/
  200. If CONFIG_EXT2_FS is set to either 'y' (built-in) or 'm' (modular)
  201. the corresponding obj- variable will be set, and kbuild will descend
  202. down in the ext2 directory.
  203. Kbuild only uses this information to decide that it needs to visit
  204. the directory, it is the Makefile in the subdirectory that
  205. specifies what is modules and what is built-in.
  206. It is good practice to use a CONFIG_ variable when assigning directory
  207. names. This allows kbuild to totally skip the directory if the
  208. corresponding CONFIG_ option is neither 'y' nor 'm'.
  209. --- 3.7 Compilation flags
  210. EXTRA_CFLAGS, EXTRA_AFLAGS, EXTRA_LDFLAGS, EXTRA_ARFLAGS
  211. All the EXTRA_ variables apply only to the kbuild makefile
  212. where they are assigned. The EXTRA_ variables apply to all
  213. commands executed in the kbuild makefile.
  214. $(EXTRA_CFLAGS) specifies options for compiling C files with
  215. $(CC).
  216. Example:
  217. # drivers/sound/emu10k1/Makefile
  218. EXTRA_CFLAGS += -I$(obj)
  219. ifdef DEBUG
  220. EXTRA_CFLAGS += -DEMU10K1_DEBUG
  221. endif
  222. This variable is necessary because the top Makefile owns the
  223. variable $(CFLAGS) and uses it for compilation flags for the
  224. entire tree.
  225. $(EXTRA_AFLAGS) is a similar string for per-directory options
  226. when compiling assembly language source.
  227. Example:
  228. #arch/x86_64/kernel/Makefile
  229. EXTRA_AFLAGS := -traditional
  230. $(EXTRA_LDFLAGS) and $(EXTRA_ARFLAGS) are similar strings for
  231. per-directory options to $(LD) and $(AR).
  232. Example:
  233. #arch/m68k/fpsp040/Makefile
  234. EXTRA_LDFLAGS := -x
  235. CFLAGS_$@, AFLAGS_$@
  236. CFLAGS_$@ and AFLAGS_$@ only apply to commands in current
  237. kbuild makefile.
  238. $(CFLAGS_$@) specifies per-file options for $(CC). The $@
  239. part has a literal value which specifies the file that it is for.
  240. Example:
  241. # drivers/scsi/Makefile
  242. CFLAGS_aha152x.o = -DAHA152X_STAT -DAUTOCONF
  243. CFLAGS_gdth.o = # -DDEBUG_GDTH=2 -D__SERIAL__ -D__COM2__ \
  244. -DGDTH_STATISTICS
  245. CFLAGS_seagate.o = -DARBITRATE -DPARITY -DSEAGATE_USE_ASM
  246. These three lines specify compilation flags for aha152x.o,
  247. gdth.o, and seagate.o
  248. $(AFLAGS_$@) is a similar feature for source files in assembly
  249. languages.
  250. Example:
  251. # arch/arm/kernel/Makefile
  252. AFLAGS_head-armv.o := -DTEXTADDR=$(TEXTADDR) -traditional
  253. AFLAGS_head-armo.o := -DTEXTADDR=$(TEXTADDR) -traditional
  254. --- 3.9 Dependency tracking
  255. Kbuild tracks dependencies on the following:
  256. 1) All prerequisite files (both *.c and *.h)
  257. 2) CONFIG_ options used in all prerequisite files
  258. 3) Command-line used to compile target
  259. Thus, if you change an option to $(CC) all affected files will
  260. be re-compiled.
  261. --- 3.10 Special Rules
  262. Special rules are used when the kbuild infrastructure does
  263. not provide the required support. A typical example is
  264. header files generated during the build process.
  265. Another example are the architecture-specific Makefiles which
  266. need special rules to prepare boot images etc.
  267. Special rules are written as normal Make rules.
  268. Kbuild is not executing in the directory where the Makefile is
  269. located, so all special rules shall provide a relative
  270. path to prerequisite files and target files.
  271. Two variables are used when defining special rules:
  272. $(src)
  273. $(src) is a relative path which points to the directory
  274. where the Makefile is located. Always use $(src) when
  275. referring to files located in the src tree.
  276. $(obj)
  277. $(obj) is a relative path which points to the directory
  278. where the target is saved. Always use $(obj) when
  279. referring to generated files.
  280. Example:
  281. #drivers/scsi/Makefile
  282. $(obj)/53c8xx_d.h: $(src)/53c7,8xx.scr $(src)/script_asm.pl
  283. $(CPP) -DCHIP=810 - < $< | ... $(src)/script_asm.pl
  284. This is a special rule, following the normal syntax
  285. required by make.
  286. The target file depends on two prerequisite files. References
  287. to the target file are prefixed with $(obj), references
  288. to prerequisites are referenced with $(src) (because they are not
  289. generated files).
  290. --- 3.11 $(CC) support functions
  291. The kernel may be built with several different versions of
  292. $(CC), each supporting a unique set of features and options.
  293. kbuild provide basic support to check for valid options for $(CC).
  294. $(CC) is usually the gcc compiler, but other alternatives are
  295. available.
  296. as-option
  297. as-option is used to check if $(CC) -- when used to compile
  298. assembler (*.S) files -- supports the given option. An optional
  299. second option may be specified if the first option is not supported.
  300. Example:
  301. #arch/sh/Makefile
  302. cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
  303. In the above example, cflags-y will be assigned the option
  304. -Wa$(comma)-isa=$(isa-y) if it is supported by $(CC).
  305. The second argument is optional, and if supplied will be used
  306. if first argument is not supported.
  307. ld-option
  308. ld-option is used to check if $(CC) when used to link object files
  309. supports the given option. An optional second option may be
  310. specified if first option are not supported.
  311. Example:
  312. #arch/i386/kernel/Makefile
  313. vsyscall-flags += $(call ld-option, -Wl$(comma)--hash-style=sysv)
  314. In the above example, vsyscall-flags will be assigned the option
  315. -Wl$(comma)--hash-style=sysv if it is supported by $(CC).
  316. The second argument is optional, and if supplied will be used
  317. if first argument is not supported.
  318. as-instr
  319. as-instr checks if the assembler reports a specific instruction
  320. and then outputs either option1 or option2
  321. C escapes are supported in the test instruction
  322. cc-option
  323. cc-option is used to check if $(CC) supports a given option, and not
  324. supported to use an optional second option.
  325. Example:
  326. #arch/i386/Makefile
  327. cflags-y += $(call cc-option,-march=pentium-mmx,-march=i586)
  328. In the above example, cflags-y will be assigned the option
  329. -march=pentium-mmx if supported by $(CC), otherwise -march=i586.
  330. The second argument to cc-option is optional, and if omitted,
  331. cflags-y will be assigned no value if first option is not supported.
  332. cc-option-yn
  333. cc-option-yn is used to check if gcc supports a given option
  334. and return 'y' if supported, otherwise 'n'.
  335. Example:
  336. #arch/ppc/Makefile
  337. biarch := $(call cc-option-yn, -m32)
  338. aflags-$(biarch) += -a32
  339. cflags-$(biarch) += -m32
  340. In the above example, $(biarch) is set to y if $(CC) supports the -m32
  341. option. When $(biarch) equals 'y', the expanded variables $(aflags-y)
  342. and $(cflags-y) will be assigned the values -a32 and -m32,
  343. respectively.
  344. cc-option-align
  345. gcc versions >= 3.0 changed the type of options used to specify
  346. alignment of functions, loops etc. $(cc-option-align), when used
  347. as prefix to the align options, will select the right prefix:
  348. gcc < 3.00
  349. cc-option-align = -malign
  350. gcc >= 3.00
  351. cc-option-align = -falign
  352. Example:
  353. CFLAGS += $(cc-option-align)-functions=4
  354. In the above example, the option -falign-functions=4 is used for
  355. gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.
  356. cc-version
  357. cc-version returns a numerical version of the $(CC) compiler version.
  358. The format is <major><minor> where both are two digits. So for example
  359. gcc 3.41 would return 0341.
  360. cc-version is useful when a specific $(CC) version is faulty in one
  361. area, for example -mregparm=3 was broken in some gcc versions
  362. even though the option was accepted by gcc.
  363. Example:
  364. #arch/i386/Makefile
  365. cflags-y += $(shell \
  366. if [ $(call cc-version) -ge 0300 ] ; then \
  367. echo "-mregparm=3"; fi ;)
  368. In the above example, -mregparm=3 is only used for gcc version greater
  369. than or equal to gcc 3.0.
  370. cc-ifversion
  371. cc-ifversion tests the version of $(CC) and equals last argument if
  372. version expression is true.
  373. Example:
  374. #fs/reiserfs/Makefile
  375. EXTRA_CFLAGS := $(call cc-ifversion, -lt, 0402, -O1)
  376. In this example, EXTRA_CFLAGS will be assigned the value -O1 if the
  377. $(CC) version is less than 4.2.
  378. cc-ifversion takes all the shell operators:
  379. -eq, -ne, -lt, -le, -gt, and -ge
  380. The third parameter may be a text as in this example, but it may also
  381. be an expanded variable or a macro.
  382. === 4 Host Program support
  383. Kbuild supports building executables on the host for use during the
  384. compilation stage.
  385. Two steps are required in order to use a host executable.
  386. The first step is to tell kbuild that a host program exists. This is
  387. done utilising the variable hostprogs-y.
  388. The second step is to add an explicit dependency to the executable.
  389. This can be done in two ways. Either add the dependency in a rule,
  390. or utilise the variable $(always).
  391. Both possibilities are described in the following.
  392. --- 4.1 Simple Host Program
  393. In some cases there is a need to compile and run a program on the
  394. computer where the build is running.
  395. The following line tells kbuild that the program bin2hex shall be
  396. built on the build host.
  397. Example:
  398. hostprogs-y := bin2hex
  399. Kbuild assumes in the above example that bin2hex is made from a single
  400. c-source file named bin2hex.c located in the same directory as
  401. the Makefile.
  402. --- 4.2 Composite Host Programs
  403. Host programs can be made up based on composite objects.
  404. The syntax used to define composite objects for host programs is
  405. similar to the syntax used for kernel objects.
  406. $(<executable>-objs) lists all objects used to link the final
  407. executable.
  408. Example:
  409. #scripts/lxdialog/Makefile
  410. hostprogs-y := lxdialog
  411. lxdialog-objs := checklist.o lxdialog.o
  412. Objects with extension .o are compiled from the corresponding .c
  413. files. In the above example, checklist.c is compiled to checklist.o
  414. and lxdialog.c is compiled to lxdialog.o.
  415. Finally, the two .o files are linked to the executable, lxdialog.
  416. Note: The syntax <executable>-y is not permitted for host-programs.
  417. --- 4.3 Defining shared libraries
  418. Objects with extension .so are considered shared libraries, and
  419. will be compiled as position independent objects.
  420. Kbuild provides support for shared libraries, but the usage
  421. shall be restricted.
  422. In the following example the libkconfig.so shared library is used
  423. to link the executable conf.
  424. Example:
  425. #scripts/kconfig/Makefile
  426. hostprogs-y := conf
  427. conf-objs := conf.o libkconfig.so
  428. libkconfig-objs := expr.o type.o
  429. Shared libraries always require a corresponding -objs line, and
  430. in the example above the shared library libkconfig is composed by
  431. the two objects expr.o and type.o.
  432. expr.o and type.o will be built as position independent code and
  433. linked as a shared library libkconfig.so. C++ is not supported for
  434. shared libraries.
  435. --- 4.4 Using C++ for host programs
  436. kbuild offers support for host programs written in C++. This was
  437. introduced solely to support kconfig, and is not recommended
  438. for general use.
  439. Example:
  440. #scripts/kconfig/Makefile
  441. hostprogs-y := qconf
  442. qconf-cxxobjs := qconf.o
  443. In the example above the executable is composed of the C++ file
  444. qconf.cc - identified by $(qconf-cxxobjs).
  445. If qconf is composed by a mixture of .c and .cc files, then an
  446. additional line can be used to identify this.
  447. Example:
  448. #scripts/kconfig/Makefile
  449. hostprogs-y := qconf
  450. qconf-cxxobjs := qconf.o
  451. qconf-objs := check.o
  452. --- 4.5 Controlling compiler options for host programs
  453. When compiling host programs, it is possible to set specific flags.
  454. The programs will always be compiled utilising $(HOSTCC) passed
  455. the options specified in $(HOSTCFLAGS).
  456. To set flags that will take effect for all host programs created
  457. in that Makefile, use the variable HOST_EXTRACFLAGS.
  458. Example:
  459. #scripts/lxdialog/Makefile
  460. HOST_EXTRACFLAGS += -I/usr/include/ncurses
  461. To set specific flags for a single file the following construction
  462. is used:
  463. Example:
  464. #arch/ppc64/boot/Makefile
  465. HOSTCFLAGS_piggyback.o := -DKERNELBASE=$(KERNELBASE)
  466. It is also possible to specify additional options to the linker.
  467. Example:
  468. #scripts/kconfig/Makefile
  469. HOSTLOADLIBES_qconf := -L$(QTDIR)/lib
  470. When linking qconf, it will be passed the extra option
  471. "-L$(QTDIR)/lib".
  472. --- 4.6 When host programs are actually built
  473. Kbuild will only build host-programs when they are referenced
  474. as a prerequisite.
  475. This is possible in two ways:
  476. (1) List the prerequisite explicitly in a special rule.
  477. Example:
  478. #drivers/pci/Makefile
  479. hostprogs-y := gen-devlist
  480. $(obj)/devlist.h: $(src)/pci.ids $(obj)/gen-devlist
  481. ( cd $(obj); ./gen-devlist ) < $<
  482. The target $(obj)/devlist.h will not be built before
  483. $(obj)/gen-devlist is updated. Note that references to
  484. the host programs in special rules must be prefixed with $(obj).
  485. (2) Use $(always)
  486. When there is no suitable special rule, and the host program
  487. shall be built when a makefile is entered, the $(always)
  488. variable shall be used.
  489. Example:
  490. #scripts/lxdialog/Makefile
  491. hostprogs-y := lxdialog
  492. always := $(hostprogs-y)
  493. This will tell kbuild to build lxdialog even if not referenced in
  494. any rule.
  495. --- 4.7 Using hostprogs-$(CONFIG_FOO)
  496. A typical pattern in a Kbuild file looks like this:
  497. Example:
  498. #scripts/Makefile
  499. hostprogs-$(CONFIG_KALLSYMS) += kallsyms
  500. Kbuild knows about both 'y' for built-in and 'm' for module.
  501. So if a config symbol evaluate to 'm', kbuild will still build
  502. the binary. In other words, Kbuild handles hostprogs-m exactly
  503. like hostprogs-y. But only hostprogs-y is recommended to be used
  504. when no CONFIG symbols are involved.
  505. === 5 Kbuild clean infrastructure
  506. "make clean" deletes most generated files in the obj tree where the kernel
  507. is compiled. This includes generated files such as host programs.
  508. Kbuild knows targets listed in $(hostprogs-y), $(hostprogs-m), $(always),
  509. $(extra-y) and $(targets). They are all deleted during "make clean".
  510. Files matching the patterns "*.[oas]", "*.ko", plus some additional files
  511. generated by kbuild are deleted all over the kernel src tree when
  512. "make clean" is executed.
  513. Additional files can be specified in kbuild makefiles by use of $(clean-files).
  514. Example:
  515. #drivers/pci/Makefile
  516. clean-files := devlist.h classlist.h
  517. When executing "make clean", the two files "devlist.h classlist.h" will
  518. be deleted. Kbuild will assume files to be in same relative directory as the
  519. Makefile except if an absolute path is specified (path starting with '/').
  520. To delete a directory hierarchy use:
  521. Example:
  522. #scripts/package/Makefile
  523. clean-dirs := $(objtree)/debian/
  524. This will delete the directory debian, including all subdirectories.
  525. Kbuild will assume the directories to be in the same relative path as the
  526. Makefile if no absolute path is specified (path does not start with '/').
  527. Usually kbuild descends down in subdirectories due to "obj-* := dir/",
  528. but in the architecture makefiles where the kbuild infrastructure
  529. is not sufficient this sometimes needs to be explicit.
  530. Example:
  531. #arch/i386/boot/Makefile
  532. subdir- := compressed/
  533. The above assignment instructs kbuild to descend down in the
  534. directory compressed/ when "make clean" is executed.
  535. To support the clean infrastructure in the Makefiles that builds the
  536. final bootimage there is an optional target named archclean:
  537. Example:
  538. #arch/i386/Makefile
  539. archclean:
  540. $(Q)$(MAKE) $(clean)=arch/i386/boot
  541. When "make clean" is executed, make will descend down in arch/i386/boot,
  542. and clean as usual. The Makefile located in arch/i386/boot/ may use
  543. the subdir- trick to descend further down.
  544. Note 1: arch/$(ARCH)/Makefile cannot use "subdir-", because that file is
  545. included in the top level makefile, and the kbuild infrastructure
  546. is not operational at that point.
  547. Note 2: All directories listed in core-y, libs-y, drivers-y and net-y will
  548. be visited during "make clean".
  549. === 6 Architecture Makefiles
  550. The top level Makefile sets up the environment and does the preparation,
  551. before starting to descend down in the individual directories.
  552. The top level makefile contains the generic part, whereas
  553. arch/$(ARCH)/Makefile contains what is required to set up kbuild
  554. for said architecture.
  555. To do so, arch/$(ARCH)/Makefile sets up a number of variables and defines
  556. a few targets.
  557. When kbuild executes, the following steps are followed (roughly):
  558. 1) Configuration of the kernel => produce .config
  559. 2) Store kernel version in include/linux/version.h
  560. 3) Symlink include/asm to include/asm-$(ARCH)
  561. 4) Updating all other prerequisites to the target prepare:
  562. - Additional prerequisites are specified in arch/$(ARCH)/Makefile
  563. 5) Recursively descend down in all directories listed in
  564. init-* core* drivers-* net-* libs-* and build all targets.
  565. - The values of the above variables are expanded in arch/$(ARCH)/Makefile.
  566. 6) All object files are then linked and the resulting file vmlinux is
  567. located at the root of the obj tree.
  568. The very first objects linked are listed in head-y, assigned by
  569. arch/$(ARCH)/Makefile.
  570. 7) Finally, the architecture-specific part does any required post processing
  571. and builds the final bootimage.
  572. - This includes building boot records
  573. - Preparing initrd images and the like
  574. --- 6.1 Set variables to tweak the build to the architecture
  575. LDFLAGS Generic $(LD) options
  576. Flags used for all invocations of the linker.
  577. Often specifying the emulation is sufficient.
  578. Example:
  579. #arch/s390/Makefile
  580. LDFLAGS := -m elf_s390
  581. Note: EXTRA_LDFLAGS and LDFLAGS_$@ can be used to further customise
  582. the flags used. See chapter 7.
  583. LDFLAGS_MODULE Options for $(LD) when linking modules
  584. LDFLAGS_MODULE is used to set specific flags for $(LD) when
  585. linking the .ko files used for modules.
  586. Default is "-r", for relocatable output.
  587. LDFLAGS_vmlinux Options for $(LD) when linking vmlinux
  588. LDFLAGS_vmlinux is used to specify additional flags to pass to
  589. the linker when linking the final vmlinux image.
  590. LDFLAGS_vmlinux uses the LDFLAGS_$@ support.
  591. Example:
  592. #arch/i386/Makefile
  593. LDFLAGS_vmlinux := -e stext
  594. OBJCOPYFLAGS objcopy flags
  595. When $(call if_changed,objcopy) is used to translate a .o file,
  596. the flags specified in OBJCOPYFLAGS will be used.
  597. $(call if_changed,objcopy) is often used to generate raw binaries on
  598. vmlinux.
  599. Example:
  600. #arch/s390/Makefile
  601. OBJCOPYFLAGS := -O binary
  602. #arch/s390/boot/Makefile
  603. $(obj)/image: vmlinux FORCE
  604. $(call if_changed,objcopy)
  605. In this example, the binary $(obj)/image is a binary version of
  606. vmlinux. The usage of $(call if_changed,xxx) will be described later.
  607. AFLAGS $(AS) assembler flags
  608. Default value - see top level Makefile
  609. Append or modify as required per architecture.
  610. Example:
  611. #arch/sparc64/Makefile
  612. AFLAGS += -m64 -mcpu=ultrasparc
  613. CFLAGS $(CC) compiler flags
  614. Default value - see top level Makefile
  615. Append or modify as required per architecture.
  616. Often, the CFLAGS variable depends on the configuration.
  617. Example:
  618. #arch/i386/Makefile
  619. cflags-$(CONFIG_M386) += -march=i386
  620. CFLAGS += $(cflags-y)
  621. Many arch Makefiles dynamically run the target C compiler to
  622. probe supported options:
  623. #arch/i386/Makefile
  624. ...
  625. cflags-$(CONFIG_MPENTIUMII) += $(call cc-option,\
  626. -march=pentium2,-march=i686)
  627. ...
  628. # Disable unit-at-a-time mode ...
  629. CFLAGS += $(call cc-option,-fno-unit-at-a-time)
  630. ...
  631. The first example utilises the trick that a config option expands
  632. to 'y' when selected.
  633. CFLAGS_KERNEL $(CC) options specific for built-in
  634. $(CFLAGS_KERNEL) contains extra C compiler flags used to compile
  635. resident kernel code.
  636. CFLAGS_MODULE $(CC) options specific for modules
  637. $(CFLAGS_MODULE) contains extra C compiler flags used to compile code
  638. for loadable kernel modules.
  639. --- 6.2 Add prerequisites to archprepare:
  640. The archprepare: rule is used to list prerequisites that need to be
  641. built before starting to descend down in the subdirectories.
  642. This is usually used for header files containing assembler constants.
  643. Example:
  644. #arch/arm/Makefile
  645. archprepare: maketools
  646. In this example, the file target maketools will be processed
  647. before descending down in the subdirectories.
  648. See also chapter XXX-TODO that describe how kbuild supports
  649. generating offset header files.
  650. --- 6.3 List directories to visit when descending
  651. An arch Makefile cooperates with the top Makefile to define variables
  652. which specify how to build the vmlinux file. Note that there is no
  653. corresponding arch-specific section for modules; the module-building
  654. machinery is all architecture-independent.
  655. head-y, init-y, core-y, libs-y, drivers-y, net-y
  656. $(head-y) lists objects to be linked first in vmlinux.
  657. $(libs-y) lists directories where a lib.a archive can be located.
  658. The rest list directories where a built-in.o object file can be
  659. located.
  660. $(init-y) objects will be located after $(head-y).
  661. Then the rest follows in this order:
  662. $(core-y), $(libs-y), $(drivers-y) and $(net-y).
  663. The top level Makefile defines values for all generic directories,
  664. and arch/$(ARCH)/Makefile only adds architecture-specific directories.
  665. Example:
  666. #arch/sparc64/Makefile
  667. core-y += arch/sparc64/kernel/
  668. libs-y += arch/sparc64/prom/ arch/sparc64/lib/
  669. drivers-$(CONFIG_OPROFILE) += arch/sparc64/oprofile/
  670. --- 6.4 Architecture-specific boot images
  671. An arch Makefile specifies goals that take the vmlinux file, compress
  672. it, wrap it in bootstrapping code, and copy the resulting files
  673. somewhere. This includes various kinds of installation commands.
  674. The actual goals are not standardized across architectures.
  675. It is common to locate any additional processing in a boot/
  676. directory below arch/$(ARCH)/.
  677. Kbuild does not provide any smart way to support building a
  678. target specified in boot/. Therefore arch/$(ARCH)/Makefile shall
  679. call make manually to build a target in boot/.
  680. The recommended approach is to include shortcuts in
  681. arch/$(ARCH)/Makefile, and use the full path when calling down
  682. into the arch/$(ARCH)/boot/Makefile.
  683. Example:
  684. #arch/i386/Makefile
  685. boot := arch/i386/boot
  686. bzImage: vmlinux
  687. $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
  688. "$(Q)$(MAKE) $(build)=<dir>" is the recommended way to invoke
  689. make in a subdirectory.
  690. There are no rules for naming architecture-specific targets,
  691. but executing "make help" will list all relevant targets.
  692. To support this, $(archhelp) must be defined.
  693. Example:
  694. #arch/i386/Makefile
  695. define archhelp
  696. echo '* bzImage - Image (arch/$(ARCH)/boot/bzImage)'
  697. endif
  698. When make is executed without arguments, the first goal encountered
  699. will be built. In the top level Makefile the first goal present
  700. is all:.
  701. An architecture shall always, per default, build a bootable image.
  702. In "make help", the default goal is highlighted with a '*'.
  703. Add a new prerequisite to all: to select a default goal different
  704. from vmlinux.
  705. Example:
  706. #arch/i386/Makefile
  707. all: bzImage
  708. When "make" is executed without arguments, bzImage will be built.
  709. --- 6.5 Building non-kbuild targets
  710. extra-y
  711. extra-y specify additional targets created in the current
  712. directory, in addition to any targets specified by obj-*.
  713. Listing all targets in extra-y is required for two purposes:
  714. 1) Enable kbuild to check changes in command lines
  715. - When $(call if_changed,xxx) is used
  716. 2) kbuild knows what files to delete during "make clean"
  717. Example:
  718. #arch/i386/kernel/Makefile
  719. extra-y := head.o init_task.o
  720. In this example, extra-y is used to list object files that
  721. shall be built, but shall not be linked as part of built-in.o.
  722. --- 6.6 Commands useful for building a boot image
  723. Kbuild provides a few macros that are useful when building a
  724. boot image.
  725. if_changed
  726. if_changed is the infrastructure used for the following commands.
  727. Usage:
  728. target: source(s) FORCE
  729. $(call if_changed,ld/objcopy/gzip)
  730. When the rule is evaluated, it is checked to see if any files
  731. need an update, or the command line has changed since the last
  732. invocation. The latter will force a rebuild if any options
  733. to the executable have changed.
  734. Any target that utilises if_changed must be listed in $(targets),
  735. otherwise the command line check will fail, and the target will
  736. always be built.
  737. Assignments to $(targets) are without $(obj)/ prefix.
  738. if_changed may be used in conjunction with custom commands as
  739. defined in 6.7 "Custom kbuild commands".
  740. Note: It is a typical mistake to forget the FORCE prerequisite.
  741. Another common pitfall is that whitespace is sometimes
  742. significant; for instance, the below will fail (note the extra space
  743. after the comma):
  744. target: source(s) FORCE
  745. #WRONG!# $(call if_changed, ld/objcopy/gzip)
  746. ld
  747. Link target. Often, LDFLAGS_$@ is used to set specific options to ld.
  748. objcopy
  749. Copy binary. Uses OBJCOPYFLAGS usually specified in
  750. arch/$(ARCH)/Makefile.
  751. OBJCOPYFLAGS_$@ may be used to set additional options.
  752. gzip
  753. Compress target. Use maximum compression to compress target.
  754. Example:
  755. #arch/i386/boot/Makefile
  756. LDFLAGS_bootsect := -Ttext 0x0 -s --oformat binary
  757. LDFLAGS_setup := -Ttext 0x0 -s --oformat binary -e begtext
  758. targets += setup setup.o bootsect bootsect.o
  759. $(obj)/setup $(obj)/bootsect: %: %.o FORCE
  760. $(call if_changed,ld)
  761. In this example, there are two possible targets, requiring different
  762. options to the linker. The linker options are specified using the
  763. LDFLAGS_$@ syntax - one for each potential target.
  764. $(targets) are assigned all potential targets, by which kbuild knows
  765. the targets and will:
  766. 1) check for commandline changes
  767. 2) delete target during make clean
  768. The ": %: %.o" part of the prerequisite is a shorthand that
  769. free us from listing the setup.o and bootsect.o files.
  770. Note: It is a common mistake to forget the "target :=" assignment,
  771. resulting in the target file being recompiled for no
  772. obvious reason.
  773. --- 6.7 Custom kbuild commands
  774. When kbuild is executing with KBUILD_VERBOSE=0, then only a shorthand
  775. of a command is normally displayed.
  776. To enable this behaviour for custom commands kbuild requires
  777. two variables to be set:
  778. quiet_cmd_<command> - what shall be echoed
  779. cmd_<command> - the command to execute
  780. Example:
  781. #
  782. quiet_cmd_image = BUILD $@
  783. cmd_image = $(obj)/tools/build $(BUILDFLAGS) \
  784. $(obj)/vmlinux.bin > $@
  785. targets += bzImage
  786. $(obj)/bzImage: $(obj)/vmlinux.bin $(obj)/tools/build FORCE
  787. $(call if_changed,image)
  788. @echo 'Kernel: $@ is ready'
  789. When updating the $(obj)/bzImage target, the line
  790. BUILD arch/i386/boot/bzImage
  791. will be displayed with "make KBUILD_VERBOSE=0".
  792. --- 6.8 Preprocessing linker scripts
  793. When the vmlinux image is built, the linker script
  794. arch/$(ARCH)/kernel/vmlinux.lds is used.
  795. The script is a preprocessed variant of the file vmlinux.lds.S
  796. located in the same directory.
  797. kbuild knows .lds files and includes a rule *lds.S -> *lds.
  798. Example:
  799. #arch/i386/kernel/Makefile
  800. always := vmlinux.lds
  801. #Makefile
  802. export CPPFLAGS_vmlinux.lds += -P -C -U$(ARCH)
  803. The assignment to $(always) is used to tell kbuild to build the
  804. target vmlinux.lds.
  805. The assignment to $(CPPFLAGS_vmlinux.lds) tells kbuild to use the
  806. specified options when building the target vmlinux.lds.
  807. When building the *.lds target, kbuild uses the variables:
  808. CPPFLAGS : Set in top-level Makefile
  809. EXTRA_CPPFLAGS : May be set in the kbuild makefile
  810. CPPFLAGS_$(@F) : Target specific flags.
  811. Note that the full filename is used in this
  812. assignment.
  813. The kbuild infrastructure for *lds file are used in several
  814. architecture-specific files.
  815. === 7 Kbuild Variables
  816. The top Makefile exports the following variables:
  817. VERSION, PATCHLEVEL, SUBLEVEL, EXTRAVERSION
  818. These variables define the current kernel version. A few arch
  819. Makefiles actually use these values directly; they should use
  820. $(KERNELRELEASE) instead.
  821. $(VERSION), $(PATCHLEVEL), and $(SUBLEVEL) define the basic
  822. three-part version number, such as "2", "4", and "0". These three
  823. values are always numeric.
  824. $(EXTRAVERSION) defines an even tinier sublevel for pre-patches
  825. or additional patches. It is usually some non-numeric string
  826. such as "-pre4", and is often blank.
  827. KERNELRELEASE
  828. $(KERNELRELEASE) is a single string such as "2.4.0-pre4", suitable
  829. for constructing installation directory names or showing in
  830. version strings. Some arch Makefiles use it for this purpose.
  831. ARCH
  832. This variable defines the target architecture, such as "i386",
  833. "arm", or "sparc". Some kbuild Makefiles test $(ARCH) to
  834. determine which files to compile.
  835. By default, the top Makefile sets $(ARCH) to be the same as the
  836. host system architecture. For a cross build, a user may
  837. override the value of $(ARCH) on the command line:
  838. make ARCH=m68k ...
  839. INSTALL_PATH
  840. This variable defines a place for the arch Makefiles to install
  841. the resident kernel image and System.map file.
  842. Use this for architecture-specific install targets.
  843. INSTALL_MOD_PATH, MODLIB
  844. $(INSTALL_MOD_PATH) specifies a prefix to $(MODLIB) for module
  845. installation. This variable is not defined in the Makefile but
  846. may be passed in by the user if desired.
  847. $(MODLIB) specifies the directory for module installation.
  848. The top Makefile defines $(MODLIB) to
  849. $(INSTALL_MOD_PATH)/lib/modules/$(KERNELRELEASE). The user may
  850. override this value on the command line if desired.
  851. INSTALL_MOD_STRIP
  852. If this variable is specified, will cause modules to be stripped
  853. after they are installed. If INSTALL_MOD_STRIP is '1', then the
  854. default option --strip-debug will be used. Otherwise,
  855. INSTALL_MOD_STRIP will used as the option(s) to the strip command.
  856. === 8 Makefile language
  857. The kernel Makefiles are designed to be run with GNU Make. The Makefiles
  858. use only the documented features of GNU Make, but they do use many
  859. GNU extensions.
  860. GNU Make supports elementary list-processing functions. The kernel
  861. Makefiles use a novel style of list building and manipulation with few
  862. "if" statements.
  863. GNU Make has two assignment operators, ":=" and "=". ":=" performs
  864. immediate evaluation of the right-hand side and stores an actual string
  865. into the left-hand side. "=" is like a formula definition; it stores the
  866. right-hand side in an unevaluated form and then evaluates this form each
  867. time the left-hand side is used.
  868. There are some cases where "=" is appropriate. Usually, though, ":="
  869. is the right choice.
  870. === 9 Credits
  871. Original version made by Michael Elizabeth Chastain, <mailto:mec@shout.net>
  872. Updates by Kai Germaschewski <kai@tp1.ruhr-uni-bochum.de>
  873. Updates by Sam Ravnborg <sam@ravnborg.org>
  874. Language QA by Jan Engelhardt <jengelh@gmx.de>
  875. === 10 TODO
  876. - Describe how kbuild supports shipped files with _shipped.
  877. - Generating offset header files.
  878. - Add more variables to section 7?