io_ordering.txt 1.9 KB

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  1. On some platforms, so-called memory-mapped I/O is weakly ordered. On such
  2. platforms, driver writers are responsible for ensuring that I/O writes to
  3. memory-mapped addresses on their device arrive in the order intended. This is
  4. typically done by reading a 'safe' device or bridge register, causing the I/O
  5. chipset to flush pending writes to the device before any reads are posted. A
  6. driver would usually use this technique immediately prior to the exit of a
  7. critical section of code protected by spinlocks. This would ensure that
  8. subsequent writes to I/O space arrived only after all prior writes (much like a
  9. memory barrier op, mb(), only with respect to I/O).
  10. A more concrete example from a hypothetical device driver:
  11. ...
  12. CPU A: spin_lock_irqsave(&dev_lock, flags)
  13. CPU A: val = readl(my_status);
  14. CPU A: ...
  15. CPU A: writel(newval, ring_ptr);
  16. CPU A: spin_unlock_irqrestore(&dev_lock, flags)
  17. ...
  18. CPU B: spin_lock_irqsave(&dev_lock, flags)
  19. CPU B: val = readl(my_status);
  20. CPU B: ...
  21. CPU B: writel(newval2, ring_ptr);
  22. CPU B: spin_unlock_irqrestore(&dev_lock, flags)
  23. ...
  24. In the case above, the device may receive newval2 before it receives newval,
  25. which could cause problems. Fixing it is easy enough though:
  26. ...
  27. CPU A: spin_lock_irqsave(&dev_lock, flags)
  28. CPU A: val = readl(my_status);
  29. CPU A: ...
  30. CPU A: writel(newval, ring_ptr);
  31. CPU A: (void)readl(safe_register); /* maybe a config register? */
  32. CPU A: spin_unlock_irqrestore(&dev_lock, flags)
  33. ...
  34. CPU B: spin_lock_irqsave(&dev_lock, flags)
  35. CPU B: val = readl(my_status);
  36. CPU B: ...
  37. CPU B: writel(newval2, ring_ptr);
  38. CPU B: (void)readl(safe_register); /* maybe a config register? */
  39. CPU B: spin_unlock_irqrestore(&dev_lock, flags)
  40. Here, the reads from safe_register will cause the I/O chipset to flush any
  41. pending writes before actually posting the read to the chipset, preventing
  42. possible data corruption.