smbus-protocol 6.4 KB

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  1. SMBus Protocol Summary
  2. ======================
  3. The following is a summary of the SMBus protocol. It applies to
  4. all revisions of the protocol (1.0, 1.1, and 2.0).
  5. Certain protocol features which are not supported by
  6. this package are briefly described at the end of this document.
  7. Some adapters understand only the SMBus (System Management Bus) protocol,
  8. which is a subset from the I2C protocol. Fortunately, many devices use
  9. only the same subset, which makes it possible to put them on an SMBus.
  10. If you write a driver for some I2C device, please try to use the SMBus
  11. commands if at all possible (if the device uses only that subset of the
  12. I2C protocol). This makes it possible to use the device driver on both
  13. SMBus adapters and I2C adapters (the SMBus command set is automatically
  14. translated to I2C on I2C adapters, but plain I2C commands can not be
  15. handled at all on most pure SMBus adapters).
  16. Below is a list of SMBus commands.
  17. Key to symbols
  18. ==============
  19. S (1 bit) : Start bit
  20. P (1 bit) : Stop bit
  21. Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0.
  22. A, NA (1 bit) : Accept and reverse accept bit.
  23. Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to
  24. get a 10 bit I2C address.
  25. Comm (8 bits): Command byte, a data byte which often selects a register on
  26. the device.
  27. Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh
  28. for 16 bit data.
  29. Count (8 bits): A data byte containing the length of a block operation.
  30. [..]: Data sent by I2C device, as opposed to data sent by the host adapter.
  31. SMBus Write Quick
  32. =================
  33. This sends a single bit to the device, at the place of the Rd/Wr bit.
  34. There is no equivalent Read Quick command.
  35. A Addr Rd/Wr [A] P
  36. SMBus Read Byte
  37. ===============
  38. This reads a single byte from a device, without specifying a device
  39. register. Some devices are so simple that this interface is enough; for
  40. others, it is a shorthand if you want to read the same register as in
  41. the previous SMBus command.
  42. S Addr Rd [A] [Data] NA P
  43. SMBus Write Byte
  44. ================
  45. This is the reverse of Read Byte: it sends a single byte to a device.
  46. See Read Byte for more information.
  47. S Addr Wr [A] Data [A] P
  48. SMBus Read Byte Data
  49. ====================
  50. This reads a single byte from a device, from a designated register.
  51. The register is specified through the Comm byte.
  52. S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P
  53. SMBus Read Word Data
  54. ====================
  55. This command is very like Read Byte Data; again, data is read from a
  56. device, from a designated register that is specified through the Comm
  57. byte. But this time, the data is a complete word (16 bits).
  58. S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P
  59. SMBus Write Byte Data
  60. =====================
  61. This writes a single byte to a device, to a designated register. The
  62. register is specified through the Comm byte. This is the opposite of
  63. the Read Byte Data command.
  64. S Addr Wr [A] Comm [A] Data [A] P
  65. SMBus Write Word Data
  66. =====================
  67. This is the opposite operation of the Read Word Data command. 16 bits
  68. of data is written to a device, to the designated register that is
  69. specified through the Comm byte.
  70. S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P
  71. SMBus Process Call
  72. ==================
  73. This command selects a device register (through the Comm byte), sends
  74. 16 bits of data to it, and reads 16 bits of data in return.
  75. S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A]
  76. S Addr Rd [A] [DataLow] A [DataHigh] NA P
  77. SMBus Block Read
  78. ================
  79. This command reads a block of up to 32 bytes from a device, from a
  80. designated register that is specified through the Comm byte. The amount
  81. of data is specified by the device in the Count byte.
  82. S Addr Wr [A] Comm [A]
  83. S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
  84. SMBus Block Write
  85. =================
  86. The opposite of the Block Read command, this writes up to 32 bytes to
  87. a device, to a designated register that is specified through the
  88. Comm byte. The amount of data is specified in the Count byte.
  89. S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P
  90. SMBus Block Process Call
  91. ========================
  92. SMBus Block Process Call was introduced in Revision 2.0 of the specification.
  93. This command selects a device register (through the Comm byte), sends
  94. 1 to 31 bytes of data to it, and reads 1 to 31 bytes of data in return.
  95. S Addr Wr [A] Comm [A] Count [A] Data [A] ...
  96. S Addr Rd [A] [Count] A [Data] ... A P
  97. SMBus Host Notify
  98. =================
  99. This command is sent from a SMBus device acting as a master to the
  100. SMBus host acting as a slave.
  101. It is the same form as Write Word, with the command code replaced by the
  102. alerting device's address.
  103. [S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P]
  104. Packet Error Checking (PEC)
  105. ===========================
  106. Packet Error Checking was introduced in Revision 1.1 of the specification.
  107. PEC adds a CRC-8 error-checking byte to all transfers.
  108. Address Resolution Protocol (ARP)
  109. =================================
  110. The Address Resolution Protocol was introduced in Revision 2.0 of
  111. the specification. It is a higher-layer protocol which uses the
  112. messages above.
  113. ARP adds device enumeration and dynamic address assignment to
  114. the protocol. All ARP communications use slave address 0x61 and
  115. require PEC checksums.
  116. I2C Block Transactions
  117. ======================
  118. The following I2C block transactions are supported by the
  119. SMBus layer and are described here for completeness.
  120. I2C block transactions do not limit the number of bytes transferred
  121. but the SMBus layer places a limit of 32 bytes.
  122. I2C Block Read
  123. ==============
  124. This command reads a block of bytes from a device, from a
  125. designated register that is specified through the Comm byte.
  126. S Addr Wr [A] Comm [A]
  127. S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
  128. I2C Block Read (2 Comm bytes)
  129. =============================
  130. This command reads a block of bytes from a device, from a
  131. designated register that is specified through the two Comm bytes.
  132. S Addr Wr [A] Comm1 [A] Comm2 [A]
  133. S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
  134. I2C Block Write
  135. ===============
  136. The opposite of the Block Read command, this writes bytes to
  137. a device, to a designated register that is specified through the
  138. Comm byte. Note that command lengths of 0, 2, or more bytes are
  139. supported as they are indistinguishable from data.
  140. S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P