cachetlb.txt 17 KB

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  1. Cache and TLB Flushing
  2. Under Linux
  3. David S. Miller <davem@redhat.com>
  4. This document describes the cache/tlb flushing interfaces called
  5. by the Linux VM subsystem. It enumerates over each interface,
  6. describes it's intended purpose, and what side effect is expected
  7. after the interface is invoked.
  8. The side effects described below are stated for a uniprocessor
  9. implementation, and what is to happen on that single processor. The
  10. SMP cases are a simple extension, in that you just extend the
  11. definition such that the side effect for a particular interface occurs
  12. on all processors in the system. Don't let this scare you into
  13. thinking SMP cache/tlb flushing must be so inefficient, this is in
  14. fact an area where many optimizations are possible. For example,
  15. if it can be proven that a user address space has never executed
  16. on a cpu (see vma->cpu_vm_mask), one need not perform a flush
  17. for this address space on that cpu.
  18. First, the TLB flushing interfaces, since they are the simplest. The
  19. "TLB" is abstracted under Linux as something the cpu uses to cache
  20. virtual-->physical address translations obtained from the software
  21. page tables. Meaning that if the software page tables change, it is
  22. possible for stale translations to exist in this "TLB" cache.
  23. Therefore when software page table changes occur, the kernel will
  24. invoke one of the following flush methods _after_ the page table
  25. changes occur:
  26. 1) void flush_tlb_all(void)
  27. The most severe flush of all. After this interface runs,
  28. any previous page table modification whatsoever will be
  29. visible to the cpu.
  30. This is usually invoked when the kernel page tables are
  31. changed, since such translations are "global" in nature.
  32. 2) void flush_tlb_mm(struct mm_struct *mm)
  33. This interface flushes an entire user address space from
  34. the TLB. After running, this interface must make sure that
  35. any previous page table modifications for the address space
  36. 'mm' will be visible to the cpu. That is, after running,
  37. there will be no entries in the TLB for 'mm'.
  38. This interface is used to handle whole address space
  39. page table operations such as what happens during
  40. fork, and exec.
  41. 3) void flush_tlb_range(struct vm_area_struct *vma,
  42. unsigned long start, unsigned long end)
  43. Here we are flushing a specific range of (user) virtual
  44. address translations from the TLB. After running, this
  45. interface must make sure that any previous page table
  46. modifications for the address space 'vma->vm_mm' in the range
  47. 'start' to 'end-1' will be visible to the cpu. That is, after
  48. running, here will be no entries in the TLB for 'mm' for
  49. virtual addresses in the range 'start' to 'end-1'.
  50. The "vma" is the backing store being used for the region.
  51. Primarily, this is used for munmap() type operations.
  52. The interface is provided in hopes that the port can find
  53. a suitably efficient method for removing multiple page
  54. sized translations from the TLB, instead of having the kernel
  55. call flush_tlb_page (see below) for each entry which may be
  56. modified.
  57. 4) void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
  58. This time we need to remove the PAGE_SIZE sized translation
  59. from the TLB. The 'vma' is the backing structure used by
  60. Linux to keep track of mmap'd regions for a process, the
  61. address space is available via vma->vm_mm. Also, one may
  62. test (vma->vm_flags & VM_EXEC) to see if this region is
  63. executable (and thus could be in the 'instruction TLB' in
  64. split-tlb type setups).
  65. After running, this interface must make sure that any previous
  66. page table modification for address space 'vma->vm_mm' for
  67. user virtual address 'addr' will be visible to the cpu. That
  68. is, after running, there will be no entries in the TLB for
  69. 'vma->vm_mm' for virtual address 'addr'.
  70. This is used primarily during fault processing.
  71. 5) void flush_tlb_pgtables(struct mm_struct *mm,
  72. unsigned long start, unsigned long end)
  73. The software page tables for address space 'mm' for virtual
  74. addresses in the range 'start' to 'end-1' are being torn down.
  75. Some platforms cache the lowest level of the software page tables
  76. in a linear virtually mapped array, to make TLB miss processing
  77. more efficient. On such platforms, since the TLB is caching the
  78. software page table structure, it needs to be flushed when parts
  79. of the software page table tree are unlinked/freed.
  80. Sparc64 is one example of a platform which does this.
  81. Usually, when munmap()'ing an area of user virtual address
  82. space, the kernel leaves the page table parts around and just
  83. marks the individual pte's as invalid. However, if very large
  84. portions of the address space are unmapped, the kernel frees up
  85. those portions of the software page tables to prevent potential
  86. excessive kernel memory usage caused by erratic mmap/mmunmap
  87. sequences. It is at these times that flush_tlb_pgtables will
  88. be invoked.
  89. 6) void update_mmu_cache(struct vm_area_struct *vma,
  90. unsigned long address, pte_t pte)
  91. At the end of every page fault, this routine is invoked to
  92. tell the architecture specific code that a translation
  93. described by "pte" now exists at virtual address "address"
  94. for address space "vma->vm_mm", in the software page tables.
  95. A port may use this information in any way it so chooses.
  96. For example, it could use this event to pre-load TLB
  97. translations for software managed TLB configurations.
  98. The sparc64 port currently does this.
  99. 7) void tlb_migrate_finish(struct mm_struct *mm)
  100. This interface is called at the end of an explicit
  101. process migration. This interface provides a hook
  102. to allow a platform to update TLB or context-specific
  103. information for the address space.
  104. The ia64 sn2 platform is one example of a platform
  105. that uses this interface.
  106. 8) void lazy_mmu_prot_update(pte_t pte)
  107. This interface is called whenever the protection on
  108. any user PTEs change. This interface provides a notification
  109. to architecture specific code to take appropriate action.
  110. Next, we have the cache flushing interfaces. In general, when Linux
  111. is changing an existing virtual-->physical mapping to a new value,
  112. the sequence will be in one of the following forms:
  113. 1) flush_cache_mm(mm);
  114. change_all_page_tables_of(mm);
  115. flush_tlb_mm(mm);
  116. 2) flush_cache_range(vma, start, end);
  117. change_range_of_page_tables(mm, start, end);
  118. flush_tlb_range(vma, start, end);
  119. 3) flush_cache_page(vma, addr, pfn);
  120. set_pte(pte_pointer, new_pte_val);
  121. flush_tlb_page(vma, addr);
  122. The cache level flush will always be first, because this allows
  123. us to properly handle systems whose caches are strict and require
  124. a virtual-->physical translation to exist for a virtual address
  125. when that virtual address is flushed from the cache. The HyperSparc
  126. cpu is one such cpu with this attribute.
  127. The cache flushing routines below need only deal with cache flushing
  128. to the extent that it is necessary for a particular cpu. Mostly,
  129. these routines must be implemented for cpus which have virtually
  130. indexed caches which must be flushed when virtual-->physical
  131. translations are changed or removed. So, for example, the physically
  132. indexed physically tagged caches of IA32 processors have no need to
  133. implement these interfaces since the caches are fully synchronized
  134. and have no dependency on translation information.
  135. Here are the routines, one by one:
  136. 1) void flush_cache_mm(struct mm_struct *mm)
  137. This interface flushes an entire user address space from
  138. the caches. That is, after running, there will be no cache
  139. lines associated with 'mm'.
  140. This interface is used to handle whole address space
  141. page table operations such as what happens during exit and exec.
  142. 2) void flush_cache_dup_mm(struct mm_struct *mm)
  143. This interface flushes an entire user address space from
  144. the caches. That is, after running, there will be no cache
  145. lines associated with 'mm'.
  146. This interface is used to handle whole address space
  147. page table operations such as what happens during fork.
  148. This option is separate from flush_cache_mm to allow some
  149. optimizations for VIPT caches.
  150. 3) void flush_cache_range(struct vm_area_struct *vma,
  151. unsigned long start, unsigned long end)
  152. Here we are flushing a specific range of (user) virtual
  153. addresses from the cache. After running, there will be no
  154. entries in the cache for 'vma->vm_mm' for virtual addresses in
  155. the range 'start' to 'end-1'.
  156. The "vma" is the backing store being used for the region.
  157. Primarily, this is used for munmap() type operations.
  158. The interface is provided in hopes that the port can find
  159. a suitably efficient method for removing multiple page
  160. sized regions from the cache, instead of having the kernel
  161. call flush_cache_page (see below) for each entry which may be
  162. modified.
  163. 4) void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn)
  164. This time we need to remove a PAGE_SIZE sized range
  165. from the cache. The 'vma' is the backing structure used by
  166. Linux to keep track of mmap'd regions for a process, the
  167. address space is available via vma->vm_mm. Also, one may
  168. test (vma->vm_flags & VM_EXEC) to see if this region is
  169. executable (and thus could be in the 'instruction cache' in
  170. "Harvard" type cache layouts).
  171. The 'pfn' indicates the physical page frame (shift this value
  172. left by PAGE_SHIFT to get the physical address) that 'addr'
  173. translates to. It is this mapping which should be removed from
  174. the cache.
  175. After running, there will be no entries in the cache for
  176. 'vma->vm_mm' for virtual address 'addr' which translates
  177. to 'pfn'.
  178. This is used primarily during fault processing.
  179. 5) void flush_cache_kmaps(void)
  180. This routine need only be implemented if the platform utilizes
  181. highmem. It will be called right before all of the kmaps
  182. are invalidated.
  183. After running, there will be no entries in the cache for
  184. the kernel virtual address range PKMAP_ADDR(0) to
  185. PKMAP_ADDR(LAST_PKMAP).
  186. This routing should be implemented in asm/highmem.h
  187. 6) void flush_cache_vmap(unsigned long start, unsigned long end)
  188. void flush_cache_vunmap(unsigned long start, unsigned long end)
  189. Here in these two interfaces we are flushing a specific range
  190. of (kernel) virtual addresses from the cache. After running,
  191. there will be no entries in the cache for the kernel address
  192. space for virtual addresses in the range 'start' to 'end-1'.
  193. The first of these two routines is invoked after map_vm_area()
  194. has installed the page table entries. The second is invoked
  195. before unmap_vm_area() deletes the page table entries.
  196. There exists another whole class of cpu cache issues which currently
  197. require a whole different set of interfaces to handle properly.
  198. The biggest problem is that of virtual aliasing in the data cache
  199. of a processor.
  200. Is your port susceptible to virtual aliasing in it's D-cache?
  201. Well, if your D-cache is virtually indexed, is larger in size than
  202. PAGE_SIZE, and does not prevent multiple cache lines for the same
  203. physical address from existing at once, you have this problem.
  204. If your D-cache has this problem, first define asm/shmparam.h SHMLBA
  205. properly, it should essentially be the size of your virtually
  206. addressed D-cache (or if the size is variable, the largest possible
  207. size). This setting will force the SYSv IPC layer to only allow user
  208. processes to mmap shared memory at address which are a multiple of
  209. this value.
  210. NOTE: This does not fix shared mmaps, check out the sparc64 port for
  211. one way to solve this (in particular SPARC_FLAG_MMAPSHARED).
  212. Next, you have to solve the D-cache aliasing issue for all
  213. other cases. Please keep in mind that fact that, for a given page
  214. mapped into some user address space, there is always at least one more
  215. mapping, that of the kernel in it's linear mapping starting at
  216. PAGE_OFFSET. So immediately, once the first user maps a given
  217. physical page into its address space, by implication the D-cache
  218. aliasing problem has the potential to exist since the kernel already
  219. maps this page at its virtual address.
  220. void copy_user_page(void *to, void *from, unsigned long addr, struct page *page)
  221. void clear_user_page(void *to, unsigned long addr, struct page *page)
  222. These two routines store data in user anonymous or COW
  223. pages. It allows a port to efficiently avoid D-cache alias
  224. issues between userspace and the kernel.
  225. For example, a port may temporarily map 'from' and 'to' to
  226. kernel virtual addresses during the copy. The virtual address
  227. for these two pages is chosen in such a way that the kernel
  228. load/store instructions happen to virtual addresses which are
  229. of the same "color" as the user mapping of the page. Sparc64
  230. for example, uses this technique.
  231. The 'addr' parameter tells the virtual address where the
  232. user will ultimately have this page mapped, and the 'page'
  233. parameter gives a pointer to the struct page of the target.
  234. If D-cache aliasing is not an issue, these two routines may
  235. simply call memcpy/memset directly and do nothing more.
  236. void flush_dcache_page(struct page *page)
  237. Any time the kernel writes to a page cache page, _OR_
  238. the kernel is about to read from a page cache page and
  239. user space shared/writable mappings of this page potentially
  240. exist, this routine is called.
  241. NOTE: This routine need only be called for page cache pages
  242. which can potentially ever be mapped into the address
  243. space of a user process. So for example, VFS layer code
  244. handling vfs symlinks in the page cache need not call
  245. this interface at all.
  246. The phrase "kernel writes to a page cache page" means,
  247. specifically, that the kernel executes store instructions
  248. that dirty data in that page at the page->virtual mapping
  249. of that page. It is important to flush here to handle
  250. D-cache aliasing, to make sure these kernel stores are
  251. visible to user space mappings of that page.
  252. The corollary case is just as important, if there are users
  253. which have shared+writable mappings of this file, we must make
  254. sure that kernel reads of these pages will see the most recent
  255. stores done by the user.
  256. If D-cache aliasing is not an issue, this routine may
  257. simply be defined as a nop on that architecture.
  258. There is a bit set aside in page->flags (PG_arch_1) as
  259. "architecture private". The kernel guarantees that,
  260. for pagecache pages, it will clear this bit when such
  261. a page first enters the pagecache.
  262. This allows these interfaces to be implemented much more
  263. efficiently. It allows one to "defer" (perhaps indefinitely)
  264. the actual flush if there are currently no user processes
  265. mapping this page. See sparc64's flush_dcache_page and
  266. update_mmu_cache implementations for an example of how to go
  267. about doing this.
  268. The idea is, first at flush_dcache_page() time, if
  269. page->mapping->i_mmap is an empty tree and ->i_mmap_nonlinear
  270. an empty list, just mark the architecture private page flag bit.
  271. Later, in update_mmu_cache(), a check is made of this flag bit,
  272. and if set the flush is done and the flag bit is cleared.
  273. IMPORTANT NOTE: It is often important, if you defer the flush,
  274. that the actual flush occurs on the same CPU
  275. as did the cpu stores into the page to make it
  276. dirty. Again, see sparc64 for examples of how
  277. to deal with this.
  278. void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
  279. unsigned long user_vaddr,
  280. void *dst, void *src, int len)
  281. void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
  282. unsigned long user_vaddr,
  283. void *dst, void *src, int len)
  284. When the kernel needs to copy arbitrary data in and out
  285. of arbitrary user pages (f.e. for ptrace()) it will use
  286. these two routines.
  287. Any necessary cache flushing or other coherency operations
  288. that need to occur should happen here. If the processor's
  289. instruction cache does not snoop cpu stores, it is very
  290. likely that you will need to flush the instruction cache
  291. for copy_to_user_page().
  292. void flush_anon_page(struct vm_area_struct *vma, struct page *page,
  293. unsigned long vmaddr)
  294. When the kernel needs to access the contents of an anonymous
  295. page, it calls this function (currently only
  296. get_user_pages()). Note: flush_dcache_page() deliberately
  297. doesn't work for an anonymous page. The default
  298. implementation is a nop (and should remain so for all coherent
  299. architectures). For incoherent architectures, it should flush
  300. the cache of the page at vmaddr.
  301. void flush_kernel_dcache_page(struct page *page)
  302. When the kernel needs to modify a user page is has obtained
  303. with kmap, it calls this function after all modifications are
  304. complete (but before kunmapping it) to bring the underlying
  305. page up to date. It is assumed here that the user has no
  306. incoherent cached copies (i.e. the original page was obtained
  307. from a mechanism like get_user_pages()). The default
  308. implementation is a nop and should remain so on all coherent
  309. architectures. On incoherent architectures, this should flush
  310. the kernel cache for page (using page_address(page)).
  311. void flush_icache_range(unsigned long start, unsigned long end)
  312. When the kernel stores into addresses that it will execute
  313. out of (eg when loading modules), this function is called.
  314. If the icache does not snoop stores then this routine will need
  315. to flush it.
  316. void flush_icache_page(struct vm_area_struct *vma, struct page *page)
  317. All the functionality of flush_icache_page can be implemented in
  318. flush_dcache_page and update_mmu_cache. In 2.7 the hope is to
  319. remove this interface completely.