Interrupts 6.9 KB

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  1. 2.5.2-rmk5
  2. ----------
  3. This is the first kernel that contains a major shake up of some of the
  4. major architecture-specific subsystems.
  5. Firstly, it contains some pretty major changes to the way we handle the
  6. MMU TLB. Each MMU TLB variant is now handled completely separately -
  7. we have TLB v3, TLB v4 (without write buffer), TLB v4 (with write buffer),
  8. and finally TLB v4 (with write buffer, with I TLB invalidate entry).
  9. There is more assembly code inside each of these functions, mainly to
  10. allow more flexible TLB handling for the future.
  11. Secondly, the IRQ subsystem.
  12. The 2.5 kernels will be having major changes to the way IRQs are handled.
  13. Unfortunately, this means that machine types that touch the irq_desc[]
  14. array (basically all machine types) will break, and this means every
  15. machine type that we currently have.
  16. Lets take an example. On the Assabet with Neponset, we have:
  17. GPIO25 IRR:2
  18. SA1100 ------------> Neponset -----------> SA1111
  19. IIR:1
  20. -----------> USAR
  21. IIR:0
  22. -----------> SMC9196
  23. The way stuff currently works, all SA1111 interrupts are mutually
  24. exclusive of each other - if you're processing one interrupt from the
  25. SA1111 and another comes in, you have to wait for that interrupt to
  26. finish processing before you can service the new interrupt. Eg, an
  27. IDE PIO-based interrupt on the SA1111 excludes all other SA1111 and
  28. SMC9196 interrupts until it has finished transferring its multi-sector
  29. data, which can be a long time. Note also that since we loop in the
  30. SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
  31. The new approach brings several new ideas...
  32. We introduce the concept of a "parent" and a "child". For example,
  33. to the Neponset handler, the "parent" is GPIO25, and the "children"d
  34. are SA1111, SMC9196 and USAR.
  35. We also bring the idea of an IRQ "chip" (mainly to reduce the size of
  36. the irqdesc array). This doesn't have to be a real "IC"; indeed the
  37. SA11x0 IRQs are handled by two separate "chip" structures, one for
  38. GPIO0-10, and another for all the rest. It is just a container for
  39. the various operations (maybe this'll change to a better name).
  40. This structure has the following operations:
  41. struct irqchip {
  42. /*
  43. * Acknowledge the IRQ.
  44. * If this is a level-based IRQ, then it is expected to mask the IRQ
  45. * as well.
  46. */
  47. void (*ack)(unsigned int irq);
  48. /*
  49. * Mask the IRQ in hardware.
  50. */
  51. void (*mask)(unsigned int irq);
  52. /*
  53. * Unmask the IRQ in hardware.
  54. */
  55. void (*unmask)(unsigned int irq);
  56. /*
  57. * Re-run the IRQ
  58. */
  59. void (*rerun)(unsigned int irq);
  60. /*
  61. * Set the type of the IRQ.
  62. */
  63. int (*type)(unsigned int irq, unsigned int, type);
  64. };
  65. ack - required. May be the same function as mask for IRQs
  66. handled by do_level_IRQ.
  67. mask - required.
  68. unmask - required.
  69. rerun - optional. Not required if you're using do_level_IRQ for all
  70. IRQs that use this 'irqchip'. Generally expected to re-trigger
  71. the hardware IRQ if possible. If not, may call the handler
  72. directly.
  73. type - optional. If you don't support changing the type of an IRQ,
  74. it should be null so people can detect if they are unable to
  75. set the IRQ type.
  76. For each IRQ, we keep the following information:
  77. - "disable" depth (number of disable_irq()s without enable_irq()s)
  78. - flags indicating what we can do with this IRQ (valid, probe,
  79. noautounmask) as before
  80. - status of the IRQ (probing, enable, etc)
  81. - chip
  82. - per-IRQ handler
  83. - irqaction structure list
  84. The handler can be one of the 3 standard handlers - "level", "edge" and
  85. "simple", or your own specific handler if you need to do something special.
  86. The "level" handler is what we currently have - its pretty simple.
  87. "edge" knows about the brokenness of such IRQ implementations - that you
  88. need to leave the hardware IRQ enabled while processing it, and queueing
  89. further IRQ events should the IRQ happen again while processing. The
  90. "simple" handler is very basic, and does not perform any hardware
  91. manipulation, nor state tracking. This is useful for things like the
  92. SMC9196 and USAR above.
  93. So, what's changed?
  94. 1. Machine implementations must not write to the irqdesc array.
  95. 2. New functions to manipulate the irqdesc array. The first 4 are expected
  96. to be useful only to machine specific code. The last is recommended to
  97. only be used by machine specific code, but may be used in drivers if
  98. absolutely necessary.
  99. set_irq_chip(irq,chip)
  100. Set the mask/unmask methods for handling this IRQ
  101. set_irq_handler(irq,handler)
  102. Set the handler for this IRQ (level, edge, simple)
  103. set_irq_chained_handler(irq,handler)
  104. Set a "chained" handler for this IRQ - automatically
  105. enables this IRQ (eg, Neponset and SA1111 handlers).
  106. set_irq_flags(irq,flags)
  107. Set the valid/probe/noautoenable flags.
  108. set_irq_type(irq,type)
  109. Set active the IRQ edge(s)/level. This replaces the
  110. SA1111 INTPOL manipulation, and the set_GPIO_IRQ_edge()
  111. function. Type should be one of the following:
  112. #define IRQT_NOEDGE (0)
  113. #define IRQT_RISING (__IRQT_RISEDGE)
  114. #define IRQT_FALLING (__IRQT_FALEDGE)
  115. #define IRQT_BOTHEDGE (__IRQT_RISEDGE|__IRQT_FALEDGE)
  116. #define IRQT_LOW (__IRQT_LOWLVL)
  117. #define IRQT_HIGH (__IRQT_HIGHLVL)
  118. 3. set_GPIO_IRQ_edge() is obsolete, and should be replaced by set_irq_type.
  119. 4. Direct access to SA1111 INTPOL is depreciated. Use set_irq_type instead.
  120. 5. A handler is expected to perform any necessary acknowledgement of the
  121. parent IRQ via the correct chip specific function. For instance, if
  122. the SA1111 is directly connected to a SA1110 GPIO, then you should
  123. acknowledge the SA1110 IRQ each time you re-read the SA1111 IRQ status.
  124. 6. For any child which doesn't have its own IRQ enable/disable controls
  125. (eg, SMC9196), the handler must mask or acknowledge the parent IRQ
  126. while the child handler is called, and the child handler should be the
  127. "simple" handler (not "edge" nor "level"). After the handler completes,
  128. the parent IRQ should be unmasked, and the status of all children must
  129. be re-checked for pending events. (see the Neponset IRQ handler for
  130. details).
  131. 7. fixup_irq() is gone, as is include/asm-arm/arch-*/irq.h
  132. Please note that this will not solve all problems - some of them are
  133. hardware based. Mixing level-based and edge-based IRQs on the same
  134. parent signal (eg neponset) is one such area where a software based
  135. solution can't provide the full answer to low IRQ latency.