DMA-API.txt 21 KB

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  1. Dynamic DMA mapping using the generic device
  2. ============================================
  3. James E.J. Bottomley <James.Bottomley@HansenPartnership.com>
  4. This document describes the DMA API. For a more gentle introduction
  5. phrased in terms of the pci_ equivalents (and actual examples) see
  6. DMA-mapping.txt
  7. This API is split into two pieces. Part I describes the API and the
  8. corresponding pci_ API. Part II describes the extensions to the API
  9. for supporting non-consistent memory machines. Unless you know that
  10. your driver absolutely has to support non-consistent platforms (this
  11. is usually only legacy platforms) you should only use the API
  12. described in part I.
  13. Part I - pci_ and dma_ Equivalent API
  14. -------------------------------------
  15. To get the pci_ API, you must #include <linux/pci.h>
  16. To get the dma_ API, you must #include <linux/dma-mapping.h>
  17. Part Ia - Using large dma-coherent buffers
  18. ------------------------------------------
  19. void *
  20. dma_alloc_coherent(struct device *dev, size_t size,
  21. dma_addr_t *dma_handle, int flag)
  22. void *
  23. pci_alloc_consistent(struct pci_dev *dev, size_t size,
  24. dma_addr_t *dma_handle)
  25. Consistent memory is memory for which a write by either the device or
  26. the processor can immediately be read by the processor or device
  27. without having to worry about caching effects. (You may however need
  28. to make sure to flush the processor's write buffers before telling
  29. devices to read that memory.)
  30. This routine allocates a region of <size> bytes of consistent memory.
  31. it also returns a <dma_handle> which may be cast to an unsigned
  32. integer the same width as the bus and used as the physical address
  33. base of the region.
  34. Returns: a pointer to the allocated region (in the processor's virtual
  35. address space) or NULL if the allocation failed.
  36. Note: consistent memory can be expensive on some platforms, and the
  37. minimum allocation length may be as big as a page, so you should
  38. consolidate your requests for consistent memory as much as possible.
  39. The simplest way to do that is to use the dma_pool calls (see below).
  40. The flag parameter (dma_alloc_coherent only) allows the caller to
  41. specify the GFP_ flags (see kmalloc) for the allocation (the
  42. implementation may chose to ignore flags that affect the location of
  43. the returned memory, like GFP_DMA). For pci_alloc_consistent, you
  44. must assume GFP_ATOMIC behaviour.
  45. void
  46. dma_free_coherent(struct device *dev, size_t size, void *cpu_addr
  47. dma_addr_t dma_handle)
  48. void
  49. pci_free_consistent(struct pci_dev *dev, size_t size, void *cpu_addr
  50. dma_addr_t dma_handle)
  51. Free the region of consistent memory you previously allocated. dev,
  52. size and dma_handle must all be the same as those passed into the
  53. consistent allocate. cpu_addr must be the virtual address returned by
  54. the consistent allocate
  55. Part Ib - Using small dma-coherent buffers
  56. ------------------------------------------
  57. To get this part of the dma_ API, you must #include <linux/dmapool.h>
  58. Many drivers need lots of small dma-coherent memory regions for DMA
  59. descriptors or I/O buffers. Rather than allocating in units of a page
  60. or more using dma_alloc_coherent(), you can use DMA pools. These work
  61. much like a struct kmem_cache, except that they use the dma-coherent allocator
  62. not __get_free_pages(). Also, they understand common hardware constraints
  63. for alignment, like queue heads needing to be aligned on N byte boundaries.
  64. struct dma_pool *
  65. dma_pool_create(const char *name, struct device *dev,
  66. size_t size, size_t align, size_t alloc);
  67. struct pci_pool *
  68. pci_pool_create(const char *name, struct pci_device *dev,
  69. size_t size, size_t align, size_t alloc);
  70. The pool create() routines initialize a pool of dma-coherent buffers
  71. for use with a given device. It must be called in a context which
  72. can sleep.
  73. The "name" is for diagnostics (like a struct kmem_cache name); dev and size
  74. are like what you'd pass to dma_alloc_coherent(). The device's hardware
  75. alignment requirement for this type of data is "align" (which is expressed
  76. in bytes, and must be a power of two). If your device has no boundary
  77. crossing restrictions, pass 0 for alloc; passing 4096 says memory allocated
  78. from this pool must not cross 4KByte boundaries.
  79. void *dma_pool_alloc(struct dma_pool *pool, int gfp_flags,
  80. dma_addr_t *dma_handle);
  81. void *pci_pool_alloc(struct pci_pool *pool, int gfp_flags,
  82. dma_addr_t *dma_handle);
  83. This allocates memory from the pool; the returned memory will meet the size
  84. and alignment requirements specified at creation time. Pass GFP_ATOMIC to
  85. prevent blocking, or if it's permitted (not in_interrupt, not holding SMP locks)
  86. pass GFP_KERNEL to allow blocking. Like dma_alloc_coherent(), this returns
  87. two values: an address usable by the cpu, and the dma address usable by the
  88. pool's device.
  89. void dma_pool_free(struct dma_pool *pool, void *vaddr,
  90. dma_addr_t addr);
  91. void pci_pool_free(struct pci_pool *pool, void *vaddr,
  92. dma_addr_t addr);
  93. This puts memory back into the pool. The pool is what was passed to
  94. the pool allocation routine; the cpu and dma addresses are what
  95. were returned when that routine allocated the memory being freed.
  96. void dma_pool_destroy(struct dma_pool *pool);
  97. void pci_pool_destroy(struct pci_pool *pool);
  98. The pool destroy() routines free the resources of the pool. They must be
  99. called in a context which can sleep. Make sure you've freed all allocated
  100. memory back to the pool before you destroy it.
  101. Part Ic - DMA addressing limitations
  102. ------------------------------------
  103. int
  104. dma_supported(struct device *dev, u64 mask)
  105. int
  106. pci_dma_supported(struct device *dev, u64 mask)
  107. Checks to see if the device can support DMA to the memory described by
  108. mask.
  109. Returns: 1 if it can and 0 if it can't.
  110. Notes: This routine merely tests to see if the mask is possible. It
  111. won't change the current mask settings. It is more intended as an
  112. internal API for use by the platform than an external API for use by
  113. driver writers.
  114. int
  115. dma_set_mask(struct device *dev, u64 mask)
  116. int
  117. pci_set_dma_mask(struct pci_device *dev, u64 mask)
  118. Checks to see if the mask is possible and updates the device
  119. parameters if it is.
  120. Returns: 0 if successful and a negative error if not.
  121. u64
  122. dma_get_required_mask(struct device *dev)
  123. After setting the mask with dma_set_mask(), this API returns the
  124. actual mask (within that already set) that the platform actually
  125. requires to operate efficiently. Usually this means the returned mask
  126. is the minimum required to cover all of memory. Examining the
  127. required mask gives drivers with variable descriptor sizes the
  128. opportunity to use smaller descriptors as necessary.
  129. Requesting the required mask does not alter the current mask. If you
  130. wish to take advantage of it, you should issue another dma_set_mask()
  131. call to lower the mask again.
  132. Part Id - Streaming DMA mappings
  133. --------------------------------
  134. dma_addr_t
  135. dma_map_single(struct device *dev, void *cpu_addr, size_t size,
  136. enum dma_data_direction direction)
  137. dma_addr_t
  138. pci_map_single(struct device *dev, void *cpu_addr, size_t size,
  139. int direction)
  140. Maps a piece of processor virtual memory so it can be accessed by the
  141. device and returns the physical handle of the memory.
  142. The direction for both api's may be converted freely by casting.
  143. However the dma_ API uses a strongly typed enumerator for its
  144. direction:
  145. DMA_NONE = PCI_DMA_NONE no direction (used for
  146. debugging)
  147. DMA_TO_DEVICE = PCI_DMA_TODEVICE data is going from the
  148. memory to the device
  149. DMA_FROM_DEVICE = PCI_DMA_FROMDEVICE data is coming from
  150. the device to the
  151. memory
  152. DMA_BIDIRECTIONAL = PCI_DMA_BIDIRECTIONAL direction isn't known
  153. Notes: Not all memory regions in a machine can be mapped by this
  154. API. Further, regions that appear to be physically contiguous in
  155. kernel virtual space may not be contiguous as physical memory. Since
  156. this API does not provide any scatter/gather capability, it will fail
  157. if the user tries to map a non physically contiguous piece of memory.
  158. For this reason, it is recommended that memory mapped by this API be
  159. obtained only from sources which guarantee to be physically contiguous
  160. (like kmalloc).
  161. Further, the physical address of the memory must be within the
  162. dma_mask of the device (the dma_mask represents a bit mask of the
  163. addressable region for the device. i.e. if the physical address of
  164. the memory anded with the dma_mask is still equal to the physical
  165. address, then the device can perform DMA to the memory). In order to
  166. ensure that the memory allocated by kmalloc is within the dma_mask,
  167. the driver may specify various platform dependent flags to restrict
  168. the physical memory range of the allocation (e.g. on x86, GFP_DMA
  169. guarantees to be within the first 16Mb of available physical memory,
  170. as required by ISA devices).
  171. Note also that the above constraints on physical contiguity and
  172. dma_mask may not apply if the platform has an IOMMU (a device which
  173. supplies a physical to virtual mapping between the I/O memory bus and
  174. the device). However, to be portable, device driver writers may *not*
  175. assume that such an IOMMU exists.
  176. Warnings: Memory coherency operates at a granularity called the cache
  177. line width. In order for memory mapped by this API to operate
  178. correctly, the mapped region must begin exactly on a cache line
  179. boundary and end exactly on one (to prevent two separately mapped
  180. regions from sharing a single cache line). Since the cache line size
  181. may not be known at compile time, the API will not enforce this
  182. requirement. Therefore, it is recommended that driver writers who
  183. don't take special care to determine the cache line size at run time
  184. only map virtual regions that begin and end on page boundaries (which
  185. are guaranteed also to be cache line boundaries).
  186. DMA_TO_DEVICE synchronisation must be done after the last modification
  187. of the memory region by the software and before it is handed off to
  188. the driver. Once this primitive is used. Memory covered by this
  189. primitive should be treated as read only by the device. If the device
  190. may write to it at any point, it should be DMA_BIDIRECTIONAL (see
  191. below).
  192. DMA_FROM_DEVICE synchronisation must be done before the driver
  193. accesses data that may be changed by the device. This memory should
  194. be treated as read only by the driver. If the driver needs to write
  195. to it at any point, it should be DMA_BIDIRECTIONAL (see below).
  196. DMA_BIDIRECTIONAL requires special handling: it means that the driver
  197. isn't sure if the memory was modified before being handed off to the
  198. device and also isn't sure if the device will also modify it. Thus,
  199. you must always sync bidirectional memory twice: once before the
  200. memory is handed off to the device (to make sure all memory changes
  201. are flushed from the processor) and once before the data may be
  202. accessed after being used by the device (to make sure any processor
  203. cache lines are updated with data that the device may have changed.
  204. void
  205. dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
  206. enum dma_data_direction direction)
  207. void
  208. pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
  209. size_t size, int direction)
  210. Unmaps the region previously mapped. All the parameters passed in
  211. must be identical to those passed in (and returned) by the mapping
  212. API.
  213. dma_addr_t
  214. dma_map_page(struct device *dev, struct page *page,
  215. unsigned long offset, size_t size,
  216. enum dma_data_direction direction)
  217. dma_addr_t
  218. pci_map_page(struct pci_dev *hwdev, struct page *page,
  219. unsigned long offset, size_t size, int direction)
  220. void
  221. dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
  222. enum dma_data_direction direction)
  223. void
  224. pci_unmap_page(struct pci_dev *hwdev, dma_addr_t dma_address,
  225. size_t size, int direction)
  226. API for mapping and unmapping for pages. All the notes and warnings
  227. for the other mapping APIs apply here. Also, although the <offset>
  228. and <size> parameters are provided to do partial page mapping, it is
  229. recommended that you never use these unless you really know what the
  230. cache width is.
  231. int
  232. dma_mapping_error(dma_addr_t dma_addr)
  233. int
  234. pci_dma_mapping_error(dma_addr_t dma_addr)
  235. In some circumstances dma_map_single and dma_map_page will fail to create
  236. a mapping. A driver can check for these errors by testing the returned
  237. dma address with dma_mapping_error(). A non zero return value means the mapping
  238. could not be created and the driver should take appropriate action (eg
  239. reduce current DMA mapping usage or delay and try again later).
  240. int
  241. dma_map_sg(struct device *dev, struct scatterlist *sg,
  242. int nents, enum dma_data_direction direction)
  243. int
  244. pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
  245. int nents, int direction)
  246. Maps a scatter gather list from the block layer.
  247. Returns: the number of physical segments mapped (this may be shorted
  248. than <nents> passed in if the block layer determines that some
  249. elements of the scatter/gather list are physically adjacent and thus
  250. may be mapped with a single entry).
  251. Please note that the sg cannot be mapped again if it has been mapped once.
  252. The mapping process is allowed to destroy information in the sg.
  253. As with the other mapping interfaces, dma_map_sg can fail. When it
  254. does, 0 is returned and a driver must take appropriate action. It is
  255. critical that the driver do something, in the case of a block driver
  256. aborting the request or even oopsing is better than doing nothing and
  257. corrupting the filesystem.
  258. With scatterlists, you use the resulting mapping like this:
  259. int i, count = dma_map_sg(dev, sglist, nents, direction);
  260. struct scatterlist *sg;
  261. for (i = 0, sg = sglist; i < count; i++, sg++) {
  262. hw_address[i] = sg_dma_address(sg);
  263. hw_len[i] = sg_dma_len(sg);
  264. }
  265. where nents is the number of entries in the sglist.
  266. The implementation is free to merge several consecutive sglist entries
  267. into one (e.g. with an IOMMU, or if several pages just happen to be
  268. physically contiguous) and returns the actual number of sg entries it
  269. mapped them to. On failure 0, is returned.
  270. Then you should loop count times (note: this can be less than nents times)
  271. and use sg_dma_address() and sg_dma_len() macros where you previously
  272. accessed sg->address and sg->length as shown above.
  273. void
  274. dma_unmap_sg(struct device *dev, struct scatterlist *sg,
  275. int nhwentries, enum dma_data_direction direction)
  276. void
  277. pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
  278. int nents, int direction)
  279. unmap the previously mapped scatter/gather list. All the parameters
  280. must be the same as those and passed in to the scatter/gather mapping
  281. API.
  282. Note: <nents> must be the number you passed in, *not* the number of
  283. physical entries returned.
  284. void
  285. dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size,
  286. enum dma_data_direction direction)
  287. void
  288. pci_dma_sync_single(struct pci_dev *hwdev, dma_addr_t dma_handle,
  289. size_t size, int direction)
  290. void
  291. dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems,
  292. enum dma_data_direction direction)
  293. void
  294. pci_dma_sync_sg(struct pci_dev *hwdev, struct scatterlist *sg,
  295. int nelems, int direction)
  296. synchronise a single contiguous or scatter/gather mapping. All the
  297. parameters must be the same as those passed into the single mapping
  298. API.
  299. Notes: You must do this:
  300. - Before reading values that have been written by DMA from the device
  301. (use the DMA_FROM_DEVICE direction)
  302. - After writing values that will be written to the device using DMA
  303. (use the DMA_TO_DEVICE) direction
  304. - before *and* after handing memory to the device if the memory is
  305. DMA_BIDIRECTIONAL
  306. See also dma_map_single().
  307. Part II - Advanced dma_ usage
  308. -----------------------------
  309. Warning: These pieces of the DMA API have no PCI equivalent. They
  310. should also not be used in the majority of cases, since they cater for
  311. unlikely corner cases that don't belong in usual drivers.
  312. If you don't understand how cache line coherency works between a
  313. processor and an I/O device, you should not be using this part of the
  314. API at all.
  315. void *
  316. dma_alloc_noncoherent(struct device *dev, size_t size,
  317. dma_addr_t *dma_handle, int flag)
  318. Identical to dma_alloc_coherent() except that the platform will
  319. choose to return either consistent or non-consistent memory as it sees
  320. fit. By using this API, you are guaranteeing to the platform that you
  321. have all the correct and necessary sync points for this memory in the
  322. driver should it choose to return non-consistent memory.
  323. Note: where the platform can return consistent memory, it will
  324. guarantee that the sync points become nops.
  325. Warning: Handling non-consistent memory is a real pain. You should
  326. only ever use this API if you positively know your driver will be
  327. required to work on one of the rare (usually non-PCI) architectures
  328. that simply cannot make consistent memory.
  329. void
  330. dma_free_noncoherent(struct device *dev, size_t size, void *cpu_addr,
  331. dma_addr_t dma_handle)
  332. free memory allocated by the nonconsistent API. All parameters must
  333. be identical to those passed in (and returned by
  334. dma_alloc_noncoherent()).
  335. int
  336. dma_is_consistent(struct device *dev, dma_addr_t dma_handle)
  337. returns true if the device dev is performing consistent DMA on the memory
  338. area pointed to by the dma_handle.
  339. int
  340. dma_get_cache_alignment(void)
  341. returns the processor cache alignment. This is the absolute minimum
  342. alignment *and* width that you must observe when either mapping
  343. memory or doing partial flushes.
  344. Notes: This API may return a number *larger* than the actual cache
  345. line, but it will guarantee that one or more cache lines fit exactly
  346. into the width returned by this call. It will also always be a power
  347. of two for easy alignment
  348. void
  349. dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
  350. unsigned long offset, size_t size,
  351. enum dma_data_direction direction)
  352. does a partial sync. starting at offset and continuing for size. You
  353. must be careful to observe the cache alignment and width when doing
  354. anything like this. You must also be extra careful about accessing
  355. memory you intend to sync partially.
  356. void
  357. dma_cache_sync(struct device *dev, void *vaddr, size_t size,
  358. enum dma_data_direction direction)
  359. Do a partial sync of memory that was allocated by
  360. dma_alloc_noncoherent(), starting at virtual address vaddr and
  361. continuing on for size. Again, you *must* observe the cache line
  362. boundaries when doing this.
  363. int
  364. dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
  365. dma_addr_t device_addr, size_t size, int
  366. flags)
  367. Declare region of memory to be handed out by dma_alloc_coherent when
  368. it's asked for coherent memory for this device.
  369. bus_addr is the physical address to which the memory is currently
  370. assigned in the bus responding region (this will be used by the
  371. platform to perform the mapping)
  372. device_addr is the physical address the device needs to be programmed
  373. with actually to address this memory (this will be handed out as the
  374. dma_addr_t in dma_alloc_coherent())
  375. size is the size of the area (must be multiples of PAGE_SIZE).
  376. flags can be or'd together and are
  377. DMA_MEMORY_MAP - request that the memory returned from
  378. dma_alloc_coherent() be directly writable.
  379. DMA_MEMORY_IO - request that the memory returned from
  380. dma_alloc_coherent() be addressable using read/write/memcpy_toio etc.
  381. One or both of these flags must be present
  382. DMA_MEMORY_INCLUDES_CHILDREN - make the declared memory be allocated by
  383. dma_alloc_coherent of any child devices of this one (for memory residing
  384. on a bridge).
  385. DMA_MEMORY_EXCLUSIVE - only allocate memory from the declared regions.
  386. Do not allow dma_alloc_coherent() to fall back to system memory when
  387. it's out of memory in the declared region.
  388. The return value will be either DMA_MEMORY_MAP or DMA_MEMORY_IO and
  389. must correspond to a passed in flag (i.e. no returning DMA_MEMORY_IO
  390. if only DMA_MEMORY_MAP were passed in) for success or zero for
  391. failure.
  392. Note, for DMA_MEMORY_IO returns, all subsequent memory returned by
  393. dma_alloc_coherent() may no longer be accessed directly, but instead
  394. must be accessed using the correct bus functions. If your driver
  395. isn't prepared to handle this contingency, it should not specify
  396. DMA_MEMORY_IO in the input flags.
  397. As a simplification for the platforms, only *one* such region of
  398. memory may be declared per device.
  399. For reasons of efficiency, most platforms choose to track the declared
  400. region only at the granularity of a page. For smaller allocations,
  401. you should use the dma_pool() API.
  402. void
  403. dma_release_declared_memory(struct device *dev)
  404. Remove the memory region previously declared from the system. This
  405. API performs *no* in-use checking for this region and will return
  406. unconditionally having removed all the required structures. It is the
  407. drivers job to ensure that no parts of this memory region are
  408. currently in use.
  409. void *
  410. dma_mark_declared_memory_occupied(struct device *dev,
  411. dma_addr_t device_addr, size_t size)
  412. This is used to occupy specific regions of the declared space
  413. (dma_alloc_coherent() will hand out the first free region it finds).
  414. device_addr is the *device* address of the region requested
  415. size is the size (and should be a page sized multiple).
  416. The return value will be either a pointer to the processor virtual
  417. address of the memory, or an error (via PTR_ERR()) if any part of the
  418. region is occupied.