regs-gpio.h 92 KB

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  1. /* linux/include/asm-arm/arch-s3c2410/regs-gpio.h
  2. *
  3. * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
  4. * http://www.simtec.co.uk/products/SWLINUX/
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * S3C2410 GPIO register definitions
  11. */
  12. #ifndef __ASM_ARCH_REGS_GPIO_H
  13. #define __ASM_ARCH_REGS_GPIO_H "$Id: regs-gpio.h,v 1.13 2008/05/29 10:24:49 boyko Exp $"
  14. #define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
  15. #define S3C2410_GPIO_BANKA (32*0)
  16. #define S3C2410_GPIO_BANKB (32*1)
  17. #define S3C2410_GPIO_BANKC (32*2)
  18. #define S3C2410_GPIO_BANKD (32*3)
  19. #define S3C2410_GPIO_BANKE (32*4)
  20. #define S3C2410_GPIO_BANKF (32*5)
  21. #define S3C2410_GPIO_BANKG (32*6)
  22. #define S3C2410_GPIO_BANKH (32*7)
  23. #define S3C2410_GPIO_BANKJ (32*13)
  24. #define S3C2410_GPIO_BANKK (32*14)
  25. #define S3C2410_GPIO_BANKL (32*15)
  26. #ifdef CONFIG_CPU_S3C2400
  27. #define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x)
  28. #define S3C24XX_MISCCR S3C2400_MISCCR
  29. #else
  30. #define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x)
  31. #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
  32. #define S3C24XX_MISCCR_SPISEL (1<<31) /* SET SPI on S3C2443 */
  33. #endif /* CONFIG_CPU_S3C2400 */
  34. /* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
  35. #define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32)
  36. #define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2))
  37. #define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \
  38. (2 * (S3C2400_BANKNUM(pin)-2)))
  39. #define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \
  40. S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
  41. S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
  42. #define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
  43. #define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
  44. /* general configuration options */
  45. #define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
  46. #define S3C2410_GPIO_INPUT (0xFFFFFFF0) /* not available on A */
  47. #define S3C2410_GPIO_OUTPUT (0xFFFFFFF1)
  48. #define S3C2410_GPIO_IRQ (0xFFFFFFF2) /* not available for all */
  49. #define S3C2410_GPIO_SFN2 (0xFFFFFFF2) /* bank A => addr/cs/nand */
  50. #define S3C2410_GPIO_SFN3 (0xFFFFFFF3) /* not available on A */
  51. /* register address for the GPIO registers.
  52. * S3C24XX_GPIOREG2 is for the second set of registers in the
  53. * GPIO which move between s3c2410 and s3c2412 type systems */
  54. #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
  55. #define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
  56. /* configure GPIO ports A..G */
  57. /* port A - S3C2410: 22bits, zero in bit X makes pin X output
  58. * S3C2400: 18bits, zero in bit X makes pin X output
  59. * 1 makes port special function, this is default
  60. */
  61. #define S3C2410_GPACON S3C2410_GPIOREG(0x00)
  62. #define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
  63. #define S3C2400_GPACON S3C2410_GPIOREG(0x00)
  64. #define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
  65. #define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
  66. #define S3C2410_GPA0_OUT (0<<0)
  67. #define S3C2410_GPA0_ADDR0 (1<<0)
  68. #define S3C2410_GPA1 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
  69. #define S3C2410_GPA1_OUT (0<<1)
  70. #define S3C2410_GPA1_ADDR16 (1<<1)
  71. #define S3C2410_GPA2 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
  72. #define S3C2410_GPA2_OUT (0<<2)
  73. #define S3C2410_GPA2_ADDR17 (1<<2)
  74. #define S3C2410_GPA3 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
  75. #define S3C2410_GPA3_OUT (0<<3)
  76. #define S3C2410_GPA3_ADDR18 (1<<3)
  77. #define S3C2410_GPA4 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
  78. #define S3C2410_GPA4_OUT (0<<4)
  79. #define S3C2410_GPA4_ADDR19 (1<<4)
  80. #define S3C2410_GPA5 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
  81. #define S3C2410_GPA5_OUT (0<<5)
  82. #define S3C2410_GPA5_ADDR20 (1<<5)
  83. #define S3C2410_GPA6 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
  84. #define S3C2410_GPA6_OUT (0<<6)
  85. #define S3C2410_GPA6_ADDR21 (1<<6)
  86. #define S3C2410_GPA7 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
  87. #define S3C2410_GPA7_OUT (0<<7)
  88. #define S3C2410_GPA7_ADDR22 (1<<7)
  89. #define S3C2410_GPA8 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
  90. #define S3C2410_GPA8_OUT (0<<8)
  91. #define S3C2410_GPA8_ADDR23 (1<<8)
  92. #define S3C2410_GPA9 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
  93. #define S3C2410_GPA9_OUT (0<<9)
  94. #define S3C2410_GPA9_ADDR24 (1<<9)
  95. #define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
  96. #define S3C2410_GPA10_OUT (0<<10)
  97. #define S3C2410_GPA10_ADDR25 (1<<10)
  98. #define S3C2400_GPA10_SCKE (1<<10)
  99. #define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
  100. #define S3C2410_GPA11_OUT (0<<11)
  101. #define S3C2410_GPA11_ADDR26 (1<<11)
  102. #define S3C2400_GPA11_nCAS0 (1<<11)
  103. #define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
  104. #define S3C2410_GPA12_OUT (0<<12)
  105. #define S3C2410_GPA12_nGCS1 (1<<12)
  106. #define S3C2400_GPA12_nCAS1 (1<<12)
  107. #define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
  108. #define S3C2410_GPA13_OUT (0<<13)
  109. #define S3C2410_GPA13_nGCS2 (1<<13)
  110. #define S3C2400_GPA13_nGCS1 (1<<13)
  111. #define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
  112. #define S3C2410_GPA14_OUT (0<<14)
  113. #define S3C2410_GPA14_nGCS3 (1<<14)
  114. #define S3C2400_GPA14_nGCS2 (1<<14)
  115. #define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
  116. #define S3C2410_GPA15_OUT (0<<15)
  117. #define S3C2410_GPA15_nGCS4 (1<<15)
  118. #define S3C2400_GPA15_nGCS3 (1<<15)
  119. #define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
  120. #define S3C2410_GPA16_OUT (0<<16)
  121. #define S3C2410_GPA16_nGCS5 (1<<16)
  122. #define S3C2400_GPA16_nGCS4 (1<<16)
  123. #define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
  124. #define S3C2410_GPA17_OUT (0<<17)
  125. #define S3C2410_GPA17_CLE (1<<17)
  126. #define S3C2400_GPA17_nGCS5 (1<<17)
  127. #define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
  128. #define S3C2410_GPA18_OUT (0<<18)
  129. #define S3C2410_GPA18_ALE (1<<18)
  130. #define S3C2410_GPA19 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
  131. #define S3C2410_GPA19_OUT (0<<19)
  132. #define S3C2410_GPA19_nFWE (1<<19)
  133. #define S3C2410_GPA20 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
  134. #define S3C2410_GPA20_OUT (0<<20)
  135. #define S3C2410_GPA20_nFRE (1<<20)
  136. #define S3C2410_GPA21 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
  137. #define S3C2410_GPA21_OUT (0<<21)
  138. #define S3C2410_GPA21_nRSTOUT (1<<21)
  139. #define S3C2410_GPA22 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
  140. #define S3C2410_GPA22_OUT (0<<22)
  141. #define S3C2410_GPA22_nFCE (1<<22)
  142. /* 0x08 and 0x0c are reserved on S3C2410 */
  143. /* S3C2410:
  144. * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
  145. * 00 = input, 01 = output, 10=special function, 11=reserved
  146. * S3C2400:
  147. * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
  148. * 00 = input, 01 = output, 10=data, 11=special function
  149. * bit 0,1 = pin 0, 2,3= pin 1...
  150. *
  151. * CPBUP = pull up resistor control, 1=disabled, 0=enabled
  152. */
  153. #define S3C2410_GPBCON S3C2410_GPIOREG(0x10)
  154. #define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
  155. #define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
  156. #define S3C2400_GPBCON S3C2410_GPIOREG(0x08)
  157. #define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
  158. #define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
  159. #define S3C2450_GPBSEL S3C2410_GPIOREG(0x1C)
  160. /* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
  161. #define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
  162. #define S3C2410_GPB0_INP (0x00 << 0)
  163. #define S3C2410_GPB0_OUTP (0x01 << 0)
  164. #define S3C2410_GPB0_TOUT0 (0x02 << 0)
  165. #define S3C2400_GPB0_DATA16 (0x02 << 0)
  166. #define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
  167. #define S3C2410_GPB1_INP (0x00 << 2)
  168. #define S3C2410_GPB1_OUTP (0x01 << 2)
  169. #define S3C2410_GPB1_TOUT1 (0x02 << 2)
  170. #define S3C2400_GPB1_DATA17 (0x02 << 2)
  171. #define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
  172. #define S3C2410_GPB2_INP (0x00 << 4)
  173. #define S3C2410_GPB2_OUTP (0x01 << 4)
  174. #define S3C2410_GPB2_TOUT2 (0x02 << 4)
  175. #define S3C2400_GPB2_DATA18 (0x02 << 4)
  176. #define S3C2400_GPB2_TCLK1 (0x03 << 4)
  177. #define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
  178. #define S3C2410_GPB3_INP (0x00 << 6)
  179. #define S3C2410_GPB3_OUTP (0x01 << 6)
  180. #define S3C2410_GPB3_TOUT3 (0x02 << 6)
  181. #define S3C2400_GPB3_DATA19 (0x02 << 6)
  182. #define S3C2400_GPB3_TXD1 (0x03 << 6)
  183. #define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
  184. #define S3C2410_GPB4_INP (0x00 << 8)
  185. #define S3C2410_GPB4_OUTP (0x01 << 8)
  186. #define S3C2410_GPB4_TCLK0 (0x02 << 8)
  187. #define S3C2400_GPB4_DATA20 (0x02 << 8)
  188. #define S3C2410_GPB4_MASK (0x03 << 8)
  189. #define S3C2400_GPB4_RXD1 (0x03 << 8)
  190. #define S3C2400_GPB4_MASK (0x03 << 8)
  191. #define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
  192. #define S3C2410_GPB5_INP (0x00 << 10)
  193. #define S3C2410_GPB5_OUTP (0x01 << 10)
  194. #define S3C2410_GPB5_nXBACK (0x02 << 10)
  195. #define S3C2443_GPB5_XBACK (0x03 << 10)
  196. #define S3C2400_GPB5_DATA21 (0x02 << 10)
  197. #define S3C2400_GPB5_nCTS1 (0x03 << 10)
  198. #define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
  199. #define S3C2410_GPB6_INP (0x00 << 12)
  200. #define S3C2410_GPB6_OUTP (0x01 << 12)
  201. #define S3C2410_GPB6_nXBREQ (0x02 << 12)
  202. #define S3C2443_GPB6_XBREQ (0x03 << 12)
  203. #define S3C2400_GPB6_DATA22 (0x02 << 12)
  204. #define S3C2400_GPB6_nRTS1 (0x03 << 12)
  205. #define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
  206. #define S3C2410_GPB7_INP (0x00 << 14)
  207. #define S3C2410_GPB7_OUTP (0x01 << 14)
  208. #define S3C2410_GPB7_nXDACK1 (0x02 << 14)
  209. #define S3C2443_GPB7_XDACK1 (0x03 << 14)
  210. #define S3C2400_GPB7_DATA23 (0x02 << 14)
  211. #define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
  212. #define S3C2410_GPB8_INP (0x00 << 16)
  213. #define S3C2410_GPB8_OUTP (0x01 << 16)
  214. #define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
  215. #define S3C2400_GPB8_DATA24 (0x02 << 16)
  216. #define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
  217. #define S3C2410_GPB9_INP (0x00 << 18)
  218. #define S3C2410_GPB9_OUTP (0x01 << 18)
  219. #define S3C2410_GPB9_nXDACK0 (0x02 << 18)
  220. #define S3C2443_GPB9_XDACK0 (0x03 << 18)
  221. #define S3C2400_GPB9_DATA25 (0x02 << 18)
  222. #define S3C2400_GPB9_I2SSDI (0x03 << 18)
  223. #define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
  224. #define S3C2410_GPB10_INP (0x00 << 20)
  225. #define S3C2410_GPB10_OUTP (0x01 << 20)
  226. #define S3C2410_GPB10_nXDRE0 (0x02 << 20)
  227. #define S3C2443_GPB10_XDREQ0 (0x03 << 20)
  228. #define S3C2400_GPB10_DATA26 (0x02 << 20)
  229. #define S3C2400_GPB10_nSS (0x03 << 20)
  230. #define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
  231. #define S3C2400_GPB11_INP (0x00 << 22)
  232. #define S3C2400_GPB11_OUTP (0x01 << 22)
  233. #define S3C2400_GPB11_DATA27 (0x02 << 22)
  234. #define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
  235. #define S3C2400_GPB12_INP (0x00 << 24)
  236. #define S3C2400_GPB12_OUTP (0x01 << 24)
  237. #define S3C2400_GPB12_DATA28 (0x02 << 24)
  238. #define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
  239. #define S3C2400_GPB13_INP (0x00 << 26)
  240. #define S3C2400_GPB13_OUTP (0x01 << 26)
  241. #define S3C2400_GPB13_DATA29 (0x02 << 26)
  242. #define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
  243. #define S3C2400_GPB14_INP (0x00 << 28)
  244. #define S3C2400_GPB14_OUTP (0x01 << 28)
  245. #define S3C2400_GPB14_DATA30 (0x02 << 28)
  246. #define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
  247. #define S3C2400_GPB15_INP (0x00 << 30)
  248. #define S3C2400_GPB15_OUTP (0x01 << 30)
  249. #define S3C2400_GPB15_DATA31 (0x02 << 30)
  250. #define S3C2410_GPB_PUPDIS(x) (1<<(x))
  251. /* Port C consits of 16 GPIO/Special function
  252. *
  253. * almost identical setup to port b, but the special functions are mostly
  254. * to do with the video system's sync/etc.
  255. */
  256. #define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
  257. #define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
  258. #define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
  259. #define S3C2400_GPCCON S3C2410_GPIOREG(0x14)
  260. #define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
  261. #define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
  262. #define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
  263. #define S3C2410_GPC0_INP (0x00 << 0)
  264. #define S3C2410_GPC0_OUTP (0x01 << 0)
  265. #define S3C2410_GPC0_LEND (0x02 << 0)
  266. #define S3C2400_GPC0_VD0 (0x02 << 0)
  267. #define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
  268. #define S3C2410_GPC1_INP (0x00 << 2)
  269. #define S3C2410_GPC1_OUTP (0x01 << 2)
  270. #define S3C2410_GPC1_VCLK (0x02 << 2)
  271. #define S3C2400_GPC1_VD1 (0x02 << 2)
  272. #define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
  273. #define S3C2410_GPC2_INP (0x00 << 4)
  274. #define S3C2410_GPC2_OUTP (0x01 << 4)
  275. #define S3C2410_GPC2_VLINE (0x02 << 4)
  276. #define S3C2400_GPC2_VD2 (0x02 << 4)
  277. #define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
  278. #define S3C2410_GPC3_INP (0x00 << 6)
  279. #define S3C2410_GPC3_OUTP (0x01 << 6)
  280. #define S3C2410_GPC3_VFRAME (0x02 << 6)
  281. #define S3C2400_GPC3_VD3 (0x02 << 6)
  282. #define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
  283. #define S3C2410_GPC4_INP (0x00 << 8)
  284. #define S3C2410_GPC4_OUTP (0x01 << 8)
  285. #define S3C2410_GPC4_VM (0x02 << 8)
  286. #define S3C2400_GPC4_VD4 (0x02 << 8)
  287. #define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
  288. #define S3C2410_GPC5_INP (0x00 << 10)
  289. #define S3C2410_GPC5_OUTP (0x01 << 10)
  290. #define S3C2410_GPC5_LCDVF0 (0x02 << 10)
  291. #define S3C2400_GPC5_VD5 (0x02 << 10)
  292. #define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
  293. #define S3C2410_GPC6_INP (0x00 << 12)
  294. #define S3C2410_GPC6_OUTP (0x01 << 12)
  295. #define S3C2410_GPC6_LCDVF1 (0x02 << 12)
  296. #define S3C2400_GPC6_VD6 (0x02 << 12)
  297. #define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
  298. #define S3C2410_GPC7_INP (0x00 << 14)
  299. #define S3C2410_GPC7_OUTP (0x01 << 14)
  300. #define S3C2410_GPC7_LCDVF2 (0x02 << 14)
  301. #define S3C2400_GPC7_VD7 (0x02 << 14)
  302. #define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
  303. #define S3C2410_GPC8_INP (0x00 << 16)
  304. #define S3C2410_GPC8_OUTP (0x01 << 16)
  305. #define S3C2410_GPC8_VD0 (0x02 << 16)
  306. #define S3C2400_GPC8_VD8 (0x02 << 16)
  307. #define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
  308. #define S3C2410_GPC9_INP (0x00 << 18)
  309. #define S3C2410_GPC9_OUTP (0x01 << 18)
  310. #define S3C2410_GPC9_VD1 (0x02 << 18)
  311. #define S3C2400_GPC9_VD9 (0x02 << 18)
  312. #define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
  313. #define S3C2410_GPC10_INP (0x00 << 20)
  314. #define S3C2410_GPC10_OUTP (0x01 << 20)
  315. #define S3C2410_GPC10_VD2 (0x02 << 20)
  316. #define S3C2400_GPC10_VD10 (0x02 << 20)
  317. #define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
  318. #define S3C2410_GPC11_INP (0x00 << 22)
  319. #define S3C2410_GPC11_OUTP (0x01 << 22)
  320. #define S3C2410_GPC11_VD3 (0x02 << 22)
  321. #define S3C2400_GPC11_VD11 (0x02 << 22)
  322. #define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
  323. #define S3C2410_GPC12_INP (0x00 << 24)
  324. #define S3C2410_GPC12_OUTP (0x01 << 24)
  325. #define S3C2410_GPC12_VD4 (0x02 << 24)
  326. #define S3C2400_GPC12_VD12 (0x02 << 24)
  327. #define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
  328. #define S3C2410_GPC13_INP (0x00 << 26)
  329. #define S3C2410_GPC13_OUTP (0x01 << 26)
  330. #define S3C2410_GPC13_VD5 (0x02 << 26)
  331. #define S3C2400_GPC13_VD13 (0x02 << 26)
  332. #define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
  333. #define S3C2410_GPC14_INP (0x00 << 28)
  334. #define S3C2410_GPC14_OUTP (0x01 << 28)
  335. #define S3C2410_GPC14_VD6 (0x02 << 28)
  336. #define S3C2400_GPC14_VD14 (0x02 << 28)
  337. #define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
  338. #define S3C2410_GPC15_INP (0x00 << 30)
  339. #define S3C2410_GPC15_OUTP (0x01 << 30)
  340. #define S3C2410_GPC15_VD7 (0x02 << 30)
  341. #define S3C2400_GPC15_VD15 (0x02 << 30)
  342. #define S3C2410_GPC_PUPDIS(x) (1<<(x))
  343. /*
  344. * S3C2410: Port D consists of 16 GPIO/Special function
  345. *
  346. * almost identical setup to port b, but the special functions are mostly
  347. * to do with the video system's data.
  348. *
  349. * S3C2400: Port D consists of 11 GPIO/Special function
  350. *
  351. * almost identical setup to port c
  352. */
  353. #define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
  354. #define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
  355. #define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
  356. #define S3C2400_GPDCON S3C2410_GPIOREG(0x20)
  357. #define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
  358. #define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
  359. #define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
  360. #define S3C2410_GPD0_INP (0x00 << 0)
  361. #define S3C2410_GPD0_OUTP (0x01 << 0)
  362. #define S3C2410_GPD0_VD8 (0x02 << 0)
  363. #define S3C2400_GPD0_VFRAME (0x02 << 0)
  364. #define S3C2442_GPD0_nSPICS1 (0x03 << 0)
  365. #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
  366. #define S3C2410_GPD1_INP (0x00 << 2)
  367. #define S3C2410_GPD1_OUTP (0x01 << 2)
  368. #define S3C2410_GPD1_VD9 (0x02 << 2)
  369. #define S3C2400_GPD1_VM (0x02 << 2)
  370. #define S3C2442_GPD1_SPICLK1 (0x03 << 2)
  371. #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
  372. #define S3C2410_GPD2_INP (0x00 << 4)
  373. #define S3C2410_GPD2_OUTP (0x01 << 4)
  374. #define S3C2410_GPD2_VD10 (0x02 << 4)
  375. #define S3C2400_GPD2_VLINE (0x02 << 4)
  376. #define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
  377. #define S3C2410_GPD3_INP (0x00 << 6)
  378. #define S3C2410_GPD3_OUTP (0x01 << 6)
  379. #define S3C2410_GPD3_VD11 (0x02 << 6)
  380. #define S3C2400_GPD3_VCLK (0x02 << 6)
  381. #define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
  382. #define S3C2410_GPD4_INP (0x00 << 8)
  383. #define S3C2410_GPD4_OUTP (0x01 << 8)
  384. #define S3C2410_GPD4_VD12 (0x02 << 8)
  385. #define S3C2400_GPD4_LEND (0x02 << 8)
  386. #define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
  387. #define S3C2410_GPD5_INP (0x00 << 10)
  388. #define S3C2410_GPD5_OUTP (0x01 << 10)
  389. #define S3C2410_GPD5_VD13 (0x02 << 10)
  390. #define S3C2400_GPD5_TOUT0 (0x02 << 10)
  391. #define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
  392. #define S3C2410_GPD6_INP (0x00 << 12)
  393. #define S3C2410_GPD6_OUTP (0x01 << 12)
  394. #define S3C2410_GPD6_VD14 (0x02 << 12)
  395. #define S3C2400_GPD6_TOUT1 (0x02 << 12)
  396. #define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
  397. #define S3C2410_GPD7_INP (0x00 << 14)
  398. #define S3C2410_GPD7_OUTP (0x01 << 14)
  399. #define S3C2410_GPD7_VD15 (0x02 << 14)
  400. #define S3C2400_GPD7_TOUT2 (0x02 << 14)
  401. #define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
  402. #define S3C2410_GPD8_INP (0x00 << 16)
  403. #define S3C2410_GPD8_OUTP (0x01 << 16)
  404. #define S3C2410_GPD8_VD16 (0x02 << 16)
  405. #define S3C2400_GPD8_TOUT3 (0x02 << 16)
  406. #define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
  407. #define S3C2410_GPD9_INP (0x00 << 18)
  408. #define S3C2410_GPD9_OUTP (0x01 << 18)
  409. #define S3C2410_GPD9_VD17 (0x02 << 18)
  410. #define S3C2400_GPD9_TCLK0 (0x02 << 18)
  411. #define S3C2410_GPD9_MASK (0x03 << 18)
  412. #define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
  413. #define S3C2410_GPD10_INP (0x00 << 20)
  414. #define S3C2410_GPD10_OUTP (0x01 << 20)
  415. #define S3C2410_GPD10_VD18 (0x02 << 20)
  416. #define S3C2400_GPD10_nWAIT (0x02 << 20)
  417. #define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
  418. #define S3C2410_GPD11_INP (0x00 << 22)
  419. #define S3C2410_GPD11_OUTP (0x01 << 22)
  420. #define S3C2410_GPD11_VD19 (0x02 << 22)
  421. #define S3C2410_GPD12 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
  422. #define S3C2410_GPD12_INP (0x00 << 24)
  423. #define S3C2410_GPD12_OUTP (0x01 << 24)
  424. #define S3C2410_GPD12_VD20 (0x02 << 24)
  425. #define S3C2410_GPD13 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
  426. #define S3C2410_GPD13_INP (0x00 << 26)
  427. #define S3C2410_GPD13_OUTP (0x01 << 26)
  428. #define S3C2410_GPD13_VD21 (0x02 << 26)
  429. #define S3C2410_GPD14 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
  430. #define S3C2410_GPD14_INP (0x00 << 28)
  431. #define S3C2410_GPD14_OUTP (0x01 << 28)
  432. #define S3C2410_GPD14_VD22 (0x02 << 28)
  433. #define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
  434. #define S3C2410_GPD15_INP (0x00 << 30)
  435. #define S3C2410_GPD15_OUTP (0x01 << 30)
  436. #define S3C2410_GPD15_VD23 (0x02 << 30)
  437. #define S3C2410_GPD_PUPDIS(x) (1<<(x))
  438. /* S3C2410:
  439. * Port E consists of 16 GPIO/Special function
  440. *
  441. * again, the same as port B, but dealing with I2S, SDI, and
  442. * more miscellaneous functions
  443. *
  444. * S3C2400:
  445. * Port E consists of 12 GPIO/Special function
  446. *
  447. * GPIO / interrupt inputs
  448. */
  449. #define S3C2410_GPECON S3C2410_GPIOREG(0x40)
  450. #define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
  451. #define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
  452. #define S3C2400_GPECON S3C2410_GPIOREG(0x2C)
  453. #define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
  454. #define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
  455. #define S3C2450_GPESEL S3C2410_GPIOREG(0x4C)
  456. #define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
  457. #define S3C2410_GPE0_INP (0x00 << 0)
  458. #define S3C2410_GPE0_OUTP (0x01 << 0)
  459. #define S3C2410_GPE0_I2SLRCK (0x02 << 0)
  460. #define S3C2443_GPE0_AC_nRESET (0x03 << 0)
  461. #define S3C2400_GPE0_EINT0 (0x02 << 0)
  462. #define S3C2410_GPE0_MASK (0x03 << 0)
  463. #define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
  464. #define S3C2410_GPE1_INP (0x00 << 2)
  465. #define S3C2410_GPE1_OUTP (0x01 << 2)
  466. #define S3C2410_GPE1_I2SSCLK (0x02 << 2)
  467. #define S3C2443_GPE1_AC_SYNC (0x03 << 2)
  468. #define S3C2400_GPE1_EINT1 (0x02 << 2)
  469. #define S3C2400_GPE1_nSS (0x03 << 2)
  470. #define S3C2410_GPE1_MASK (0x03 << 2)
  471. #define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
  472. #define S3C2410_GPE2_INP (0x00 << 4)
  473. #define S3C2410_GPE2_OUTP (0x01 << 4)
  474. #define S3C2410_GPE2_CDCLK (0x02 << 4)
  475. #define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
  476. #define S3C2400_GPE2_EINT2 (0x02 << 4)
  477. #define S3C2400_GPE2_I2SSDI (0x03 << 4)
  478. #define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
  479. #define S3C2410_GPE3_INP (0x00 << 6)
  480. #define S3C2410_GPE3_OUTP (0x01 << 6)
  481. #define S3C2410_GPE3_I2SSDI (0x02 << 6)
  482. #define S3C2443_GPE3_AC_SDI (0x03 << 6)
  483. #define S3C2400_GPE3_EINT3 (0x02 << 6)
  484. #define S3C2400_GPE3_nCTS1 (0x03 << 6)
  485. #define S3C2410_GPE3_nSS0 (0x03 << 6)
  486. #define S3C2410_GPE3_MASK (0x03 << 6)
  487. #define S3C2410_GPE4 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
  488. #define S3C2410_GPE4_INP (0x00 << 8)
  489. #define S3C2410_GPE4_OUTP (0x01 << 8)
  490. #define S3C2410_GPE4_I2SSDO (0x02 << 8)
  491. #define S3C2443_GPE4_AC_SDO (0x03 << 8)
  492. #define S3C2400_GPE4_EINT4 (0x02 << 8)
  493. #define S3C2400_GPE4_nRTS1 (0x03 << 8)
  494. #define S3C2410_GPE4_I2SSDI (0x03 << 8)
  495. #define S3C2410_GPE4_MASK (0x03 << 8)
  496. #define S3C2410_GPE5 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
  497. #define S3C2410_GPE5_INP (0x00 << 10)
  498. #define S3C2410_GPE5_OUTP (0x01 << 10)
  499. #define S3C2410_GPE5_SDCLK (0x02 << 10)
  500. #define S3C2443_GPE5_SD1_CLK (0x02 << 10)
  501. #define S3C2450_GPE5_SD0_CLK (0x02 << 10)
  502. #define S3C2400_GPE5_EINT5 (0x02 << 10)
  503. #define S3C2400_GPE5_TCLK1 (0x03 << 10)
  504. #define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
  505. #define S3C2410_GPE6_INP (0x00 << 12)
  506. #define S3C2410_GPE6_OUTP (0x01 << 12)
  507. #define S3C2410_GPE6_SDCMD (0x02 << 12)
  508. #define S3C2443_GPE6_SD1_CMD (0x02 << 12)
  509. #define S3C2450_GPE6_SD0_CMD (0x02 << 12)
  510. #define S3C2443_GPE6_AC_BITCLK (0x03 << 12)
  511. #define S3C2400_GPE6_EINT6 (0x02 << 12)
  512. #define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
  513. #define S3C2410_GPE7_INP (0x00 << 14)
  514. #define S3C2410_GPE7_OUTP (0x01 << 14)
  515. #define S3C2410_GPE7_SDDAT0 (0x02 << 14)
  516. #define S3C2443_GPE7_SD1_DAT0 (0x02 << 14)
  517. #define S3C2450_GPE7_SD0_DAT0 (0x02 << 14)
  518. #define S3C2443_GPE7_AC_SDI (0x03 << 14)
  519. #define S3C2400_GPE7_EINT7 (0x02 << 14)
  520. #define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
  521. #define S3C2410_GPE8_INP (0x00 << 16)
  522. #define S3C2410_GPE8_OUTP (0x01 << 16)
  523. #define S3C2410_GPE8_SDDAT1 (0x02 << 16)
  524. #define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
  525. #define S3C2450_GPE8_SD0_DAT1 (0x02 << 16)
  526. #define S3C2443_GPE8_AC_SDO (0x03 << 16)
  527. #define S3C2400_GPE8_nXDACK0 (0x02 << 16)
  528. #define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
  529. #define S3C2410_GPE9_INP (0x00 << 18)
  530. #define S3C2410_GPE9_OUTP (0x01 << 18)
  531. #define S3C2410_GPE9_SDDAT2 (0x02 << 18)
  532. #define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
  533. #define S3C2450_GPE9_SD0_DAT2 (0x02 << 18)
  534. #define S3C2443_GPE9_AC_SYNC (0x03 << 18)
  535. #define S3C2400_GPE9_nXDACK1 (0x02 << 18)
  536. #define S3C2400_GPE9_nXBACK (0x03 << 18)
  537. #define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
  538. #define S3C2410_GPE10_INP (0x00 << 20)
  539. #define S3C2410_GPE10_OUTP (0x01 << 20)
  540. #define S3C2410_GPE10_SDDAT3 (0x02 << 20)
  541. #define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
  542. #define S3C2450_GPE10_SD0_DAT3 (0x02 << 20)
  543. #define S3C2443_GPE10_AC_nRESET (0x03 << 20)
  544. #define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
  545. #define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
  546. #define S3C2410_GPE11_INP (0x00 << 22)
  547. #define S3C2410_GPE11_OUTP (0x01 << 22)
  548. #define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
  549. #define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
  550. #define S3C2400_GPE11_nXBREQ (0x03 << 22)
  551. #define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
  552. #define S3C2410_GPE12_INP (0x00 << 24)
  553. #define S3C2410_GPE12_OUTP (0x01 << 24)
  554. #define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
  555. #define S3C2410_GPE13 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
  556. #define S3C2410_GPE13_INP (0x00 << 26)
  557. #define S3C2410_GPE13_OUTP (0x01 << 26)
  558. #define S3C2410_GPE13_SPICLK0 (0x02 << 26)
  559. #define S3C2410_GPE14 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
  560. #define S3C2410_GPE14_INP (0x00 << 28)
  561. #define S3C2410_GPE14_OUTP (0x01 << 28)
  562. #define S3C2410_GPE14_IICSCL (0x02 << 28)
  563. #define S3C2410_GPE14_MASK (0x03 << 28)
  564. #define S3C2410_GPE15 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
  565. #define S3C2410_GPE15_INP (0x00 << 30)
  566. #define S3C2410_GPE15_OUTP (0x01 << 30)
  567. #define S3C2410_GPE15_IICSDA (0x02 << 30)
  568. #define S3C2410_GPE15_MASK (0x03 << 30)
  569. #define S3C2440_GPE0_ACSYNC (0x03 << 0)
  570. #define S3C2440_GPE1_ACBITCLK (0x03 << 2)
  571. #define S3C2440_GPE2_ACRESET (0x03 << 4)
  572. #define S3C2440_GPE3_ACIN (0x03 << 6)
  573. #define S3C2440_GPE4_ACOUT (0x03 << 8)
  574. #define S3C2410_GPE_PUPDIS(x) (1<<(x))
  575. /* S3C2410:
  576. * Port F consists of 8 GPIO/Special function
  577. *
  578. * GPIO / interrupt inputs
  579. *
  580. * GPFCON has 2 bits for each of the input pins on port F
  581. * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
  582. *
  583. * pull up works like all other ports.
  584. *
  585. * S3C2400:
  586. * Port F consists of 7 GPIO/Special function
  587. *
  588. * GPIO/serial/misc pins
  589. */
  590. #define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
  591. #define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
  592. #define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
  593. #define S3C2400_GPFCON S3C2410_GPIOREG(0x38)
  594. #define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
  595. #define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
  596. #define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
  597. #define S3C2410_GPF0_INP (0x00 << 0)
  598. #define S3C2410_GPF0_OUTP (0x01 << 0)
  599. #define S3C2410_GPF0_EINT0 (0x02 << 0)
  600. #define S3C2400_GPF0_RXD0 (0x02 << 0)
  601. #define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
  602. #define S3C2410_GPF1_INP (0x00 << 2)
  603. #define S3C2410_GPF1_OUTP (0x01 << 2)
  604. #define S3C2410_GPF1_EINT1 (0x02 << 2)
  605. #define S3C2400_GPF1_RXD1 (0x02 << 2)
  606. #define S3C2400_GPF1_IICSDA (0x03 << 2)
  607. #define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
  608. #define S3C2410_GPF2_INP (0x00 << 4)
  609. #define S3C2410_GPF2_OUTP (0x01 << 4)
  610. #define S3C2410_GPF2_EINT2 (0x02 << 4)
  611. #define S3C2400_GPF2_TXD0 (0x02 << 4)
  612. #define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
  613. #define S3C2410_GPF3_INP (0x00 << 6)
  614. #define S3C2410_GPF3_OUTP (0x01 << 6)
  615. #define S3C2410_GPF3_EINT3 (0x02 << 6)
  616. #define S3C2400_GPF3_TXD1 (0x02 << 6)
  617. #define S3C2400_GPF3_IICSCL (0x03 << 6)
  618. #define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
  619. #define S3C2410_GPF4_INP (0x00 << 8)
  620. #define S3C2410_GPF4_OUTP (0x01 << 8)
  621. #define S3C2410_GPF4_EINT4 (0x02 << 8)
  622. #define S3C2400_GPF4_nRTS0 (0x02 << 8)
  623. #define S3C2400_GPF4_nXBACK (0x03 << 8)
  624. #define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
  625. #define S3C2410_GPF5_INP (0x00 << 10)
  626. #define S3C2410_GPF5_OUTP (0x01 << 10)
  627. #define S3C2410_GPF5_EINT5 (0x02 << 10)
  628. #define S3C2400_GPF5_nCTS0 (0x02 << 10)
  629. #define S3C2400_GPF5_nXBREQ (0x03 << 10)
  630. #define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
  631. #define S3C2410_GPF6_INP (0x00 << 12)
  632. #define S3C2410_GPF6_OUTP (0x01 << 12)
  633. #define S3C2410_GPF6_EINT6 (0x02 << 12)
  634. #define S3C2400_GPF6_CLKOUT (0x02 << 12)
  635. #define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
  636. #define S3C2410_GPF7_INP (0x00 << 14)
  637. #define S3C2410_GPF7_OUTP (0x01 << 14)
  638. #define S3C2410_GPF7_EINT7 (0x02 << 14)
  639. #define S3C2410_GPF_PUPDIS(x) (1<<(x))
  640. /* S3C2410:
  641. * Port G consists of 8 GPIO/IRQ/Special function
  642. *
  643. * GPGCON has 2 bits for each of the input pins on port F
  644. * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
  645. *
  646. * pull up works like all other ports.
  647. *
  648. * S3C2400:
  649. * Port G consists of 10 GPIO/Special function
  650. */
  651. #define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
  652. #define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
  653. #define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
  654. #define S3C2400_GPGCON S3C2410_GPIOREG(0x44)
  655. #define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
  656. #define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
  657. #define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
  658. #define S3C2410_GPG0_INP (0x00 << 0)
  659. #define S3C2410_GPG0_OUTP (0x01 << 0)
  660. #define S3C2410_GPG0_EINT8 (0x02 << 0)
  661. #define S3C2400_GPG0_I2SLRCK (0x02 << 0)
  662. #define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
  663. #define S3C2410_GPG1_INP (0x00 << 2)
  664. #define S3C2410_GPG1_OUTP (0x01 << 2)
  665. #define S3C2410_GPG1_EINT9 (0x02 << 2)
  666. #define S3C2400_GPG1_I2SSCLK (0x02 << 2)
  667. #define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
  668. #define S3C2410_GPG2_INP (0x00 << 4)
  669. #define S3C2410_GPG2_OUTP (0x01 << 4)
  670. #define S3C2410_GPG2_EINT10 (0x02 << 4)
  671. #define S3C2400_GPG2_CDCLK (0x02 << 4)
  672. #define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
  673. #define S3C2410_GPG3_INP (0x00 << 6)
  674. #define S3C2410_GPG3_OUTP (0x01 << 6)
  675. #define S3C2410_GPG3_EINT11 (0x02 << 6)
  676. #define S3C2400_GPG3_I2SSDO (0x02 << 6)
  677. #define S3C2400_GPG3_I2SSDI (0x03 << 6)
  678. #define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
  679. #define S3C2410_GPG4_INP (0x00 << 8)
  680. #define S3C2410_GPG4_OUTP (0x01 << 8)
  681. #define S3C2410_GPG4_EINT12 (0x02 << 8)
  682. #define S3C2400_GPG4_MMCCLK (0x02 << 8)
  683. #define S3C2400_GPG4_I2SSDI (0x03 << 8)
  684. #define S3C2410_GPG4_LCDPWREN (0x03 << 8)
  685. #define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
  686. #define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
  687. #define S3C2410_GPG5_INP (0x00 << 10)
  688. #define S3C2410_GPG5_OUTP (0x01 << 10)
  689. #define S3C2410_GPG5_EINT13 (0x02 << 10)
  690. #define S3C2400_GPG5_MMCCMD (0x02 << 10)
  691. #define S3C2400_GPG5_IICSDA (0x03 << 10)
  692. #define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
  693. #define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
  694. #define S3C2410_GPG6_INP (0x00 << 12)
  695. #define S3C2410_GPG6_OUTP (0x01 << 12)
  696. #define S3C2410_GPG6_EINT14 (0x02 << 12)
  697. #define S3C2400_GPG6_MMCDAT (0x02 << 12)
  698. #define S3C2400_GPG6_IICSCL (0x03 << 12)
  699. #define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
  700. #define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
  701. #define S3C2410_GPG7_INP (0x00 << 14)
  702. #define S3C2410_GPG7_OUTP (0x01 << 14)
  703. #define S3C2410_GPG7_EINT15 (0x02 << 14)
  704. #define S3C2410_GPG7_SPICLK1 (0x03 << 14)
  705. #define S3C2400_GPG7_SPIMISO (0x02 << 14)
  706. #define S3C2400_GPG7_IICSDA (0x03 << 14)
  707. #define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
  708. #define S3C2410_GPG8_INP (0x00 << 16)
  709. #define S3C2410_GPG8_OUTP (0x01 << 16)
  710. #define S3C2410_GPG8_EINT16 (0x02 << 16)
  711. #define S3C2400_GPG8_SPIMOSI (0x02 << 16)
  712. #define S3C2400_GPG8_IICSCL (0x03 << 16)
  713. #define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
  714. #define S3C2410_GPG9_INP (0x00 << 18)
  715. #define S3C2410_GPG9_OUTP (0x01 << 18)
  716. #define S3C2410_GPG9_EINT17 (0x02 << 18)
  717. #define S3C2400_GPG9_SPICLK (0x02 << 18)
  718. #define S3C2400_GPG9_MMCCLK (0x03 << 18)
  719. #define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
  720. #define S3C2410_GPG10_INP (0x00 << 20)
  721. #define S3C2410_GPG10_OUTP (0x01 << 20)
  722. #define S3C2410_GPG10_EINT18 (0x02 << 20)
  723. #define S3C2410_GPG11 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
  724. #define S3C2410_GPG11_INP (0x00 << 22)
  725. #define S3C2410_GPG11_OUTP (0x01 << 22)
  726. #define S3C2410_GPG11_EINT19 (0x02 << 22)
  727. #define S3C2410_GPG11_TCLK1 (0x03 << 22)
  728. #define S3C2443_GPG11_CF_nIREQ (0x03 << 22)
  729. #define S3C2410_GPG12 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
  730. #define S3C2410_GPG12_INP (0x00 << 24)
  731. #define S3C2410_GPG12_OUTP (0x01 << 24)
  732. #define S3C2410_GPG12_EINT20 (0x02 << 24)
  733. #define S3C2410_GPG12_XMON (0x03 << 24)
  734. #define S3C2442_GPG12_nSPICS0 (0x03 << 24)
  735. #define S3C2443_GPG12_nINPACK (0x03 << 24)
  736. #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
  737. #define S3C2410_GPG13_INP (0x00 << 26)
  738. #define S3C2410_GPG13_OUTP (0x01 << 26)
  739. #define S3C2410_GPG13_EINT21 (0x02 << 26)
  740. #define S3C2410_GPG13_nXPON (0x03 << 26)
  741. #define S3C2443_GPG13_CF_nREG (0x03 << 26)
  742. #define S3C2410_GPG14 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
  743. #define S3C2410_GPG14_INP (0x00 << 28)
  744. #define S3C2410_GPG14_OUTP (0x01 << 28)
  745. #define S3C2410_GPG14_EINT22 (0x02 << 28)
  746. #define S3C2410_GPG14_YMON (0x03 << 28)
  747. #define S3C2443_GPG14_CF_RESET (0x03 << 28)
  748. #define S3C2410_GPG15 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
  749. #define S3C2410_GPG15_INP (0x00 << 30)
  750. #define S3C2410_GPG15_OUTP (0x01 << 30)
  751. #define S3C2410_GPG15_EINT23 (0x02 << 30)
  752. #define S3C2410_GPG15_nYPON (0x03 << 30)
  753. #define S3C2443_GPG15_CF_PWR (0x03 << 30)
  754. #define S3C2410_GPG_PUPDIS(x) (1<<(x))
  755. /* Port H consists of11 GPIO/serial/Misc pins
  756. *
  757. * GPGCON has 2 bits for each of the input pins on port F
  758. * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
  759. *
  760. * pull up works like all other ports.
  761. */
  762. #define S3C2410_GPHCON S3C2410_GPIOREG(0x70)
  763. #define S3C2410_GPHDAT S3C2410_GPIOREG(0x74)
  764. #define S3C2410_GPHUP S3C2410_GPIOREG(0x78)
  765. #define S3C2410_GPH0 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
  766. #define S3C2410_GPH0_INP (0x00 << 0)
  767. #define S3C2410_GPH0_OUTP (0x01 << 0)
  768. #define S3C2410_GPH0_nCTS0 (0x02 << 0)
  769. #define S3C2410_GPH1 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
  770. #define S3C2410_GPH1_INP (0x00 << 2)
  771. #define S3C2410_GPH1_OUTP (0x01 << 2)
  772. #define S3C2410_GPH1_nRTS0 (0x02 << 2)
  773. #define S3C2410_GPH2 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
  774. #define S3C2410_GPH2_INP (0x00 << 4)
  775. #define S3C2410_GPH2_OUTP (0x01 << 4)
  776. #define S3C2410_GPH2_TXD0 (0x02 << 4)
  777. #define S3C2410_GPH3 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
  778. #define S3C2410_GPH3_INP (0x00 << 6)
  779. #define S3C2410_GPH3_OUTP (0x01 << 6)
  780. #define S3C2410_GPH3_RXD0 (0x02 << 6)
  781. #define S3C2410_GPH4 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
  782. #define S3C2410_GPH4_INP (0x00 << 8)
  783. #define S3C2410_GPH4_OUTP (0x01 << 8)
  784. #define S3C2410_GPH4_TXD1 (0x02 << 8)
  785. #define S3C2410_GPH5 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
  786. #define S3C2410_GPH5_INP (0x00 << 10)
  787. #define S3C2410_GPH5_OUTP (0x01 << 10)
  788. #define S3C2410_GPH5_RXD1 (0x02 << 10)
  789. #define S3C2410_GPH6 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
  790. #define S3C2410_GPH6_INP (0x00 << 12)
  791. #define S3C2410_GPH6_OUTP (0x01 << 12)
  792. #define S3C2410_GPH6_TXD2 (0x02 << 12)
  793. #define S3C2410_GPH6_nRTS1 (0x03 << 12)
  794. #define S3C2410_GPH7 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
  795. #define S3C2410_GPH7_INP (0x00 << 14)
  796. #define S3C2410_GPH7_OUTP (0x01 << 14)
  797. #define S3C2410_GPH7_RXD2 (0x02 << 14)
  798. #define S3C2410_GPH7_nCTS1 (0x03 << 14)
  799. #define S3C2410_GPH8 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
  800. #define S3C2410_GPH8_INP (0x00 << 16)
  801. #define S3C2410_GPH8_OUTP (0x01 << 16)
  802. #define S3C2410_GPH8_UCLK (0x02 << 16)
  803. #define S3C2410_GPH9 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
  804. #define S3C2410_GPH9_INP (0x00 << 18)
  805. #define S3C2410_GPH9_OUTP (0x01 << 18)
  806. #define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
  807. #define S3C2442_GPH9_nSPICS0 (0x03 << 18)
  808. #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
  809. #define S3C2410_GPH10_INP (0x00 << 20)
  810. #define S3C2410_GPH10_OUTP (0x01 << 20)
  811. #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
  812. #define S3C2410_GPH11 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 11)
  813. #define S3C2410_GPH11_INP (0x00 << 22)
  814. #define S3C2410_GPH11_OUTP (0x01 << 22)
  815. #define S3C2410_GPH11_nRTS (0x02 << 22)
  816. #define S3C2410_GPH12 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
  817. #define S3C2410_GPH12_INP (0x00 << 24)
  818. #define S3C2410_GPH12_OUTP (0x01 << 24)
  819. #define S3C2410_GPH12_EXTUART (0x02 << 24)
  820. #define S3C2443_GPH13 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 13)
  821. #define S3C2443_GPH13_INP (0x00 << 26)
  822. #define S3C2443_GPH13_OUTP (0x01 << 26)
  823. #define S3C2443_GPH13_CLKOUT0 (0x02 << 26)
  824. #define S3C2443_GPH14 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 14)
  825. #define S3C2443_GPH14_INP (0x00 << 28)
  826. #define S3C2443_GPH14_OUTP (0x01 << 28)
  827. #define S3C2443_GPH14_CLKOUT1 (0x02 << 28)
  828. /* Port L consists of14 SPI1/Misc pins
  829. *
  830. * GPLCON has 2 bits for each of the input pins on port L
  831. * 00 = 0 input, 1 output,
  832. *
  833. * pull up works like all other ports.
  834. */
  835. #define S3C2410_GPLCON S3C2410_GPIOREG(0xf0)
  836. #define S3C2410_GPLDAT S3C2410_GPIOREG(0xf4)
  837. #define S3C2410_GPLUP S3C2410_GPIOREG(0xf8)
  838. #define S3C2450_GPLSEL S3C2410_GPIOREG(0xfC)
  839. #define S3C2410_GPL0 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 0)
  840. #define S3C2410_GPL0_INP (0x00 << 0)
  841. #define S3C2410_GPL0_OUTP (0x01 << 0)
  842. #define S3C2410_GPL0_SD0_DAT0 (0x02 << 0)
  843. #define S3C2410_GPL1 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 1)
  844. #define S3C2410_GPL1_INP (0x00 << 2)
  845. #define S3C2410_GPL1_OUTP (0x01 << 2)
  846. #define S3C2410_GPL1_SD0_DAT1 (0x02 << 2)
  847. #define S3C2410_GPL2 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 2)
  848. #define S3C2410_GPL2_INP (0x00 << 4)
  849. #define S3C2410_GPL2_OUTP (0x01 << 4)
  850. #define S3C2410_GPL2_SD0_DAT02 (0x02 << 4)
  851. #define S3C2410_GPL3 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 3)
  852. #define S3C2410_GPL3_INP (0x00 << 6)
  853. #define S3C2410_GPL3_OUTP (0x01 << 6)
  854. #define S3C2410_GPL3_SD0_DAT3 (0x02 << 6)
  855. #define S3C2410_GPL4 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 4)
  856. #define S3C2410_GPL4_INP (0x00 << 8)
  857. #define S3C2410_GPL4_OUTP (0x01 << 8)
  858. #define S3C2410_GPL4_SD0_DAT4 (0x02 << 8)
  859. #define S3C2450_GPL4_I2S1_SCLK (0x03 << 8)
  860. #define S3C2410_GPL5 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 5)
  861. #define S3C2410_GPL5_INP (0x00 << 10)
  862. #define S3C2410_GPL5_OUTP (0x01 << 10)
  863. #define S3C2410_GPL5_SD0_DAT5 (0x02 << 10)
  864. #define S3C2450_GPL5_I2S1_CDCLK (0x03 << 10)
  865. #define S3C2410_GPL6 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 6)
  866. #define S3C2410_GPL6_INP (0x00 << 12)
  867. #define S3C2410_GPL6_OUTP (0x01 << 12)
  868. #define S3C2410_GPL6_TXD2 (0x02 << 12)
  869. #define S3C2410_GPL6_SD0_DAT6 (0x03 << 12)
  870. #define S3C2450_GPL6_I2S1_SDI (0x03 << 12)
  871. #define S3C2410_GPL7 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 7)
  872. #define S3C2410_GPL7_INP (0x00 << 14)
  873. #define S3C2410_GPL7_OUTP (0x01 << 14)
  874. #define S3C2410_GPL7_RXD2 (0x02 << 14)
  875. #define S3C2410_GPL7_SD0_DAT7 (0x03 << 14)
  876. #define S3C2450_GPL7_I2S1_SDO (0x03 << 14)
  877. #define S3C2410_GPL8 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 8)
  878. #define S3C2410_GPL8_INP (0x00 << 16)
  879. #define S3C2410_GPL8_OUTP (0x01 << 16)
  880. #define S3C2410_GPL8_SD0_CMD (0x02 << 16)
  881. #define S3C2410_GPL9 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 9)
  882. #define S3C2410_GPL9_INP (0x00 << 18)
  883. #define S3C2410_GPL9_OUTP (0x01 << 18)
  884. #define S3C2410_GPL9_SD0_CLK (0x02 << 18)
  885. #define S3C2442_GPL9_nSPICS0 (0x03 << 18)
  886. #define S3C2410_GPL10 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 10)
  887. #define S3C2410_GPL10_INP (0x00 << 20)
  888. #define S3C2410_GPL10_OUTP (0x01 << 20)
  889. #define S3C2410_GPL10_SPICLK1 (0x02 << 20)
  890. #define S3C2410_GPL11 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 11)
  891. #define S3C2410_GPL11_INP (0x00 << 22)
  892. #define S3C2410_GPL11_OUTP (0x01 << 22)
  893. #define S3C2410_GPL11_SPIMOSI1 (0x02 << 22)
  894. #define S3C2410_GPL12 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 12)
  895. #define S3C2410_GPL12_INP (0x00 << 24)
  896. #define S3C2410_GPL12_OUTP (0x01 << 24)
  897. #define S3C2410_GPL12_SPIMISO1 (0x02 << 24)
  898. #define S3C2410_GPL13 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 13)
  899. #define S3C2410_GPL13_INP (0x00 << 26)
  900. #define S3C2410_GPL13_OUTP (0x01 << 26)
  901. #define S3C2410_GPL13_SS0 (0x02 << 26)
  902. #define S3C2410_GPL14 S3C2410_GPIONO(S3C2410_GPIO_BANKL, 14)
  903. #define S3C2410_GPL14_INP (0x00 << 28)
  904. #define S3C2410_GPL14_OUTP (0x01 << 28)
  905. #define S3C2410_GPL14_SS1 (0x02 << 28)
  906. /* Port L consists of14 SPI1/Misc pins
  907. *
  908. * GPLCON has 2 bits for each of the input pins on port L
  909. * 00 = 0 input, 1 output,
  910. *
  911. * pull up works like all other ports.
  912. */
  913. #define S3C2410_GPLCON S3C2410_GPIOREG(0xf0)
  914. #define S3C2410_GPLDAT S3C2410_GPIOREG(0xf4)
  915. #define S3C2410_GPLUP S3C2410_GPIOREG(0xf8)
  916. #define S3C2450_GPLSEL S3C2410_GPIOREG(0xfC)
  917. #define S3C2410_GPK0 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 0)
  918. #define S3C2410_GPK0_INP (0x00 << 0)
  919. #define S3C2410_GPK0_OUTP (0x01 << 0)
  920. #define S3C2410_GPK1 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 1)
  921. #define S3C2410_GPK1_INP (0x00 << 2)
  922. #define S3C2410_GPK1_OUTP (0x01 << 2)
  923. #define S3C2410_GPK2 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 2)
  924. #define S3C2410_GPK2_INP (0x00 << 4)
  925. #define S3C2410_GPK2_OUTP (0x01 << 4)
  926. #define S3C2410_GPK3 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 3)
  927. #define S3C2410_GPK3_INP (0x00 << 6)
  928. #define S3C2410_GPK3_OUTP (0x01 << 6)
  929. #define S3C2410_GPK4 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 4)
  930. #define S3C2410_GPK4_INP (0x00 << 8)
  931. #define S3C2410_GPK4_OUTP (0x01 << 8)
  932. #define S3C2410_GPK5 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 5)
  933. #define S3C2410_GPK5_INP (0x00 << 10)
  934. #define S3C2410_GPK5_OUTP (0x01 << 10)
  935. #define S3C2410_GPK6 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 6)
  936. #define S3C2410_GPK6_INP (0x00 << 12)
  937. #define S3C2410_GPK6_OUTP (0x01 << 12)
  938. #define S3C2410_GPK7 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 7)
  939. #define S3C2410_GPK7_INP (0x00 << 14)
  940. #define S3C2410_GPK7_OUTP (0x01 << 14)
  941. #define S3C2410_GPK8 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 8)
  942. #define S3C2410_GPK8_INP (0x00 << 16)
  943. #define S3C2410_GPK8_OUTP (0x01 << 16)
  944. #define S3C2410_GPK9 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 9)
  945. #define S3C2410_GPK9_INP (0x00 << 18)
  946. #define S3C2410_GPK9_OUTP (0x01 << 18)
  947. #define S3C2410_GPK10 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 10)
  948. #define S3C2410_GPK10_INP (0x00 << 20)
  949. #define S3C2410_GPK10_OUTP (0x01 << 20)
  950. #define S3C2410_GPK11 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 11)
  951. #define S3C2410_GPK11_INP (0x00 << 22)
  952. #define S3C2410_GPK11_OUTP (0x01 << 22)
  953. #define S3C2410_GPK12 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 12)
  954. #define S3C2410_GPK12_INP (0x00 << 24)
  955. #define S3C2410_GPK12_OUTP (0x01 << 24)
  956. #define S3C2410_GPK13 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 13)
  957. #define S3C2410_GPK13_INP (0x00 << 26)
  958. #define S3C2410_GPK13_OUTP (0x01 << 26)
  959. #define S3C2410_GPK14 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 14)
  960. #define S3C2410_GPK14_INP (0x00 << 28)
  961. #define S3C2410_GPK14_OUTP (0x01 << 28)
  962. #define S3C2410_GPK15 S3C2410_GPIONO(S3C2410_GPIO_BANKK, 15)
  963. #define S3C2410_GPK15_INP (0x00 << 30)
  964. #define S3C2410_GPK15_OUTP (0x01 << 30)
  965. /*2009/7/17,Qisda Leo SJ Yang Set GPK3 for enabling SD_POWER{*/
  966. #define S3C2416_GPLCON S3C2410_GPIOREG(0xF0)
  967. #define S3C2416_GPLDAT S3C2410_GPIOREG(0xF4)
  968. #define S3C2416_GPLUDP S3C2410_GPIOREG(0xF8)
  969. #define S3C2416_GPKCON S3C2410_GPIOREG(0xE0)
  970. #define S3C2416_GPKDAT S3C2410_GPIOREG(0xE4)
  971. #define S3C2416_GPKUDP S3C2410_GPIOREG(0xE8)
  972. #define S3C2416_GPIO_BANKK (32*13)
  973. /*}2009/7/17,Qisda Leo SJ Yang Set GPK3 for enabling SD_POWER*/
  974. /* The S3C2412 and S3C2413 move the GPJ register set to after
  975. * GPH, which means all registers after 0x80 are now offset by 0x10
  976. * for the 2412/2413 from the 2410/2440/2442
  977. */
  978. /* miscellaneous control */
  979. #define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
  980. #define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
  981. #define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
  982. #define S3C24XX_DCLKCON S3C24XX_GPIOREG2(0x84)
  983. /* see clock.h for dclk definitions */
  984. /* pullup control on databus */
  985. #define S3C2410_MISCCR_SPUCR_HEN (0<<0)
  986. #define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
  987. #define S3C2410_MISCCR_SPUCR_LEN (0<<1)
  988. #define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
  989. #define S3C2400_MISCCR_SPUCR_LEN (0<<0)
  990. #define S3C2400_MISCCR_SPUCR_LDIS (1<<0)
  991. #define S3C2400_MISCCR_SPUCR_HEN (0<<1)
  992. #define S3C2400_MISCCR_SPUCR_HDIS (1<<1)
  993. #define S3C2400_MISCCR_HZ_STOPEN (0<<2)
  994. #define S3C2400_MISCCR_HZ_STOPPREV (1<<2)
  995. #define S3C2410_MISCCR_USBDEV (0<<3)
  996. #define S3C2410_MISCCR_USBHOST (1<<3)
  997. #define S3C2410_MISCCR_CLK0_MPLL (0<<4)
  998. #define S3C2410_MISCCR_CLK0_UPLL (1<<4)
  999. #define S3C2410_MISCCR_CLK0_FCLK (2<<4)
  1000. #define S3C2410_MISCCR_CLK0_HCLK (3<<4)
  1001. #define S3C2410_MISCCR_CLK0_PCLK (4<<4)
  1002. #define S3C2410_MISCCR_CLK0_DCLK0 (5<<4)
  1003. #define S3C2410_MISCCR_CLK0_MASK (7<<4)
  1004. #define S3C2412_MISCCR_CLK0_RTC (2<<4)
  1005. #define S3C2410_MISCCR_CLK1_MPLL (0<<8)
  1006. #define S3C2410_MISCCR_CLK1_UPLL (1<<8)
  1007. #define S3C2410_MISCCR_CLK1_FCLK (2<<8)
  1008. #define S3C2410_MISCCR_CLK1_HCLK (3<<8)
  1009. #define S3C2410_MISCCR_CLK1_PCLK (4<<8)
  1010. #define S3C2410_MISCCR_CLK1_DCLK1 (5<<8)
  1011. #define S3C2410_MISCCR_CLK1_MASK (7<<8)
  1012. #define S3C2412_MISCCR_CLK1_CLKsrc (0<<8)
  1013. #define S3C2410_MISCCR_USBSUSPND0 (1<<12)
  1014. #define S3C2410_MISCCR_USBSUSPND1 (1<<13)
  1015. #define S3C2410_MISCCR_nRSTCON (1<<16)
  1016. #define S3C2410_MISCCR_nEN_SCLK0 (1<<17)
  1017. #define S3C2410_MISCCR_nEN_SCLK1 (1<<18)
  1018. #define S3C2410_MISCCR_nEN_SCLKE (1<<19) /* not 2412 */
  1019. #define S3C2410_MISCCR_SDSLEEP (7<<17)
  1020. /* external interrupt control... */
  1021. /* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
  1022. * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
  1023. * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
  1024. *
  1025. * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
  1026. *
  1027. * Samsung datasheet p9-25
  1028. */
  1029. #define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58)
  1030. #define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
  1031. #define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
  1032. #define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
  1033. #define S3C24XX_EXTINT0 S3C24XX_GPIOREG2(0x88)
  1034. #define S3C24XX_EXTINT1 S3C24XX_GPIOREG2(0x8C)
  1035. #define S3C24XX_EXTINT2 S3C24XX_GPIOREG2(0x90)
  1036. /* values for S3C2410_EXTINT0/1/2 */
  1037. #define S3C2410_EXTINT_LOWLEV (0x00)
  1038. #define S3C2410_EXTINT_HILEV (0x01)
  1039. #define S3C2410_EXTINT_FALLEDGE (0x02)
  1040. #define S3C2410_EXTINT_RISEEDGE (0x04)
  1041. #define S3C2410_EXTINT_BOTHEDGE (0x06)
  1042. /* interrupt filtering conrrol for EINT16..EINT23 */
  1043. #define S3C2410_EINFLT0 S3C2410_GPIOREG(0x94)
  1044. #define S3C2410_EINFLT1 S3C2410_GPIOREG(0x98)
  1045. #define S3C2410_EINFLT2 S3C2410_GPIOREG(0x9C)
  1046. #define S3C2410_EINFLT3 S3C2410_GPIOREG(0xA0)
  1047. #define S3C24XX_EINFLT0 S3C24XX_GPIOREG2(0x94)
  1048. #define S3C24XX_EINFLT1 S3C24XX_GPIOREG2(0x98)
  1049. #define S3C24XX_EINFLT2 S3C24XX_GPIOREG2(0x9C)
  1050. #define S3C24XX_EINFLT3 S3C24XX_GPIOREG2(0xA0)
  1051. /* values for interrupt filtering */
  1052. #define S3C2410_EINTFLT_PCLK (0x00)
  1053. #define S3C2410_EINTFLT_EXTCLK (1<<7)
  1054. #define S3C2410_EINTFLT_WIDTHMSK(x) ((x) & 0x3f)
  1055. /* removed EINTxxxx defs from here, not meant for this */
  1056. /* GSTATUS have miscellaneous information in them
  1057. *
  1058. * These move between s3c2410 and s3c2412 style systems.
  1059. */
  1060. #define S3C2410_GSTATUS0 S3C2410_GPIOREG(0x0AC)
  1061. #define S3C2410_GSTATUS1 S3C2410_GPIOREG(0x0B0)
  1062. #define S3C2410_GSTATUS2 S3C2410_GPIOREG(0x0B4)
  1063. #define S3C2410_GSTATUS3 S3C2410_GPIOREG(0x0B8)
  1064. #define S3C2410_GSTATUS4 S3C2410_GPIOREG(0x0BC)
  1065. #define S3C2412_GSTATUS0 S3C2410_GPIOREG(0x0BC)
  1066. #define S3C2412_GSTATUS1 S3C2410_GPIOREG(0x0C0)
  1067. #define S3C2412_GSTATUS2 S3C2410_GPIOREG(0x0C4)
  1068. #define S3C2412_GSTATUS3 S3C2410_GPIOREG(0x0C8)
  1069. #define S3C2412_GSTATUS4 S3C2410_GPIOREG(0x0CC)
  1070. #define S3C24XX_GSTATUS0 S3C24XX_GPIOREG2(0x0AC)
  1071. #define S3C24XX_GSTATUS1 S3C24XX_GPIOREG2(0x0B0)
  1072. #define S3C24XX_GSTATUS2 S3C24XX_GPIOREG2(0x0B4)
  1073. #define S3C24XX_GSTATUS3 S3C24XX_GPIOREG2(0x0B8)
  1074. #define S3C24XX_GSTATUS4 S3C24XX_GPIOREG2(0x0BC)
  1075. #define S3C2410_GSTATUS0_nWAIT (1<<3)
  1076. #define S3C2410_GSTATUS0_NCON (1<<2)
  1077. #define S3C2410_GSTATUS0_RnB (1<<1)
  1078. #define S3C2410_GSTATUS0_nBATTFLT (1<<0)
  1079. #define S3C2410_GSTATUS1_IDMASK (0xffff0000)
  1080. #define S3C2410_GSTATUS1_2410 (0x32410000)
  1081. #define S3C2410_GSTATUS1_2412 (0x32412001)
  1082. #define S3C2410_GSTATUS1_2440 (0x32440000)
  1083. #define S3C2410_GSTATUS1_2442 (0x32440aaa)
  1084. #define S3C2410_GSTATUS2_WTRESET (1<<2)
  1085. #define S3C2410_GSTATUS2_OFFRESET (1<<1)
  1086. #define S3C2410_GSTATUS2_PONRESET (1<<0)
  1087. /* open drain control register */
  1088. #define S3C2400_OPENCR S3C2410_GPIOREG(0x50)
  1089. #define S3C2400_OPENCR_OPC_RXD1DIS (0<<0)
  1090. #define S3C2400_OPENCR_OPC_RXD1EN (1<<0)
  1091. #define S3C2400_OPENCR_OPC_TXD1DIS (0<<1)
  1092. #define S3C2400_OPENCR_OPC_TXD1EN (1<<1)
  1093. #define S3C2400_OPENCR_OPC_CMDDIS (0<<2)
  1094. #define S3C2400_OPENCR_OPC_CMDEN (1<<2)
  1095. #define S3C2400_OPENCR_OPC_DATDIS (0<<3)
  1096. #define S3C2400_OPENCR_OPC_DATEN (1<<3)
  1097. #define S3C2400_OPENCR_OPC_MISODIS (0<<4)
  1098. #define S3C2400_OPENCR_OPC_MISOEN (1<<4)
  1099. #define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
  1100. #define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
  1101. /* 2412/2413 sleep configuration registers */
  1102. #define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
  1103. #define S3C2412_GPCSLPCON S3C2410_GPIOREG(0x2C)
  1104. #define S3C2412_GPDSLPCON S3C2410_GPIOREG(0x3C)
  1105. #define S3C2412_GPESLPCON S3C2410_GPIOREG(0x4C)
  1106. #define S3C2412_GPFSLPCON S3C2410_GPIOREG(0x5C)
  1107. #define S3C2412_GPGSLPCON S3C2410_GPIOREG(0x6C)
  1108. #define S3C2412_GPHSLPCON S3C2410_GPIOREG(0x7C)
  1109. /* definitions for each pin bit */
  1110. #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2))
  1111. #define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2))
  1112. #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2))
  1113. #define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2))
  1114. #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2))
  1115. /* definitions for power domain SDRAM and SRAM */
  1116. #define S3C2450_PDDMCON S3C2410_GPIOREG(0x114)
  1117. #define S3C2450_PDSMCON S3C2410_GPIOREG(0x118)
  1118. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  1119. /* configure GPIO ports A..G */
  1120. #define S3C_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
  1121. /* GPIO */
  1122. #define S3C_GPIONO(bank,offset) ((bank) + (offset))
  1123. #define S3C_GPIO_BANKA (32*0)
  1124. #define S3C_GPIO_BANKB (32*1)
  1125. #define S3C_GPIO_BANKC (32*2)
  1126. #define S3C_GPIO_BANKD (32*3)
  1127. #define S3C_GPIO_BANKE (32*4)
  1128. #define S3C_GPIO_BANKF (32*5)
  1129. #define S3C_GPIO_BANKG (32*6)
  1130. #define S3C_GPIO_BANKH (32*7)
  1131. #define S3C_GPIO_BANKI (32*8)
  1132. #define S3C_GPIO_BANKJ (32*9)
  1133. #define S3C_GPIO_BANKO (32*10)
  1134. #define S3C_GPIO_BANKP (32*11)
  1135. #define S3C_GPIO_BANKQ (32*12)
  1136. #define S3C_GPIO_BANKK (32*13)
  1137. #define S3C_GPIO_BANKL (32*14)
  1138. #define S3C_GPIO_BANKM (32*15)
  1139. #define S3C_GPIO_BANKN (32*16)
  1140. #define S3C_GPIO_BASE(pin) ((pin & ~31) >> 5)
  1141. #define S3C_GPIO_OFFSET(pin) (pin & 31)
  1142. /* general configuration options */
  1143. #define S3C_GPIO_LEAVE (0xFFFFFFFF)
  1144. /* GPA : 8 in/out port . UART */
  1145. #define S3C_GPADAT S3C_GPIOREG(0x04)
  1146. #define S3C_GPACON S3C_GPIOREG(0x00)
  1147. #define S3C_GPAPU S3C_GPIOREG(0x08)
  1148. #define S3C_GPASLPCON S3C_GPIOREG(0x0C)
  1149. #define S3C_GPA0 S3C_GPIONO(S3C_GPIO_BANKA, 0)
  1150. #define S3C_GPA0_INP (0)
  1151. #define S3C_GPA0_OUTP (1)
  1152. #define S3C_GPA0_UART_RXD0 (2)
  1153. #define S3C_GPA0_EXT_INT_G1_0 (7)
  1154. #define S3C_GPA1 S3C_GPIONO(S3C_GPIO_BANKA, 1)
  1155. #define S3C_GPA1_INP (0)
  1156. #define S3C_GPA1_OUTP (1)
  1157. #define S3C_GPA1_UART_TXD0 (2)
  1158. #define S3C_GPA1_EXT_INT_G1_1 (7)
  1159. #define S3C_GPA2 S3C_GPIONO(S3C_GPIO_BANKA, 2)
  1160. #define S3C_GPA2_INP (0)
  1161. #define S3C_GPA2_OUTP (1)
  1162. #define S3C_GPA2_UART_CTS0 (2)
  1163. #define S3C_GPA2_ADDR_CF0 (5)
  1164. #define S3C_GPA2_EXT_INT_G1_2 (7)
  1165. #define S3C_GPA3 S3C_GPIONO(S3C_GPIO_BANKA, 3)
  1166. #define S3C_GPA3_INP (0)
  1167. #define S3C_GPA3_OUTP (1)
  1168. #define S3C_GPA3_UART_RTS0 (2)
  1169. #define S3C_GPA3_ADDR_CF1 (5)
  1170. #define S3C_GPA3_EXT_INT_G1_3 (7)
  1171. #define S3C_GPA4 S3C_GPIONO(S3C_GPIO_BANKA, 4)
  1172. #define S3C_GPA4_INP (0)
  1173. #define S3C_GPA4_OUTP (1)
  1174. #define S3C_GPA4_UART_RXD1 (2)
  1175. #define S3C_GPA4_EXT_INT_G1_4 (7)
  1176. #define S3C_GPA5 S3C_GPIONO(S3C_GPIO_BANKA, 5)
  1177. #define S3C_GPA5_INP (0)
  1178. #define S3C_GPA5_OUTP (1)
  1179. #define S3C_GPA5_UART_TXD1 (2)
  1180. #define S3C_GPA5_EXT_INT_G1_5 (7)
  1181. #define S3C_GPA6 S3C_GPIONO(S3C_GPIO_BANKA, 6)
  1182. #define S3C_GPA6_INP (0)
  1183. #define S3C_GPA6_OUTP (1)
  1184. #define S3C_GPA6_UART_CTS1 (2)
  1185. #define S3C_GPA6_ADDR_CF0 (5)
  1186. #define S3C_GPA6_EXT_INT_G1_6 (7)
  1187. #define S3C_GPA7 S3C_GPIONO(S3C_GPIO_BANKA, 7)
  1188. #define S3C_GPA7_INP (0)
  1189. #define S3C_GPA7_OUTP (1)
  1190. #define S3C_GPA7_UART_RTS1 (2)
  1191. #define S3C_GPA7_ADDR_CF1 (5)
  1192. #define S3C_GPA7_EXT_INT_G1_7 (7)
  1193. /* GPB : 7 in/out port . UART, IrDA, External DMA, I2C */
  1194. #define S3C_GPBDAT S3C_GPIOREG(0x24)
  1195. #define S3C_GPBCON S3C_GPIOREG(0x20)
  1196. #define S3C_GPBPU S3C_GPIOREG(0x28)
  1197. #define S3C_GPBSLPCON S3C_GPIOREG(0x2C)
  1198. #define S3C_GPB0 S3C_GPIONO(S3C_GPIO_BANKB, 0)
  1199. #define S3C_GPB0_INP (0)
  1200. #define S3C_GPB0_OUTP (1)
  1201. #define S3C_GPB0_UART_RXD2 (2)
  1202. #define S3C_GPB0_EXT_DMA_REQ (3)
  1203. #define S3C_GPB0_IRDA_RXD (4)
  1204. #define S3C_GPB0_ADDR_CF0 (5)
  1205. #define S3C_GPB0_RESERVED (6)
  1206. #define S3C_GPB0_EXT_INT_G1_8 (7)
  1207. #define S3C_GPB1 S3C_GPIONO(S3C_GPIO_BANKB, 1)
  1208. #define S3C_GPB1_INP (0)
  1209. #define S3C_GPB1_OUTP (1)
  1210. #define S3C_GPB1_UART_TXD2 (2)
  1211. #define S3C_GPB1_EXT_DMA_ACK (3)
  1212. #define S3C_GPB1_IRDA_TXD (4)
  1213. #define S3C_GPB1_ADDR_CF1 (5)
  1214. #define S3C_GPB1_RESERVED (6)
  1215. #define S3C_GPB1_EXT_INT_G1_9 (7)
  1216. #define S3C_GPB2 S3C_GPIONO(S3C_GPIO_BANKB, 2)
  1217. #define S3C_GPB2_INP (0)
  1218. #define S3C_GPB2_OUTP (1)
  1219. #define S3C_GPB2_UART_RXD3 (2)
  1220. #define S3C_GPB2_IRDA_RXD (3)
  1221. #define S3C_GPB2_EXT_DMA_REQ (4)
  1222. #define S3C_GPB2_ADDR_CF2 (5)
  1223. #define S3C_GPB2_RESERVED (6)
  1224. #define S3C_GPB2_EXT_INT_G1_10 (7)
  1225. #define S3C_GPB3 S3C_GPIONO(S3C_GPIO_BANKB, 3)
  1226. #define S3C_GPB3_INP (0)
  1227. #define S3C_GPB3_OUTP (1)
  1228. #define S3C_GPB3_UART_TXD3 (2)
  1229. #define S3C_GPB3_IRDA_RXD (3)
  1230. #define S3C_GPB3_EXT_DMA_ACK (4)
  1231. #define S3C_GPB3_RESERVED1 (5)
  1232. #define S3C_GPB3_RESERVED2 (6)
  1233. #define S3C_GPB3_EXT_INT_G1_11 (7)
  1234. #define S3C_GPB4 S3C_GPIONO(S3C_GPIO_BANKB, 4)
  1235. #define S3C_GPB4_INP (0)
  1236. #define S3C_GPB4_OUTP (1)
  1237. #define S3C_GPB4_IRDA_SDBW (2)
  1238. #define S3C_GPB4_RESERVED1 (3)
  1239. #define S3C_GPB4_CF_DATA_DIR (4)
  1240. #define S3C_GPB4_RESERVED2 (5)
  1241. #define S3C_GPB4_RESERVED3 (6)
  1242. #define S3C_GPB4_EXT_INT_G1_12 (7)
  1243. #define S3C_GPB5 S3C_GPIONO(S3C_GPIO_BANKB, 5)
  1244. #define S3C_GPB5_INP (0)
  1245. #define S3C_GPB5_OUTP (1)
  1246. #define S3C_GPB5_I2C_SCL (2)
  1247. #define S3C_GPB5_RESERVED1 (3)
  1248. #define S3C_GPB5_RESERVED2 (4)
  1249. #define S3C_GPB5_RESERVED3 (5)
  1250. #define S3C_GPB5_RESERVED4 (6)
  1251. #define S3C_GPB5_EXT_INT_G1_13 (7)
  1252. #define S3C_GPB6 S3C_GPIONO(S3C_GPIO_BANKB, 6)
  1253. #define S3C_GPB6_INP (0)
  1254. #define S3C_GPB6_OUTP (1)
  1255. #define S3C_GPB6_I2C_SDA (2)
  1256. #define S3C_GPB6_RESERVED1 (3)
  1257. #define S3C_GPB6_RESERVED2 (4)
  1258. #define S3C_GPB6_RESERVED3 (5)
  1259. #define S3C_GPB6_RESERVED (6)
  1260. #define S3C_GPB6_EXT_INT_G1_14 (7)
  1261. /* GPC : 8 in/out port . SPI */
  1262. #define S3C_GPCDAT S3C_GPIOREG(0x44)
  1263. #define S3C_GPCCON S3C_GPIOREG(0x40)
  1264. #define S3C_GPCPU S3C_GPIOREG(0x48)
  1265. #define S3C_GPCSLPCON S3C_GPIOREG(0x4C)
  1266. #define S3C_GPC0 S3C_GPIONO(S3C_GPIO_BANKC, 0)
  1267. #define S3C_GPC0_INP (0)
  1268. #define S3C_GPC0_OUTP (1)
  1269. #define S3C_GPC0_SPI_MISO0 (2)
  1270. #define S3C_GPC0_RESERVED1 (3)
  1271. #define S3C_GPC0_RESERVED2 (4)
  1272. #define S3C_GPC0_ADDR_CF0 (5)
  1273. #define S3C_GBP0_RESERVED3 (6)
  1274. #define S3C_GPC0_EXT_INT_G2_0 (7)
  1275. #define S3C_GPC1 S3C_GPIONO(S3C_GPIO_BANKC, 1)
  1276. #define S3C_GPC1_INP (0)
  1277. #define S3C_GPC1_OUTP (1)
  1278. #define S3C_GPC1_SPI_CLK0 (2)
  1279. #define S3C_GPC1_RESERVED1 (3)
  1280. #define S3C_GPC1_RESERVED2 (4)
  1281. #define S3C_GPC1_ADDR_CF1 (5)
  1282. #define S3C_GPC1_RESERVED3 (6)
  1283. #define S3C_GPC1_EXT_INT_G2_1 (7)
  1284. #define S3C_GPC2 S3C_GPIONO(S3C_GPIO_BANKC, 2)
  1285. #define S3C_GPC2_INP (0)
  1286. #define S3C_GPC2_OUTP (1)
  1287. #define S3C_GPC2_SPI_MOSI0 (2)
  1288. #define S3C_GPC2_RESERVED1 (3)
  1289. #define S3C_GPC2_RESERVED2 (4)
  1290. #define S3C_GPC2_ADDR_CF2 (5)
  1291. #define S3C_GPC2_RESERVED3 (6)
  1292. #define S3C_GPC2_EXT_INT_G2_2 (7)
  1293. #define S3C_GPC3 S3C_GPIONO(S3C_GPIO_BANKC, 3)
  1294. #define S3C_GPC3_INP (0)
  1295. #define S3C_GPC3_OUTP (1)
  1296. #define S3C_GPC3_SPI_CS0 (2)
  1297. #define S3C_GPC3_RESERVED1 (3)
  1298. #define S3C_GPC3_RESERVED2 (4)
  1299. #define S3C_GPC3_RESERVED3 (5)
  1300. #define S3C_GPC3_RESERVED4 (6)
  1301. #define S3C_GPC3_EXT_INT_G2_3 (7)
  1302. #define S3C_GPC4 S3C_GPIONO(S3C_GPIO_BANKC, 4)
  1303. #define S3C_GPC4_INP (0)
  1304. #define S3C_GPC4_OUTP (1)
  1305. #define S3C_GPC4_SPI_MISO1 (2)
  1306. #define S3C_GPC4_MMC_CMD2 (3)
  1307. #define S3C_GPC4_RESERVED1 (4)
  1308. #define S3C_GPC4_I2S_V40_DO0 (5)
  1309. #define S3C_GPC4_RESERVED3 (6)
  1310. #define S3C_GPC4_EXT_INT_G2_4 (7)
  1311. #define S3C_GPC5 S3C_GPIONO(S3C_GPIO_BANKC, 5)
  1312. #define S3C_GPC5_INP (0)
  1313. #define S3C_GPC5_OUTP (1)
  1314. #define S3C_GPC5_SPI_CLK1 (2)
  1315. #define S3C_GPC5_MMC_CLK2 (3)
  1316. #define S3C_GPC5_RESERVED2 (4)
  1317. #define S3C_GPC5_I2S_V40_DO1 (5)
  1318. #define S3C_GPC5_RESERVED4 (6)
  1319. #define S3C_GPC5_EXT_INT_G2_5 (7)
  1320. #define S3C_GPC6 S3C_GPIONO(S3C_GPIO_BANKC, 6)
  1321. #define S3C_GPC6_INP (0)
  1322. #define S3C_GPC6_OUTP (1)
  1323. #define S3C_GPC6_SPI_MOSI1 (2)
  1324. #define S3C_GPC6_RESERVED1 (3)
  1325. #define S3C_GPC6_RESERVED2 (4)
  1326. #define S3C_GPC6_RESERVED3 (5)
  1327. #define S3C_GPC6_RESERVED4 (6)
  1328. #define S3C_GPC6_EXT_INT_G2_6 (7)
  1329. #define S3C_GPC7 S3C_GPIONO(S3C_GPIO_BANKC, 7)
  1330. #define S3C_GPC7_INP (0)
  1331. #define S3C_GPC7_OUTP (1)
  1332. #define S3C_GPC7_SPI_CS1 (2)
  1333. #define S3C_GPC7_RESERVED1 (3)
  1334. #define S3C_GPC7_RESERVED2 (4)
  1335. #define S3C_GPC7_I2S_V40_DO2 (5)
  1336. #define S3C_GPC7_RESERVED4 (6)
  1337. #define S3C_GPC7_EXT_INT_G2_7 (7)
  1338. /* GPD : 5 in/out port . PCM, I2S, AC97 */
  1339. #define S3C_GPDDAT S3C_GPIOREG(0x64)
  1340. #define S3C_GPDCON S3C_GPIOREG(0x60)
  1341. #define S3C_GPDPU S3C_GPIOREG(0x68)
  1342. #define S3C_GPDSLPCON S3C_GPIOREG(0x6C)
  1343. #define S3C_GPD0 S3C_GPIONO(S3C_GPIO_BANKD, 0)
  1344. #define S3C_GPD0_INP (0)
  1345. #define S3C_GPD0_OUTP (1)
  1346. #define S3C_GPD0_PCM_DCLK0 (2)
  1347. #define S3C_GPD0_I2S_CLK0 (3)
  1348. #define S3C_GPD0_AC97_BITCLK (4)
  1349. #define S3C_GPD0_ADDR_CF0 (5)
  1350. #define S3C_GBP0_RESERVED1 (6)
  1351. #define S3C_GPD0_EXT_INT_G3_0 (7)
  1352. #define S3C_GPD1 S3C_GPIONO(S3C_GPIO_BANKD, 1)
  1353. #define S3C_GPD1_INP (0)
  1354. #define S3C_GPD1_OUTP (1)
  1355. #define S3C_GPD1_PCM_EXTCLK0 (2)
  1356. #define S3C_GPD1_I2S_CDCLK0 (3)
  1357. #define S3C_GPD1_AC97_RESET (4)
  1358. #define S3C_GPD1_ADDR_CF1 (5)
  1359. #define S3C_GPD1_RESERVED1 (6)
  1360. #define S3C_GPD1_EXT_INT_G3_1 (7)
  1361. #define S3C_GPD2 S3C_GPIONO(S3C_GPIO_BANKD, 2)
  1362. #define S3C_GPD2_INP (0)
  1363. #define S3C_GPD2_OUTP (1)
  1364. #define S3C_GPD2_PCM_FSYNC0 (2)
  1365. #define S3C_GPD2_I2S_LRCLK0 (3)
  1366. #define S3C_GPD2_AC97_SYNC (4)
  1367. #define S3C_GPD2_ADDR_CF2 (5)
  1368. #define S3C_GPD2_RESERVED1 (6)
  1369. #define S3C_GPD2_EXT_INT_G3_2 (7)
  1370. #define S3C_GPD3 S3C_GPIONO(S3C_GPIO_BANKD, 3)
  1371. #define S3C_GPD3_INP (0)
  1372. #define S3C_GPD3_OUTP (1)
  1373. #define S3C_GPD3_PCM_SIN0 (2)
  1374. #define S3C_GPD3_I2S_DI0 (3)
  1375. #define S3C_GPD3_AC97_SDI (4)
  1376. #define S3C_GPD3_RESERVED1 (5)
  1377. #define S3C_GPD3_RESERVED2 (6)
  1378. #define S3C_GPD3_EXT_INT_G3_3 (7)
  1379. #define S3C_GPD4 S3C_GPIONO(S3C_GPIO_BANKD, 4)
  1380. #define S3C_GPD4_INP (0)
  1381. #define S3C_GPD4_OUTP (1)
  1382. #define S3C_GPD4_PCM_SOUT0 (2)
  1383. #define S3C_GPD4_I2S_DO0 (3)
  1384. #define S3C_GPD4_AC97_SDO (4)
  1385. #define S3C_GPD4_RESERVED1 (5)
  1386. #define S3C_GPD4_RESERVED2 (6)
  1387. #define S3C_GPD4_EXT_INT_G3_4 (7)
  1388. /* GPE : 5 in/out port . PCM, I2S, AC97 */
  1389. #define S3C_GPEDAT S3C_GPIOREG(0x84)
  1390. #define S3C_GPECON S3C_GPIOREG(0x80)
  1391. #define S3C_GPEPU S3C_GPIOREG(0x88)
  1392. #define S3C_GPESLPCON S3C_GPIOREG(0x8C)
  1393. #define S3C_GPE0 S3C_GPIONO(S3C_GPIO_BANKE, 0)
  1394. #define S3C_GPE0_INP (0)
  1395. #define S3C_GPE0_OUTP (1)
  1396. #define S3C_GPE0_PCM_DCLK1 (2)
  1397. #define S3C_GPE0_I2S_CLK1 (3)
  1398. #define S3C_GPE0_AC97_BITCLK (4)
  1399. #define S3C_GPE0_RESERVED1 (5)
  1400. #define S3C_GPE0_RESERVED2 (6)
  1401. #define S3C_GPE0_EXT_INT_G3_5 (7)
  1402. #define S3C_GPE1 S3C_GPIONO(S3C_GPIO_BANKE, 1)
  1403. #define S3C_GPE1_INP (0)
  1404. #define S3C_GPE1_OUTP (1)
  1405. #define S3C_GPE1_PCM_EXTCLK1 (2)
  1406. #define S3C_GPE1_I2S_CDCLK1 (3)
  1407. #define S3C_GPE1_AC97_RESET (4)
  1408. #define S3C_GPE1_RESERVED1 (5)
  1409. #define S3C_GPE1_RESERVED2 (6)
  1410. #define S3C_GPE1_EXT_INT_G3_6 (7)
  1411. #define S3C_GPE2 S3C_GPIONO(S3C_GPIO_BANKE, 2)
  1412. #define S3C_GPE2_INP (0)
  1413. #define S3C_GPE2_OUTP (1)
  1414. #define S3C_GPE2_PCM_FSYNC1 (2)
  1415. #define S3C_GPE2_I2S_LRCLK1 (3)
  1416. #define S3C_GPE2_AC97_SYNC (4)
  1417. #define S3C_GPE2_RESERVED1 (5)
  1418. #define S3C_GPE2_RESERVED2 (6)
  1419. #define S3C_GPE2_EXT_INT_G3_7 (7)
  1420. #define S3C_GPE3 S3C_GPIONO(S3C_GPIO_BANKE, 3)
  1421. #define S3C_GPE3_INP (0)
  1422. #define S3C_GPE3_OUTP (1)
  1423. #define S3C_GPE3_PCM_SIN1 (2)
  1424. #define S3C_GPE3_I2S_DI1 (3)
  1425. #define S3C_GPE3_AC97_SDI (4)
  1426. #define S3C_GPE3_RESERVED1 (5)
  1427. #define S3C_GPE3_RESERVED2 (6)
  1428. #define S3C_GPE3_EXT_INT_G3_8 (7)
  1429. #define S3C_GPE4 S3C_GPIONO(S3C_GPIO_BANKE, 4)
  1430. #define S3C_GPE4_INP (0)
  1431. #define S3C_GPE4_OUTP (1)
  1432. #define S3C_GPE4_PCM_SOUT1 (2)
  1433. #define S3C_GPE4_I2S_DO1 (3)
  1434. #define S3C_GPE4_AC97_SDO (4)
  1435. #define S3C_GPE4_RESERVED1 (5)
  1436. #define S3C_GPE4_RESERVED2 (6)
  1437. #define S3C_GPE4_EXT_INT_G3_9 (7)
  1438. #define S3C_GPE11 S3C_GPIONO(S3C_GPIO_BANKE, 11)
  1439. #define S3C_GPE11_INP (0)
  1440. #define S3C_GPE11_OUTP (1)
  1441. #define S3C_GPE11_SPI_MISO0 (2)
  1442. #define S3C_GPE11_I2S_DO1 (3)
  1443. #define S3C_GPE11_AC97_SDO (4)
  1444. #define S3C_GPE11_RESERVED1 (5)
  1445. #define S3C_GPE11_RESERVED2 (6)
  1446. #define S3C_GPE11_EXT_INT_G3_9 (7)
  1447. #define S3C_GPE12 S3C_GPIONO(S3C_GPIO_BANKE, 12)
  1448. #define S3C_GPE12_INP (0)
  1449. #define S3C_GPE12_OUTP (1)
  1450. #define S3C_GPE12_SPI_MOSI0 (2)
  1451. #define S3C_GPE12_I2S_DO1 (3)
  1452. #define S3C_GPE12_AC97_SDO (4)
  1453. #define S3C_GPE12_RESERVED1 (5)
  1454. #define S3C_GPE12_RESERVED2 (6)
  1455. #define S3C_GPE12_EXT_INT_G3_9 (7)
  1456. #define S3C_GPE13 S3C_GPIONO(S3C_GPIO_BANKE, 13)
  1457. #define S3C_GPE13_INP (0)
  1458. #define S3C_GPE13_OUTP (1)
  1459. #define S3C_GPE13_SPI_CLK0 (2)
  1460. #define S3C_GPE13_I2S_DO1 (3)
  1461. #define S3C_GPE13_AC97_SDO (4)
  1462. #define S3C_GPE13_RESERVED1 (5)
  1463. #define S3C_GPE13_RESERVED2 (6)
  1464. #define S3C_GPE13_EXT_INT_G3_9 (7)
  1465. /* GPF : 16 in/out port . Camera I/F, PWM, Clock Out */
  1466. #define S3C_GPFDAT S3C_GPIOREG(0xA4)
  1467. #define S3C_GPFCON S3C_GPIOREG(0xA0)
  1468. #define S3C_GPFPU S3C_GPIOREG(0xA8)
  1469. #define S3C_GPFSLPCON S3C_GPIOREG(0xAC)
  1470. #define S3C_GPF0 S3C_GPIONO(S3C_GPIO_BANKF, 0)
  1471. #define S3C_GPF0_INP (0)
  1472. #define S3C_GPF0_OUTP (1)
  1473. #define S3C_GPF0_CAMIF_CLK (2)
  1474. #define S3C_GPF0_EXT_INT_G4_0 (3)
  1475. #define S3C_GPF1 S3C_GPIONO(S3C_GPIO_BANKF, 1)
  1476. #define S3C_GPF1_INP (0)
  1477. #define S3C_GPF1_OUTP (1)
  1478. #define S3C_GPF1_CAMIF_HREF (2)
  1479. #define S3C_GPF1_EXT_INT_G4_1 (3)
  1480. #define S3C_GPF2 S3C_GPIONO(S3C_GPIO_BANKF, 2)
  1481. #define S3C_GPF2_INP (0)
  1482. #define S3C_GPF2_OUTP (1)
  1483. #define S3C_GPF2_CAMIF_CLK (2)
  1484. #define S3C_GPF2_EXT_INT_G4_2 (3)
  1485. #define S3C_GPF3 S3C_GPIONO(S3C_GPIO_BANKF, 3)
  1486. #define S3C_GPF3_INP (0)
  1487. #define S3C_GPF3_OUTP (1)
  1488. #define S3C_GPF3_CAMIF_RST (2)
  1489. #define S3C_GPF3_EXT_INT_G4_3 (3)
  1490. #define S3C_GPF4 S3C_GPIONO(S3C_GPIO_BANKF, 4)
  1491. #define S3C_GPF4_INP (0)
  1492. #define S3C_GPF4_OUTP (1)
  1493. #define S3C_GPF4_CAMIF_VSYNC (2)
  1494. #define S3C_GPF4_EXT_INT_G4_4 (3)
  1495. #define S3C_GPF5 S3C_GPIONO(S3C_GPIO_BANKF, 5)
  1496. #define S3C_GPF5_INP (0)
  1497. #define S3C_GPF5_OUTP (1)
  1498. #define S3C_GPF5_CAMIF_YDATA0 (2)
  1499. #define S3C_GPF5_EXT_INT_G4_5 (3)
  1500. #define S3C_GPF6 S3C_GPIONO(S3C_GPIO_BANKF, 6)
  1501. #define S3C_GPF6_INP (0)
  1502. #define S3C_GPF6_OUTP (1)
  1503. #define S3C_GPF6_CAMIF_YDATA1 (2)
  1504. #define S3C_GPF6_EXT_INT_G4_6 (3)
  1505. #define S3C_GPF7 S3C_GPIONO(S3C_GPIO_BANKF, 7)
  1506. #define S3C_GPF7_INP (0)
  1507. #define S3C_GPF7_OUTP (1)
  1508. #define S3C_GPF7_CAMIF_YDATA2 (2)
  1509. #define S3C_GPF7_EXT_INT_G4_7 (3)
  1510. #define S3C_GPF8 S3C_GPIONO(S3C_GPIO_BANKF, 8)
  1511. #define S3C_GPF8_INP (0)
  1512. #define S3C_GPF8_OUTP (1)
  1513. #define S3C_GPF8_CAMIF_YDATA03 (2)
  1514. #define S3C_GPF8_EXT_INT_G4_8 (3)
  1515. #define S3C_GPF9 S3C_GPIONO(S3C_GPIO_BANKF, 9)
  1516. #define S3C_GPF9_INP (0)
  1517. #define S3C_GPF9_OUTP (1)
  1518. #define S3C_GPF9_CAMIF_YDATA4 (2)
  1519. #define S3C_GPF9_EXT_INT_G4_9 (3)
  1520. #define S3C_GPF10 S3C_GPIONO(S3C_GPIO_BANKF, 10)
  1521. #define S3C_GPF10_INP (0)
  1522. #define S3C_GPF10_OUTP (1)
  1523. #define S3C_GPF10_CAMIF_YDATA5 (2)
  1524. #define S3C_GPF10_EXT_INT_G4_10 (3)
  1525. #define S3C_GPF11 S3C_GPIONO(S3C_GPIO_BANKF, 11)
  1526. #define S3C_GPF11_INP (0)
  1527. #define S3C_GPF11_OUTP (1)
  1528. #define S3C_GPF11_CAMIF_YDATA06 (2)
  1529. #define S3C_GPF11_EXT_INT_G4_11 (3)
  1530. #define S3C_GPF12 S3C_GPIONO(S3C_GPIO_BANKF, 12)
  1531. #define S3C_GPF12_INP (0)
  1532. #define S3C_GPF12_OUTP (1)
  1533. #define S3C_GPF12_CAMIF_YDATA7 (2)
  1534. #define S3C_GPF12_EXT_INT_G4_12 (3)
  1535. #define S3C_GPF13 S3C_GPIONO(S3C_GPIO_BANKF, 13)
  1536. #define S3C_GPF13_INP (0)
  1537. #define S3C_GPF13_OUTP (1)
  1538. #define S3C_GPF13_PWM_ECLK (2)
  1539. #define S3C_GPF13_EXT_INT_G4_13 (3)
  1540. #define S3C_GPF14 S3C_GPIONO(S3C_GPIO_BANKF, 14)
  1541. #define S3C_GPF14_INP (0)
  1542. #define S3C_GPF14_OUTP (1)
  1543. #define S3C_GPF14_PWM_TOUT0 (2)
  1544. #define S3C_GPF14_CLKOUT0 (3)
  1545. #define S3C_GPF15 S3C_GPIONO(S3C_GPIO_BANKF, 15)
  1546. #define S3C_GPF15_INP (0)
  1547. #define S3C_GPF15_OUTP (1)
  1548. #define S3C_GPF15_PWM_TOUT1 (2)
  1549. #define S3C_GPF15_RESERVED (3)
  1550. /* GPG : 7 in/out port . MMC channel 0 */
  1551. #define S3C_GPGDAT S3C_GPIOREG(0xC4)
  1552. #define S3C_GPGCON S3C_GPIOREG(0xC0)
  1553. #define S3C_GPGPU S3C_GPIOREG(0xC8)
  1554. #define S3C_GPGSLPCON S3C_GPIOREG(0xCC)
  1555. #define S3C_GPG0 S3C_GPIONO(S3C_GPIO_BANKG, 0)
  1556. #define S3C_GPG0_INP (0)
  1557. #define S3C_GPG0_OUTP (1)
  1558. #define S3C_GPG0_MMC_CLK0 (2)
  1559. #define S3C_GPG0_RESERVED1 (3)
  1560. #define S3C_GPG0_RESERVED2 (4)
  1561. #define S3C_GPG0_ADDR_CF0 (5)
  1562. #define S3C_GPG0_RESERVED3 (6)
  1563. #define S3C_GPG0_EXT_INT_G5_1 (7)
  1564. #define S3C_GPG1 S3C_GPIONO(S3C_GPIO_BANKG, 1)
  1565. #define S3C_GPG1_INP (0)
  1566. #define S3C_GPG1_OUTP (1)
  1567. #define S3C_GPG1_MMC_CMD0 (2)
  1568. #define S3C_GPG1_EXT_DMA_ACK (3)
  1569. #define S3C_GPG1_RESERVED1 (4)
  1570. #define S3C_GPG1_ADDR_CF1 (5)
  1571. #define S3C_GPG1_RESERVED2 (6)
  1572. #define S3C_GPG1_EXT_INT_G5_2 (7)
  1573. #define S3C_GPG2 S3C_GPIONO(S3C_GPIO_BANKG, 2)
  1574. #define S3C_GPG2_INP (0)
  1575. #define S3C_GPG2_OUTP (1)
  1576. #define S3C_GPG2_MMC_DATA0_0 (2)
  1577. #define S3C_GPG2_RESERVED1 (3)
  1578. #define S3C_GPG2_RESERVED2 (4)
  1579. #define S3C_GPG2_RESERVED3 (5)
  1580. #define S3C_GPG2_RESERVED4 (6)
  1581. #define S3C_GPG2_EXT_INT_G5_3 (7)
  1582. #define S3C_GPG3 S3C_GPIONO(S3C_GPIO_BANKG, 3)
  1583. #define S3C_GPG3_INP (0)
  1584. #define S3C_GPG3_OUTP (1)
  1585. #define S3C_GPG3_MMC_DATA0_1 (2)
  1586. #define S3C_GPG3_RESERVED1 (3)
  1587. #define S3C_GPG3_RESERVED2 (4)
  1588. #define S3C_GPG3_RESERVED3 (5)
  1589. #define S3C_GPG3_RESERVED4 (6)
  1590. #define S3C_GPG3_EXT_INT_G5_4 (7)
  1591. #define S3C_GPG4 S3C_GPIONO(S3C_GPIO_BANKG, 4)
  1592. #define S3C_GPG4_INP (0)
  1593. #define S3C_GPG4_OUTP (1)
  1594. #define S3C_GPG4_MMC_DATA0_2 (2)
  1595. #define S3C_GPG4_RESERVED1 (3)
  1596. #define S3C_GPG4_RESERVED2 (4)
  1597. #define S3C_GPG4_RESERVED3 (5)
  1598. #define S3C_GPG4_RESERVED4 (6)
  1599. #define S3C_GPG4_EXT_INT_G5_5 (7)
  1600. #define S3C_GPG5 S3C_GPIONO(S3C_GPIO_BANKG, 5)
  1601. #define S3C_GPG5_INP (0)
  1602. #define S3C_GPG5_OUTP (1)
  1603. #define S3C_GPG5_MMC_DATA0_3 (2)
  1604. #define S3C_GPG5_RESERVED1 (3)
  1605. #define S3C_GPG5_RESERVED2 (4)
  1606. #define S3C_GPG5_RESERVED3 (5)
  1607. #define S3C_GPG5_RESERVED4 (6)
  1608. #define S3C_GPG5_EXT_INT_G5_6 (7)
  1609. #define S3C_GPG6 S3C_GPIONO(S3C_GPIO_BANKG, 6)
  1610. #define S3C_GPG6_INP (0)
  1611. #define S3C_GPG6_OUTP (1)
  1612. #define S3C_GPG6_MMC_CD0 (2)
  1613. #define S3C_GPG6_MMC_CD1 (3)
  1614. #define S3C_GPG6_RESERVED2 (4)
  1615. #define S3C_GPG6_RESERVED3 (5)
  1616. #define S3C_GPG6_RESERVED4 (6)
  1617. #define S3C_GPG6_EXT_INT_G5_7 (7)
  1618. /*GPH : 10 in/out port . MMC channel 1 */
  1619. /* Notice!!! Watch out GPIO data register address*/
  1620. #define S3C_GPHDAT S3C_GPIOREG(0xE8)
  1621. #define S3C_GPH0CON S3C_GPIOREG(0xE0)
  1622. #define S3C_GPH1CON S3C_GPIOREG(0xE4)
  1623. #define S3C_GPHPU S3C_GPIOREG(0xEC)
  1624. #define S3C_GPHSLPCON S3C_GPIOREG(0xF0)
  1625. #define S3C_GPH0 S3C_GPIONO(S3C_GPIO_BANKH, 0)
  1626. #define S3C_GPH0_INP (0)
  1627. #define S3C_GPH0_OUTP (1)
  1628. #define S3C_GPH0_MMC_CLK1 (2)
  1629. #define S3C_GPH0_RESERVED1 (3)
  1630. #define S3C_GPH0_KEYPAD_COL0 (4)
  1631. #define S3C_GPH0_ADDR_CF0 (5)
  1632. #define S3C_GPH0_RESERVED2 (6)
  1633. #define S3C_GPH0_EXT_INT_G6_0 (7)
  1634. #define S3C_GPH1 S3C_GPIONO(S3C_GPIO_BANKH, 1)
  1635. #define S3C_GPH1_INP (0)
  1636. #define S3C_GPH1_OUTP (1)
  1637. #define S3C_GPH1_MMC_CMD1 (2)
  1638. #define S3C_GPH1_RESERVED1 (3)
  1639. #define S3C_GPH1_KEYPAD_COL1 (4)
  1640. #define S3C_GPH1_ADDR_CF1 (5)
  1641. #define S3C_GPH1_RESERVED2 (6)
  1642. #define S3C_GPH1_EXT_INT_G6_1 (7)
  1643. #define S3C_GPH2 S3C_GPIONO(S3C_GPIO_BANKH, 2)
  1644. #define S3C_GPH2_INP (0)
  1645. #define S3C_GPH2_OUTP (1)
  1646. #define S3C_GPH2_MMC_DATA1_0 (2)
  1647. #define S3C_GPH2_RESERVED1 (3)
  1648. #define S3C_GPH2_KEYPAD_COL2 (4)
  1649. #define S3C_GPH2_RESERVED3 (5)
  1650. #define S3C_GPH2_RESERVED4 (6)
  1651. #define S3C_GPH2_EXT_INT_G6_2 (7)
  1652. #define S3C_GPH3 S3C_GPIONO(S3C_GPIO_BANKH, 3)
  1653. #define S3C_GPH3_INP (0)
  1654. #define S3C_GPH3_OUTP (1)
  1655. #define S3C_GPH3_MMC_DATA1_1 (2)
  1656. #define S3C_GPH3_RESERVED1 (3)
  1657. #define S3C_GPH3_KEYPAD_COL3 (4)
  1658. #define S3C_GPH3_RESERVED3 (5)
  1659. #define S3C_GPH3_RESERVED4 (6)
  1660. #define S3C_GPH3_EXT_INT_G6_3 (7)
  1661. #define S3C_GPH4 S3C_GPIONO(S3C_GPIO_BANKH, 4)
  1662. #define S3C_GPH4_INP (0)
  1663. #define S3C_GPH4_OUTP (1)
  1664. #define S3C_GPH4_MMC_DATA1_2 (2)
  1665. #define S3C_GPH4_RESERVED1 (3)
  1666. #define S3C_GPH4_KEYPAD_COL4 (4)
  1667. #define S3C_GPH4_RESERVED3 (5)
  1668. #define S3C_GPH4_RESERVED4 (6)
  1669. #define S3C_GPH4_EXT_INT_G6_4 (7)
  1670. #define S3C_GPH5 S3C_GPIONO(S3C_GPIO_BANKH, 5)
  1671. #define S3C_GPH5_INP (0)
  1672. #define S3C_GPH5_OUTP (1)
  1673. #define S3C_GPH5_MMC_DATA1_3 (2)
  1674. #define S3C_GPH5_RESERVED1 (3)
  1675. #define S3C_GPH5_KEYPAD_COL5 (4)
  1676. #define S3C_GPH5_RESERVED3 (5)
  1677. #define S3C_GPH5_RESERVED4 (6)
  1678. #define S3C_GPH5_EXT_INT_G6_5 (7)
  1679. #define S3C_GPH6 S3C_GPIONO(S3C_GPIO_BANKH, 6)
  1680. #define S3C_GPH6_INP (0)
  1681. #define S3C_GPH6_OUTP (1)
  1682. #define S3C_GPH6_MMC_DATA1_4 (2)
  1683. #define S3C_GPH6_MMC_DATA2_0 (3)
  1684. #define S3C_GPH6_KEYPAD_COL6 (4)
  1685. #define S3C_GPH6_I2S_V40_BCLK (5)
  1686. #define S3C_GPH6_ADDR_CF0 (6)
  1687. #define S3C_GPH6_EXT_INT_G6_6 (7)
  1688. #define S3C_GPH7 S3C_GPIONO(S3C_GPIO_BANKH, 7)
  1689. #define S3C_GPH7_INP (0)
  1690. #define S3C_GPH7_OUTP (1)
  1691. #define S3C_GPH7_MMC_DATA1_5 (2)
  1692. #define S3C_GPH7_MMC_DATA2_1 (3)
  1693. #define S3C_GPH7_KEYPAD_COL7 (4)
  1694. #define S3C_GPH7_I2S_V40_CDCLK (5)
  1695. #define S3C_GPH7_ADDR_CF1 (6)
  1696. #define S3C_GPH7_EXT_INT_G6_7 (7)
  1697. #define S3C_GPH8 S3C_GPIONO(S3C_GPIO_BANKH, 8)
  1698. #define S3C_GPH8_INP (0)
  1699. #define S3C_GPH8_OUTP (1)
  1700. #define S3C_GPH8_MMC_DATA1_6 (2)
  1701. #define S3C_GPH8_MMC_DATA2_2 (3)
  1702. #define S3C_GPH8_RESERVED2 (4)
  1703. #define S3C_GPH8_I2S_V40_LRCLK (5)
  1704. #define S3C_GPH8_ADDR_CF2 (6)
  1705. #define S3C_GPH8_EXT_INT_G6_8 (7)
  1706. #define S3C_GPH9 S3C_GPIONO(S3C_GPIO_BANKH, 9)
  1707. #define S3C_GPH9_INP (0)
  1708. #define S3C_GPH9_OUTP (1)
  1709. #define S3C_GPH9_MMC_DATA1_7 (2)
  1710. #define S3C_GPH9_MMC_DATA2_3 (3)
  1711. #define S3C_GPH9_RESERVED2 (4)
  1712. #define S3C_GPH9_I2S_V40_DI (5)
  1713. #define S3C_GPH9_RESERVED4 (6)
  1714. #define S3C_GPH9_EXT_INT_G6_9 (7)
  1715. /* GPI : 16 in/out port . LCD Video Out[15:0] */
  1716. #define S3C_GPIDAT S3C_GPIOREG(0x104)
  1717. #define S3C_GPICON S3C_GPIOREG(0x100)
  1718. #define S3C_GPIPU S3C_GPIOREG(0x108)
  1719. #define S3C_GPISLPCON S3C_GPIOREG(0x10C)
  1720. #define S3C_GPI0 S3C_GPIONO(S3C_GPIO_BANKI, 0)
  1721. #define S3C_GPI0_INP (0)
  1722. #define S3C_GPI0_OUTP (1)
  1723. #define S3C_GPI0_LCD_VD0 (2)
  1724. #define S3C_GPI0_RESERVED (3)
  1725. #define S3C_GPI1 S3C_GPIONO(S3C_GPIO_BANKI, 1)
  1726. #define S3C_GPI1_INP (0)
  1727. #define S3C_GPI1_OUTP (1)
  1728. #define S3C_GPI1_LCD_VD1 (2)
  1729. #define S3C_GPI1_RESERVED (3)
  1730. #define S3C_GPI2 S3C_GPIONO(S3C_GPIO_BANKI, 2)
  1731. #define S3C_GPI2_INP (0)
  1732. #define S3C_GPI2_OUTP (1)
  1733. #define S3C_GPI2_LCD_VD2 (2)
  1734. #define S3C_GPI2_RESERVED (3)
  1735. #define S3C_GPI3 S3C_GPIONO(S3C_GPIO_BANKI, 3)
  1736. #define S3C_GPI3_INP (0)
  1737. #define S3C_GPI3_OUTP (1)
  1738. #define S3C_GPI3_LCD_VD3 (2)
  1739. #define S3C_GPI3_RESERVED (3)
  1740. #define S3C_GPI4 S3C_GPIONO(S3C_GPIO_BANKI, 4)
  1741. #define S3C_GPI4_INP (0)
  1742. #define S3C_GPI4_OUTP (1)
  1743. #define S3C_GPI4_LCD_VD4 (2)
  1744. #define S3C_GPI4_RESERVED (3)
  1745. #define S3C_GPI5 S3C_GPIONO(S3C_GPIO_BANKI, 5)
  1746. #define S3C_GPI5_INP (0)
  1747. #define S3C_GPI5_OUTP (1)
  1748. #define S3C_GPI5_LCD_VD5 (2)
  1749. #define S3C_GPI5_RESERVED (3)
  1750. #define S3C_GPI6 S3C_GPIONO(S3C_GPIO_BANKI, 6)
  1751. #define S3C_GPI6_INP (0)
  1752. #define S3C_GPI6_OUTP (1)
  1753. #define S3C_GPI6_LCD_VD6 (2)
  1754. #define S3C_GPI6_RESERVED (3)
  1755. #define S3C_GPI7 S3C_GPIONO(S3C_GPIO_BANKI, 7)
  1756. #define S3C_GPI7_INP (0)
  1757. #define S3C_GPI7_OUTP (1)
  1758. #define S3C_GPI7_LCD_VD7 (2)
  1759. #define S3C_GPI7_RESERVED (3)
  1760. #define S3C_GPI8 S3C_GPIONO(S3C_GPIO_BANKI, 8)
  1761. #define S3C_GPI8_INP (0)
  1762. #define S3C_GPI8_OUTP (1)
  1763. #define S3C_GPI8_LCD_VD8 (2)
  1764. #define S3C_GPI8_RESERVED (3)
  1765. #define S3C_GPI9 S3C_GPIONO(S3C_GPIO_BANKI, 9)
  1766. #define S3C_GPI9_INP (0)
  1767. #define S3C_GPI9_OUTP (1)
  1768. #define S3C_GPI9_LCD_VD9 (2)
  1769. #define S3C_GPI9_RESERVED (3)
  1770. #define S3C_GPI10 S3C_GPIONO(S3C_GPIO_BANKI, 10)
  1771. #define S3C_GPI10_INP (0)
  1772. #define S3C_GPI10_OUTP (1)
  1773. #define S3C_GPI10_LCD_VD10 (2)
  1774. #define S3C_GPI10_RESERVED (3)
  1775. #define S3C_GPI11 S3C_GPIONO(S3C_GPIO_BANKI, 11)
  1776. #define S3C_GPI11_INP (0)
  1777. #define S3C_GPI11_OUTP (1)
  1778. #define S3C_GPI11_LCD_VD11 (2)
  1779. #define S3C_GPI11_RESERVED (3)
  1780. #define S3C_GPI12 S3C_GPIONO(S3C_GPIO_BANKI, 12)
  1781. #define S3C_GPI12_INP (0)
  1782. #define S3C_GPI12_OUTP (1)
  1783. #define S3C_GPI12_LCD_VD12 (2)
  1784. #define S3C_GPI12_RESERVED (3)
  1785. #define S3C_GPI13 S3C_GPIONO(S3C_GPIO_BANKI, 13)
  1786. #define S3C_GPI13_INP (0)
  1787. #define S3C_GPI13_OUTP (1)
  1788. #define S3C_GPI13_LCD_VD13 (2)
  1789. #define S3C_GPI13_RESERVED (3)
  1790. #define S3C_GPI14 S3C_GPIONO(S3C_GPIO_BANKI, 14)
  1791. #define S3C_GPI14_INP (0)
  1792. #define S3C_GPI14_OUTP (1)
  1793. #define S3C_GPI14_LCD_VD14 (2)
  1794. #define S3C_GPI14_RESERVED (3)
  1795. #define S3C_GPI15 S3C_GPIONO(S3C_GPIO_BANKI, 15)
  1796. #define S3C_GPI15_INP (0)
  1797. #define S3C_GPI15_OUTP (1)
  1798. #define S3C_GPI15_LCD_VD15 (2)
  1799. #define S3C_GPI15_RESERVED (3)
  1800. /* GPJ : 12 in/out port . LCD Video Out[23:16], Control signals */
  1801. #define S3C_GPJDAT S3C_GPIOREG(0x124)
  1802. #define S3C_GPJCON S3C_GPIOREG(0x120)
  1803. #define S3C_GPJPU S3C_GPIOREG(0x128)
  1804. #define S3C_GPJSLPCON S3C_GPIOREG(0x12C)
  1805. #define S3C_GPJ0 S3C_GPIONO(S3C_GPIO_BANKJ, 0)
  1806. #define S3C_GPJ0_INP (0)
  1807. #define S3C_GPJ0_OUTP (1)
  1808. #define S3C_GPJ0_LCD_VD16 (2)
  1809. #define S3C_GPJ0_RESERVED (3)
  1810. #define S3C_GPJ1 S3C_GPIONO(S3C_GPIO_BANKJ, 1)
  1811. #define S3C_GPJ1_INP (0)
  1812. #define S3C_GPJ1_OUTP (1)
  1813. #define S3C_GPJ1_LCD_VD17 (2)
  1814. #define S3C_GPJ1_RESERVED (3)
  1815. #define S3C_GPJ2 S3C_GPIONO(S3C_GPIO_BANKJ, 2)
  1816. #define S3C_GPJ2_INP (0)
  1817. #define S3C_GPJ2_OUTP (1)
  1818. #define S3C_GPJ2_LCD_VD18 (2)
  1819. #define S3C_GPJ2_RESERVED (3)
  1820. #define S3C_GPJ3 S3C_GPIONO(S3C_GPIO_BANKJ, 3)
  1821. #define S3C_GPJ3_INP (0)
  1822. #define S3C_GPJ3_OUTP (1)
  1823. #define S3C_GPJ3_LCD_VD19 (2)
  1824. #define S3C_GPJ3_RESERVED (3)
  1825. #define S3C_GPJ4 S3C_GPIONO(S3C_GPIO_BANKJ, 4)
  1826. #define S3C_GPJ4_INP (0)
  1827. #define S3C_GPJ4_OUTP (1)
  1828. #define S3C_GPJ4_LCD_VD20 (2)
  1829. #define S3C_GPJ4_RESERVED (3)
  1830. #define S3C_GPJ5 S3C_GPIONO(S3C_GPIO_BANKJ, 5)
  1831. #define S3C_GPJ5_INP (0)
  1832. #define S3C_GPJ5_OUTP (1)
  1833. #define S3C_GPJ5_LCD_VD21 (2)
  1834. #define S3C_GPJ5_RESERVED (3)
  1835. #define S3C_GPJ6 S3C_GPIONO(S3C_GPIO_BANKJ, 6)
  1836. #define S3C_GPJ6_INP (0)
  1837. #define S3C_GPJ6_OUTP (1)
  1838. #define S3C_GPJ6_LCD_VD22 (2)
  1839. #define S3C_GPJ6_RESERVED (3)
  1840. #define S3C_GPJ7 S3C_GPIONO(S3C_GPIO_BANKJ, 7)
  1841. #define S3C_GPJ7_INP (0)
  1842. #define S3C_GPJ7_OUTP (1)
  1843. #define S3C_GPJ7_LCD_VD23 (2)
  1844. #define S3C_GPJ7_RESERVED (3)
  1845. #define S3C_GPJ8 S3C_GPIONO(S3C_GPIO_BANKJ, 8)
  1846. #define S3C_GPJ8_INP (0)
  1847. #define S3C_GPJ8_OUTP (1)
  1848. #define S3C_GPJ8_LCD_HSYNC (2)
  1849. #define S3C_GPJ8_RESERVED (3)
  1850. #define S3C_GPJ9 S3C_GPIONO(S3C_GPIO_BANKJ, 9)
  1851. #define S3C_GPJ9_INP (0)
  1852. #define S3C_GPJ9_OUTP (1)
  1853. #define S3C_GPJ9_LCD_VSYNC (2)
  1854. #define S3C_GPJ9_RESERVED (3)
  1855. #define S3C_GPJ10 S3C_GPIONO(S3C_GPIO_BANKJ, 10)
  1856. #define S3C_GPJ10_INP (0)
  1857. #define S3C_GPJ10_OUTP (1)
  1858. #define S3C_GPJ10_LCD_VDEN (2)
  1859. #define S3C_GPJ10_RESERVED (3)
  1860. #define S3C_GPJ11 S3C_GPIONO(S3C_GPIO_BANKJ, 11)
  1861. #define S3C_GPJ11_INP (0)
  1862. #define S3C_GPJ11_OUTP (1)
  1863. #define S3C_GPJ11_LCD_VCLK (2)
  1864. #define S3C_GPJ11_RESERVED (3)
  1865. /* GPK : 16 in/out port . Host I/F, HSI, Key pad I/F */
  1866. #define S3C_GPKDAT S3C_GPIOREG(0x808)
  1867. #define S3C_GPK0CON S3C_GPIOREG(0x800)
  1868. #define S3C_GPK1CON S3C_GPIOREG(0x804)
  1869. #define S3C_GPKPU S3C_GPIOREG(0x80C)
  1870. #define S3C_GPK0 S3C_GPIONO(S3C_GPIO_BANKK, 0)
  1871. #define S3C_GPK0_INP (0)
  1872. #define S3C_GPK0_OUTP (1)
  1873. #define S3C_GPK0_HOSTIF_DATA0 (2)
  1874. #define S3C_GPK0_HSI_RX_RDY (3)
  1875. #define S3C_GPK0_RESERVED1 (4)
  1876. #define S3C_GPK0_DATA_CF0 (5)
  1877. #define S3C_GPK0_RESERVED2 (6)
  1878. #define S3C_GPK0_RESERVED3 (7)
  1879. #define S3C_GPK1 S3C_GPIONO(S3C_GPIO_BANKK, 1)
  1880. #define S3C_GPK1_INP (0)
  1881. #define S3C_GPK1_OUTP (1)
  1882. #define S3C_GPK1_HOSTIF_DATA1 (2)
  1883. #define S3C_GPK1_HSI_RX_WAKE (3)
  1884. #define S3C_GPK1_RESERVED1 (4)
  1885. #define S3C_GPK1_DATA_CF1 (5)
  1886. #define S3C_GPK1_RESERVED2 (6)
  1887. #define S3C_GPK1_RESERVED3 (7)
  1888. #define S3C_GPK2 S3C_GPIONO(S3C_GPIO_BANKK, 2)
  1889. #define S3C_GPK2_INP (0)
  1890. #define S3C_GPK2_OUTP (1)
  1891. #define S3C_GPK2_HOSTIF_DATA2 (2)
  1892. #define S3C_GPK2_HSI_RX_FLAG (3)
  1893. #define S3C_GPK2_RESERVED1 (4)
  1894. #define S3C_GPK2_DATA_CF2 (5)
  1895. #define S3C_GPK2_RESERVED2 (6)
  1896. #define S3C_GPK2_RESERVED3 (7)
  1897. #define S3C_GPK3 S3C_GPIONO(S3C_GPIO_BANKK, 3)
  1898. #define S3C_GPK3_INP (0)
  1899. #define S3C_GPK3_OUTP (1)
  1900. #define S3C_GPK3_HOSTIF_DATA3 (2)
  1901. #define S3C_GPK3_HSI_RX_DATA (3)
  1902. #define S3C_GPK3_RESERVED1 (4)
  1903. #define S3C_GPK3_DATA_CF3 (5)
  1904. #define S3C_GPK3_RESERVED2 (6)
  1905. #define S3C_GPK3_RESERVED3 (7)
  1906. #define S3C_GPK4 S3C_GPIONO(S3C_GPIO_BANKK, 4)
  1907. #define S3C_GPK4_INP (0)
  1908. #define S3C_GPK4_OUTP (1)
  1909. #define S3C_GPK4_HOSTIF_DATA4 (2)
  1910. #define S3C_GPK4_HSI_TX_RDY (3)
  1911. #define S3C_GPK4_RESERVED1 (4)
  1912. #define S3C_GPK4_DATA_CF4 (5)
  1913. #define S3C_GPK4_RESERVED2 (6)
  1914. #define S3C_GPK4_RESERVED3 (7)
  1915. #define S3C_GPK5 S3C_GPIONO(S3C_GPIO_BANKK, 5)
  1916. #define S3C_GPK5_INP (0)
  1917. #define S3C_GPK5_OUTP (1)
  1918. #define S3C_GPK5_HOSTIF_DATA5 (2)
  1919. #define S3C_GPK5_HSI_TX_WAKE (3)
  1920. #define S3C_GPK5_RESERVED1 (4)
  1921. #define S3C_GPK5_DATA_CF5 (5)
  1922. #define S3C_GPK5_RESERVED2 (6)
  1923. #define S3C_GPK5_RESERVED3 (7)
  1924. #define S3C_GPK6 S3C_GPIONO(S3C_GPIO_BANKK, 6)
  1925. #define S3C_GPK6_INP (0)
  1926. #define S3C_GPK6_OUTP (1)
  1927. #define S3C_GPK6_HOSTIF_DATA6 (2)
  1928. #define S3C_GPK6_HSI_TX_FLAG (3)
  1929. #define S3C_GPK6_RESERVED1 (4)
  1930. #define S3C_GPK6_DATA_CF6 (5)
  1931. #define S3C_GPK6_RESERVED2 (6)
  1932. #define S3C_GPK6_RESERVED3 (7)
  1933. #define S3C_GPK7 S3C_GPIONO(S3C_GPIO_BANKK, 7)
  1934. #define S3C_GPK7_INP (0)
  1935. #define S3C_GPK7_OUTP (1)
  1936. #define S3C_GPK7_HOSTIF_DATA7 (2)
  1937. #define S3C_GPK7_HSI_TX_DATA (3)
  1938. #define S3C_GPK7_RESERVED1 (4)
  1939. #define S3C_GPK7_DATA_CF7 (5)
  1940. #define S3C_GPK7_RESERVED2 (6)
  1941. #define S3C_GPK7_RESERVED3 (7)
  1942. #define S3C_GPK8 S3C_GPIONO(S3C_GPIO_BANKK, 8)
  1943. #define S3C_GPK8_INP (0)
  1944. #define S3C_GPK8_OUTP (1)
  1945. #define S3C_GPK8_HOSTIF_DATA8 (2)
  1946. #define S3C_GPK8_KEYPAD_ROW0 (3)
  1947. #define S3C_GPK8_RESERVED1 (4)
  1948. #define S3C_GPK8_DATA_CF8 (5)
  1949. #define S3C_GPK8_RESERVED2 (6)
  1950. #define S3C_GPK8_RESERVED3 (7)
  1951. #define S3C_GPK9 S3C_GPIONO(S3C_GPIO_BANKK, 9)
  1952. #define S3C_GPK9_INP (0)
  1953. #define S3C_GPK9_OUTP (1)
  1954. #define S3C_GPK9_HOSTIF_DATA9 (2)
  1955. #define S3C_GPK9_KEYPAD_ROW1 (3)
  1956. #define S3C_GPK9_RESERVED1 (4)
  1957. #define S3C_GPK9_DATA_CF9 (5)
  1958. #define S3C_GPK9_RESERVED2 (6)
  1959. #define S3C_GPK9_RESERVED3 (7)
  1960. #define S3C_GPK10 S3C_GPIONO(S3C_GPIO_BANKK, 10)
  1961. #define S3C_GPK10_INP (0)
  1962. #define S3C_GPK10_OUTP (1)
  1963. #define S3C_GPK10_HOSTIF_DATA10 (2)
  1964. #define S3C_GPK10_KEYPAD_ROW2 (3)
  1965. #define S3C_GPK10_RESERVED1 (4)
  1966. #define S3C_GPK10_DATA_CF9 (5)
  1967. #define S3C_GPK10_RESERVED2 (6)
  1968. #define S3C_GPK10_RESERVED3 (7)
  1969. #define S3C_GPK11 S3C_GPIONO(S3C_GPIO_BANKK, 11)
  1970. #define S3C_GPK11_INP (0)
  1971. #define S3C_GPK11_OUTP (1)
  1972. #define S3C_GPK11_HOSTIF_DATA11 (2)
  1973. #define S3C_GPK11_KEYPAD_ROW3 (3)
  1974. #define S3C_GPK11_RESERVED1 (4)
  1975. #define S3C_GPK11_DATA_CF11 (5)
  1976. #define S3C_GPK11_RESERVED2 (6)
  1977. #define S3C_GPK11_RESERVED3 (7)
  1978. #define S3C_GPK12 S3C_GPIONO(S3C_GPIO_BANKK, 12)
  1979. #define S3C_GPK12_INP (0)
  1980. #define S3C_GPK12_OUTP (1)
  1981. #define S3C_GPK12_HOSTIF_DATA12 (2)
  1982. #define S3C_GPK12_KEYPAD_ROW4 (3)
  1983. #define S3C_GPK12_RESERVED1 (4)
  1984. #define S3C_GPK12_DATA_CF12 (5)
  1985. #define S3C_GPK12_RESERVED2 (6)
  1986. #define S3C_GPK12_RESERVED3 (7)
  1987. #define S3C_GPK13 S3C_GPIONO(S3C_GPIO_BANKK, 13)
  1988. #define S3C_GPK13_INP (0)
  1989. #define S3C_GPK13_OUTP (1)
  1990. #define S3C_GPK13_HOSTIF_DATA13 (2)
  1991. #define S3C_GPK13_KEYPAD_ROW5 (3)
  1992. #define S3C_GPK13_RESERVED1 (4)
  1993. #define S3C_GPK13_DATA_CF8 (5)
  1994. #define S3C_GPK13_RESERVED2 (6)
  1995. #define S3C_GPK13_RESERVED3 (7)
  1996. #define S3C_GPK14 S3C_GPIONO(S3C_GPIO_BANKK, 14)
  1997. #define S3C_GPK14_INP (0)
  1998. #define S3C_GPK14_OUTP (1)
  1999. #define S3C_GPK14_HOSTIF_DATA14 (2)
  2000. #define S3C_GPK14_KEYPAD_ROW6 (3)
  2001. #define S3C_GPK14_RESERVED1 (4)
  2002. #define S3C_GPK14_DATA_CF14 (5)
  2003. #define S3C_GPK14_RESERVED2 (6)
  2004. #define S3C_GPK14_RESERVED3 (7)
  2005. #define S3C_GPK15 S3C_GPIONO(S3C_GPIO_BANKK, 15)
  2006. #define S3C_GPK15_INP (0)
  2007. #define S3C_GPK15_OUTP (1)
  2008. #define S3C_GPK15_HOSTIF_DATA15 (2)
  2009. #define S3C_GPK15_KEYPAD_ROW7 (3)
  2010. #define S3C_GPK15_RESERVED1 (4)
  2011. #define S3C_GPK15_DATA_CF15 (5)
  2012. #define S3C_GPK15_RESERVED2 (6)
  2013. #define S3C_GPK15_RESERVED3 (7)
  2014. /* GPL : 16 in/out port . Host I/F, HSI, Key pad I/F */
  2015. #define S3C_GPLDAT S3C_GPIOREG(0x818)
  2016. #define S3C_GPL0CON S3C_GPIOREG(0x810)
  2017. #define S3C_GPL1CON S3C_GPIOREG(0x814)
  2018. #define S3C_GPLPU S3C_GPIOREG(0x81C)
  2019. #define S3C_GPL0 S3C_GPIONO(S3C_GPIO_BANKL, 0)
  2020. #define S3C_GPL0_INP (0)
  2021. #define S3C_GPL0_OUTP (1)
  2022. #define S3C_GPL0_HOSTIF_ADDR0 (2)
  2023. #define S3C_GPL0_KEYPAD_COL0 (3)
  2024. #define S3C_GPL0_RESERVED1 (4)
  2025. #define S3C_GPL0_RESERVED2 (5)
  2026. #define S3C_GPL0_ADDR_CF0 (6)
  2027. #define S3C_GPL0_OTG_ULPI_DATA0 (7)
  2028. #define S3C_GPL1 S3C_GPIONO(S3C_GPIO_BANKL, 1)
  2029. #define S3C_GPL1_INP (0)
  2030. #define S3C_GPL1_OUTP (1)
  2031. #define S3C_GPL1_HOSTIF_ADDR1 (2)
  2032. #define S3C_GPL1_KEYPAD_COL1 (3)
  2033. #define S3C_GPL1_RESERVED1 (4)
  2034. #define S3C_GPL1_RESERVED2 (5)
  2035. #define S3C_GPL1_ADDR_CF1 (6)
  2036. #define S3C_GPL1_OTG_ULPI_DATA1 (7)
  2037. #define S3C_GPL2 S3C_GPIONO(S3C_GPIO_BANKL, 2)
  2038. #define S3C_GPL2_INP (0)
  2039. #define S3C_GPL2_OUTP (1)
  2040. #define S3C_GPL2_HOSTIF_ADDR2 (2)
  2041. #define S3C_GPL2_KEYPAD_COL2 (3)
  2042. #define S3C_GPL2_RESERVED1 (4)
  2043. #define S3C_GPL2_RESERVED2 (5)
  2044. #define S3C_GPL2_ADDR_CF2 (6)
  2045. #define S3C_GPL2_OTG_ULPI_DATA2 (7)
  2046. #define S3C_GPL3 S3C_GPIONO(S3C_GPIO_BANKL, 3)
  2047. #define S3C_GPL3_INP (0)
  2048. #define S3C_GPL3_OUTP (1)
  2049. #define S3C_GPL3_HOSTIF_ADDR3 (2)
  2050. #define S3C_GPL3_KEYPAD_COL3 (3)
  2051. #define S3C_GPL3_RESERVED1 (4)
  2052. #define S3C_GPL3_RESERVED2 (5)
  2053. #define S3C_GPL3_RESERVED3 (6)
  2054. #define S3C_GPL3_OTG_ULPI_DATA3 (7)
  2055. #define S3C_GPL4 S3C_GPIONO(S3C_GPIO_BANKL, 4)
  2056. #define S3C_GPL4_INP (0)
  2057. #define S3C_GPL4_OUTP (1)
  2058. #define S3C_GPL4_HOSTIF_ADDR4 (2)
  2059. #define S3C_GPL4_KEYPAD_COL4 (3)
  2060. #define S3C_GPL4_RESERVED1 (4)
  2061. #define S3C_GPL4_RESERVED2 (5)
  2062. #define S3C_GPL4_RESERVED3 (6)
  2063. #define S3C_GPL4_OTG_ULPI_DATA4 (7)
  2064. #define S3C_GPL5 S3C_GPIONO(S3C_GPIO_BANKL, 5)
  2065. #define S3C_GPL5_INP (0)
  2066. #define S3C_GPL5_OUTP (1)
  2067. #define S3C_GPL5_HOSTIF_ADDR5 (2)
  2068. #define S3C_GPL5_KEYPAD_COL5 (3)
  2069. #define S3C_GPL5_RESERVED1 (4)
  2070. #define S3C_GPL5_RESERVED2 (5)
  2071. #define S3C_GPL5_RESERVED3 (6)
  2072. #define S3C_GPL5_OTG_ULPI_DATA5 (7)
  2073. #define S3C_GPL6 S3C_GPIONO(S3C_GPIO_BANKL, 6)
  2074. #define S3C_GPL6_INP (0)
  2075. #define S3C_GPL6_OUTP (1)
  2076. #define S3C_GPL6_HOSTIF_ADDR6 (2)
  2077. #define S3C_GPL6_KEYPAD_COL6 (3)
  2078. #define S3C_GPL6_RESERVED1 (4)
  2079. #define S3C_GPL6_RESERVED2 (5)
  2080. #define S3C_GPL6_RESERVED3 (6)
  2081. #define S3C_GPL6_OTG_ULPI_DATA6 (7)
  2082. #define S3C_GPL7 S3C_GPIONO(S3C_GPIO_BANKL, 7)
  2083. #define S3C_GPL7_INP (0)
  2084. #define S3C_GPL7_OUTP (1)
  2085. #define S3C_GPL7_HOSTIF_ADDR7 (2)
  2086. #define S3C_GPL7_KEYPAD_COL7 (3)
  2087. #define S3C_GPL7_RESERVED1 (4)
  2088. #define S3C_GPL7_RESERVED2 (5)
  2089. #define S3C_GPL7_RESERVED3 (6)
  2090. #define S3C_GPL7_OTG_ULPI_DATA (7)
  2091. #define S3C_GPL8 S3C_GPIONO(S3C_GPIO_BANKL, 8)
  2092. #define S3C_GPL8_INP (0)
  2093. #define S3C_GPL8_OUTP (1)
  2094. #define S3C_GPL8_HOSTIF_ADDR8 (2)
  2095. #define S3C_GPL8_EXTINT16 (3)
  2096. #define S3C_GPL8_RESERVED1 (4)
  2097. #define S3C_GPL8_CE_CF0 (5)
  2098. #define S3C_GPL8_RESERVED2 (6)
  2099. #define S3C_GPL8_OTG_ULPI_STP (7)
  2100. #define S3C_GPL9 S3C_GPIONO(S3C_GPIO_BANKL, 9)
  2101. #define S3C_GPL9_INP (0)
  2102. #define S3C_GPL9_OUTP (1)
  2103. #define S3C_GPL9_HOSTIF_ADDR9 (2)
  2104. #define S3C_GPL9_EXTINT17 (3)
  2105. #define S3C_GPL9_RESERVED1 (4)
  2106. #define S3C_GPL9_CE_CF1 (5)
  2107. #define S3C_GPL9_RESERVED2 (6)
  2108. #define S3C_GPL9_OTG_ULPI_CLK (7)
  2109. #define S3C_GPL10 S3C_GPIONO(S3C_GPIO_BANKL, 10)
  2110. #define S3C_GPL10_INP (0)
  2111. #define S3C_GPL10_OUTP (1)
  2112. #define S3C_GPL10_SPI_CLK1 (2)
  2113. #define S3C_GPL10_EXTINT18 (3)
  2114. #define S3C_GPL10_RESERVED1 (4)
  2115. #define S3C_GPL10_IORD_CF (5)
  2116. #define S3C_GPL10_RESERVED2 (6)
  2117. #define S3C_GPL10_OTG_ULPI_NXT (7)
  2118. #define S3C_GPL11 S3C_GPIONO(S3C_GPIO_BANKL, 11)
  2119. #define S3C_GPL11_INP (0)
  2120. #define S3C_GPL11_OUTP (1)
  2121. #define S3C_GPL11_SPI_MOSI1 (2)
  2122. #define S3C_GPL11_EXTINT19 (3)
  2123. #define S3C_GPL11_RESERVED1 (4)
  2124. #define S3C_GPL11_IOWR_CF (5)
  2125. #define S3C_GPL11_RESERVED2 (6)
  2126. #define S3C_GPL11_OTG_ULPI_DIR (7)
  2127. #define S3C_GPL12 S3C_GPIONO(S3C_GPIO_BANKL, 12)
  2128. #define S3C_GPL12_INP (0)
  2129. #define S3C_GPL12_OUTP (1)
  2130. #define S3C_GPL12_SPI_MISO1 (2)
  2131. #define S3C_GPL12_EXTINT20 (3)
  2132. #define S3C_GPL12_RESERVED1 (4)
  2133. #define S3C_GPL12_IORDY_CF (5)
  2134. #define S3C_GPL12_RESERVED2 (6)
  2135. #define S3C_GPL12_RESERVED3 (7)
  2136. #define S3C_GPL13 S3C_GPIONO(S3C_GPIO_BANKL, 13)
  2137. #define S3C_GPL13_INP (0)
  2138. #define S3C_GPL13_OUTP (1)
  2139. #define S3C_GPL14_nSS0 (2)
  2140. #define S3C_GPL13_EXTINT21 (3)
  2141. #define S3C_GPL13_RESERVED1 (4)
  2142. #define S3C_GPL13_DATA_CF8 (5)
  2143. #define S3C_GPL13_RESERVED2 (6)
  2144. #define S3C_GPL13_RESERVED3 (7)
  2145. #define S3C_GPL14 S3C_GPIONO(S3C_GPIO_BANKL, 14)
  2146. #define S3C_GPL14_INP (0)
  2147. #define S3C_GPL14_OUTP (1)
  2148. #define S3C_GPL14_nSS1 (2)
  2149. #define S3C_GPL14_EXTINT22 (3)
  2150. #define S3C_GPL14_RESERVED1 (4)
  2151. #define S3C_GPL14_DATA_CF9 (5)
  2152. #define S3C_GPL14_RESERVED2 (6)
  2153. #define S3C_GPL14_RESERVED3 (7)
  2154. /* GPM : 6 in/out port . Host I/F, EINT */
  2155. #define S3C_GPMDAT S3C_GPIOREG(0x824)
  2156. #define S3C_GPMCON S3C_GPIOREG(0x820)
  2157. #define S3C_GPMPU S3C_GPIOREG(0x828)
  2158. #define S3C_GPM0 S3C_GPIONO(S3C_GPIO_BANKM, 0)
  2159. #define S3C_GPM0_INP (0)
  2160. #define S3C_GPM0_OUTP (1)
  2161. #define S3C_GPM0_HOSTIF_CS (2)
  2162. #define S3C_GPM0_EXTINT23 (3)
  2163. #define S3C_GPM0_RESERVED1 (4)
  2164. #define S3C_GPM0_DATA_CF10 (5)
  2165. #define S3C_GPM0_CE_CF0 (6)
  2166. #define S3C_GPM0_RESERVED2 (7)
  2167. #define S3C_GPM1 S3C_GPIONO(S3C_GPIO_BANKM, 1)
  2168. #define S3C_GPM1_INP (0)
  2169. #define S3C_GPM1_OUTP (1)
  2170. #define S3C_GPM1_HOSTIF_CS_M (2)
  2171. #define S3C_GPM1_EXTINT24 (3)
  2172. #define S3C_GPM1_RESERVED1 (4)
  2173. #define S3C_GPM1_DATA_CF11 (5)
  2174. #define S3C_GPM1_CE_CF1 (6)
  2175. #define S3C_GPM1_RESERVED2 (7)
  2176. #define S3C_GPM2 S3C_GPIONO(S3C_GPIO_BANKM, 2)
  2177. #define S3C_GPM2_INP (0)
  2178. #define S3C_GPM2_OUTP (1)
  2179. #define S3C_GPM2_HOST_IF_CS_S (2)
  2180. #define S3C_GPM2_EXTINT25 (3)
  2181. #define S3C_GPM2_HOSTIF_MDP_VSYNC (4)
  2182. #define S3C_GPM2_DATA_CF12 (5)
  2183. #define S3C_GPM2_IORD_CF (6)
  2184. #define S3C_GPM2_RESERVED2 (7)
  2185. #define S3C_GPM3 S3C_GPIONO(S3C_GPIO_BANKM, 3)
  2186. #define S3C_GPM3_INP (0)
  2187. #define S3C_GPM3_OUTP (1)
  2188. #define S3C_GPM3_HOSTIF_WE (2)
  2189. #define S3C_GPM3_EXTINT26 (3)
  2190. #define S3C_GPM3_RESERVED1 (4)
  2191. #define S3C_GPM3_DATA_CF13 (5)
  2192. #define S3C_GPM3_IOWR_CF (6)
  2193. #define S3C_GPM3_RESERVED2 (7)
  2194. #define S3C_GPM4 S3C_GPIONO(S3C_GPIO_BANKM, 4)
  2195. #define S3C_GPM4_INP (0)
  2196. #define S3C_GPM4_OUTP (1)
  2197. #define S3C_GPM4_HOSTIF_OE (2)
  2198. #define S3C_GPM4_EXTINT27 (3)
  2199. #define S3C_GPM4_RESERVED1 (4)
  2200. #define S3C_GPM4_DATA_CF14 (5)
  2201. #define S3C_GPM4_IORDY_CF (6)
  2202. #define S3C_GPM4_RESERVED2 (7)
  2203. #define S3C_GPM5 S3C_GPIONO(S3C_GPIO_BANKM, 5)
  2204. #define S3C_GPM5_INP (0)
  2205. #define S3C_GPM5_OUTP (1)
  2206. #define S3C_GPM5_HOSTIF_INTR (2)
  2207. #define S3C_GPM5_CF_DATA_DIR (3)
  2208. #define S3C_GPM5_RESERVED1 (4)
  2209. #define S3C_GPM5_DATA_CF15 (5)
  2210. #define S3C_GPM5_RESERVED2 (6)
  2211. #define S3C_GPM5_RESERVED3 (7)
  2212. /* GPN : 16 in/out port . EINT */
  2213. #define S3C_GPNDAT S3C_GPIOREG(0x834)
  2214. #define S3C_GPNCON S3C_GPIOREG(0x830)
  2215. #define S3C_GPNPU S3C_GPIOREG(0x838)
  2216. #define S3C_GPN0 S3C_GPIONO(S3C_GPIO_BANKN, 0)
  2217. #define S3C_GPN0_INP (0)
  2218. #define S3C_GPN0_OUTP (1)
  2219. #define S3C_GPN0_EXTINT0 (2)
  2220. #define S3C_GPN0_KEYPAD_ROW0 (3)
  2221. #define S3C_GPN1 S3C_GPIONO(S3C_GPIO_BANKN, 1)
  2222. #define S3C_GPN1_INP (0)
  2223. #define S3C_GPN1_OUTP (1)
  2224. #define S3C_GPN1_EXTINT1 (2)
  2225. #define S3C_GPN1_KEYPAD_ROW1 (3)
  2226. #define S3C_GPN2 S3C_GPIONO(S3C_GPIO_BANKN, 2)
  2227. #define S3C_GPN2_INP (0)
  2228. #define S3C_GPN2_OUTP (1)
  2229. #define S3C_GPN2_EXTINT2 (2)
  2230. #define S3C_GPN2_KEYPAD_ROW2 (3)
  2231. #define S3C_GPN3 S3C_GPIONO(S3C_GPIO_BANKN, 3)
  2232. #define S3C_GPN3_INP (0)
  2233. #define S3C_GPN3_OUTP (1)
  2234. #define S3C_GPN3_EXTINT3 (2)
  2235. #define S3C_GPN3_KEYPAD_ROW3 (3)
  2236. #define S3C_GPN4 S3C_GPIONO(S3C_GPIO_BANKN, 4)
  2237. #define S3C_GPN4_INP (0)
  2238. #define S3C_GPN4_OUTP (1)
  2239. #define S3C_GPN4_EXTINT4 (2)
  2240. #define S3C_GPN4_KEYPAD_ROW4 (3)
  2241. #define S3C_GPN5 S3C_GPIONO(S3C_GPIO_BANKN, 5)
  2242. #define S3C_GPN5_INP (0)
  2243. #define S3C_GPN5_OUTP (1)
  2244. #define S3C_GPN5_EXTINT5 (2)
  2245. #define S3C_GPN5_KEYPAD_ROW5 (3)
  2246. #define S3C_GPN6 S3C_GPIONO(S3C_GPIO_BANKN, 6)
  2247. #define S3C_GPN6_INP (0)
  2248. #define S3C_GPN6_OUTP (1)
  2249. #define S3C_GPN6_EXTINT6 (2)
  2250. #define S3C_GPN6_KEYPAD_ROW6 (3)
  2251. #define S3C_GPN7 S3C_GPIONO(S3C_GPIO_BANKN, 7)
  2252. #define S3C_GPN7_INP (0)
  2253. #define S3C_GPN7_OUTP (1)
  2254. #define S3C_GPN7_EXTINT7 (2)
  2255. #define S3C_GPN7_KEYPAD_ROW7 (3)
  2256. #define S3C_GPN8 S3C_GPIONO(S3C_GPIO_BANKN, 8)
  2257. #define S3C_GPN8_INP (0)
  2258. #define S3C_GPN8_OUTP (1)
  2259. #define S3C_GPN8_EXTINT8 (2)
  2260. #define S3C_GPN8_ADDR_CF0 (3)
  2261. #define S3C_GPN9 S3C_GPIONO(S3C_GPIO_BANKN, 9)
  2262. #define S3C_GPN9_INP (0)
  2263. #define S3C_GPN9_OUTP (1)
  2264. #define S3C_GPN9_EXTINT9 (2)
  2265. #define S3C_GPN9_ADDR_CF1 (3)
  2266. #define S3C_GPN10 S3C_GPIONO(S3C_GPIO_BANKN, 10)
  2267. #define S3C_GPN10_INP (0)
  2268. #define S3C_GPN10_OUTP (1)
  2269. #define S3C_GPN10_EXTINT10 (2)
  2270. #define S3C_GPN10_ADDR_CF2 (3)
  2271. #define S3C_GPN11 S3C_GPIONO(S3C_GPIO_BANKN, 11)
  2272. #define S3C_GPN11_INP (0)
  2273. #define S3C_GPN11_OUTP (1)
  2274. #define S3C_GPN11_EXTINT11 (2)
  2275. #define S3C_GPN11_RESERVED (3)
  2276. #define S3C_GPN12 S3C_GPIONO(S3C_GPIO_BANKN, 12)
  2277. #define S3C_GPN12_INP (0)
  2278. #define S3C_GPN12_OUTP (1)
  2279. #define S3C_GPN12_EXTINT12 (2)
  2280. #define S3C_GPN12_RESERVED (3)
  2281. #define S3C_GPN13 S3C_GPIONO(S3C_GPIO_BANKN, 13)
  2282. #define S3C_GPN13_INP (0)
  2283. #define S3C_GPN13_OUTP (1)
  2284. #define S3C_GPN13_EXTINT13 (2)
  2285. #define S3C_GPN13_RESERVED (3)
  2286. #define S3C_GPN14 S3C_GPIONO(S3C_GPIO_BANKN, 14)
  2287. #define S3C_GPN14_INP (0)
  2288. #define S3C_GPN14_OUTP (1)
  2289. #define S3C_GPN14_EXTINT14 (2)
  2290. #define S3C_GPN14_RESERVED (3)
  2291. #define S3C_GPN15 S3C_GPIONO(S3C_GPIO_BANKN, 15)
  2292. #define S3C_GPN15_INP (0)
  2293. #define S3C_GPN15_OUTP (1)
  2294. #define S3C_GPN15_EXTINT15 (2)
  2295. #define S3C_GPN15_RESERVED (3)
  2296. /* GPO : 16 in/out port . Memory Port 0 */
  2297. #define S3C_GPODAT S3C_GPIOREG(0x144)
  2298. #define S3C_GPOCON S3C_GPIOREG(0x140)
  2299. #define S3C_GPOPU S3C_GPIOREG(0x148)
  2300. /* GPP : 15 in/out port . Memory Port 0 */
  2301. #define S3C_GPPDAT S3C_GPIOREG(0x164)
  2302. #define S3C_GPPCON S3C_GPIOREG(0x160)
  2303. #define S3C_GPPPU S3C_GPIOREG(0x168)
  2304. /* GPQ : 9 in/out port . Memory Port 0 Dram part */
  2305. #define S3C_GPQDAT S3C_GPIOREG(0x184)
  2306. #define S3C_GPQCON S3C_GPIOREG(0x180)
  2307. #define S3C_GPQPU S3C_GPIOREG(0x188)
  2308. #define S3C_MEM0CONSTOP S3C_GPIOREG(0x1B0)
  2309. #define S3C_MEM1CONSTOP S3C_GPIOREG(0x1B4)
  2310. #define S3C_MEM0CONSLP0 S3C_GPIOREG(0x1C0)
  2311. #define S3C_MEM0CONSLP1 S3C_GPIOREG(0x1C4)
  2312. #define S3C_MEM1CONSLP S3C_GPIOREG(0x1C8)
  2313. #define S3C_MEM0DRVCON S3C_GPIOREG(0x1D0)
  2314. #define S3C_MEM1DRVCON S3C_GPIOREG(0x1D4)
  2315. #define S3C_EINTCON0 S3C_GPIOREG(0x900)
  2316. #define S3C_EINTCON1 S3C_GPIOREG(0x904)
  2317. #define S3C_EINTFLTCON0 S3C_GPIOREG(0x910)
  2318. #define S3C_EINTFLTCON1 S3C_GPIOREG(0x914)
  2319. #define S3C_EINTFLTCON2 S3C_GPIOREG(0x918)
  2320. #define S3C_EINTFLTCON3 S3C_GPIOREG(0x91C)
  2321. #define S3C_EINTMASK S3C_GPIOREG(0x920)
  2322. #define S3C_EINTPEND S3C_GPIOREG(0x924) /* External Interrupt Pending Register */
  2323. #define S3C_EINT12CON S3C_GPIOREG(0x200) /* External Interrupt 1,2 Configuration Register */
  2324. #define S3C_EINT34CON S3C_GPIOREG(0x204) /* External Interrupt 3,4 Configuration Register */
  2325. #define S3C_EINT56CON S3C_GPIOREG(0x208) /* External Interrupt 5,6 Configuration Register */
  2326. #define S3C_EINT78CON S3C_GPIOREG(0x20C) /* External Interrupt 7,8 Configuration Register */
  2327. #define S3C_EINT9CON S3C_GPIOREG(0x210) /* External Interrupt 9 Configuration Register */
  2328. #define S3C_EINT12FLTCON S3C_GPIOREG(0x220) /* External Interrupt 1,2 Filter Control Register */
  2329. #define S3C_EINT34FLTCON S3C_GPIOREG(0x224) /* External Interrupt 3,4 Filter Control Register */
  2330. #define S3C_EINT56FLTCON S3C_GPIOREG(0x228) /* External Interrupt 5,6 Filter Control Register */
  2331. #define S3C_EINT78FLTCON S3C_GPIOREG(0x22C) /* External Interrupt 7,8 Filter Control Register */
  2332. #define S3C_EINT9FLTCON S3C_GPIOREG(0x230) /* External Interrupt 9 Filter Control Register */
  2333. #define S3C_EINT12MASK S3C_GPIOREG(0x240) /* External Interrupt 1,2 Mask Register */
  2334. #define S3C_EINT34MASK S3C_GPIOREG(0x244) /* External Interrupt 3,4 Mask Register */
  2335. #define S3C_EINT56MASK S3C_GPIOREG(0x248) /* External Interrupt 5,6 Mask Register */
  2336. #define S3C_EINT78MASK S3C_GPIOREG(0x24C) /* External Interrupt 7,8 Mask Register */
  2337. #define S3C_EINT9MASK S3C_GPIOREG(0x250) /* External Interrupt 9 Mask Register */
  2338. #define S3C_EINT12PEND S3C_GPIOREG(0x260) /* External Interrupt 1,2 Pending Register */
  2339. #define S3C_EINT34PEND S3C_GPIOREG(0x264) /* External Interrupt 3,4 Pending Register */
  2340. #define S3C_EINT56PEND S3C_GPIOREG(0x268) /* External Interrupt 5,6 Pending Register */
  2341. #define S3C_EINT78PEND S3C_GPIOREG(0x26C) /* External Interrupt 7,8 Pending Register */
  2342. #define S3C_EINT9PEND S3C_GPIOREG(0x270) /* External Interrupt 9 Pending Register */
  2343. #define S3C_PRIORITY S3C_GPIOREG(0x280) /* Priority Control Register */
  2344. #define S3C_SERVICE S3C_GPIOREG(0x284) /* Current Service Register */
  2345. #define S3C_SERVICEPEND S3C_GPIOREG(0x288) /* Current Service Pending Register */
  2346. /* values for S3C_EXTINT0 */
  2347. #define S3C_EXTINT_LOWLEV (0x00)
  2348. #define S3C_EXTINT_HILEV (0x01)
  2349. #define S3C_EXTINT_FALLEDGE (0x02)
  2350. #define S3C_EXTINT_RISEEDGE (0x04)
  2351. #define S3C_EXTINT_BOTHEDGE (0x06)
  2352. /* Special port control register*/
  2353. #define S3C_SPCON S3C_GPIOREG(0x1A0)
  2354. #define S3C_SPONSLP S3C_GPIOREG(0x880)
  2355. #define S3C_SLPEN S3C_GPIOREG(0x934)
  2356. #endif
  2357. #endif /* __ASM_ARCH_REGS_GPIO_H */