vga16fb.c 39 KB

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  1. /*
  2. * linux/drivers/video/vga16.c -- VGA 16-color framebuffer driver
  3. *
  4. * Copyright 1999 Ben Pfaff <pfaffben@debian.org> and Petr Vandrovec <VANDROVE@vc.cvut.cz>
  5. * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
  6. * Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
  7. *
  8. * This file is subject to the terms and conditions of the GNU General
  9. * Public License. See the file COPYING in the main directory of this
  10. * archive for more details.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/errno.h>
  15. #include <linux/string.h>
  16. #include <linux/mm.h>
  17. #include <linux/slab.h>
  18. #include <linux/delay.h>
  19. #include <linux/fb.h>
  20. #include <linux/ioport.h>
  21. #include <linux/init.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/screen_info.h>
  24. #include <asm/io.h>
  25. #include <video/vga.h>
  26. #define GRAPHICS_ADDR_REG VGA_GFX_I /* Graphics address register. */
  27. #define GRAPHICS_DATA_REG VGA_GFX_D /* Graphics data register. */
  28. #define SET_RESET_INDEX VGA_GFX_SR_VALUE /* Set/Reset Register index. */
  29. #define ENABLE_SET_RESET_INDEX VGA_GFX_SR_ENABLE /* Enable Set/Reset Register index. */
  30. #define DATA_ROTATE_INDEX VGA_GFX_DATA_ROTATE /* Data Rotate Register index. */
  31. #define GRAPHICS_MODE_INDEX VGA_GFX_MODE /* Graphics Mode Register index. */
  32. #define BIT_MASK_INDEX VGA_GFX_BIT_MASK /* Bit Mask Register index. */
  33. #define dac_reg (VGA_PEL_IW)
  34. #define dac_val (VGA_PEL_D)
  35. #define VGA_FB_PHYS 0xA0000
  36. #define VGA_FB_PHYS_LEN 65536
  37. #define MODE_SKIP4 1
  38. #define MODE_8BPP 2
  39. #define MODE_CFB 4
  40. #define MODE_TEXT 8
  41. /* --------------------------------------------------------------------- */
  42. /*
  43. * card parameters
  44. */
  45. struct vga16fb_par {
  46. /* structure holding original VGA register settings when the
  47. screen is blanked */
  48. struct {
  49. unsigned char SeqCtrlIndex; /* Sequencer Index reg. */
  50. unsigned char CrtCtrlIndex; /* CRT-Contr. Index reg. */
  51. unsigned char CrtMiscIO; /* Miscellaneous register */
  52. unsigned char HorizontalTotal; /* CRT-Controller:00h */
  53. unsigned char HorizDisplayEnd; /* CRT-Controller:01h */
  54. unsigned char StartHorizRetrace;/* CRT-Controller:04h */
  55. unsigned char EndHorizRetrace; /* CRT-Controller:05h */
  56. unsigned char Overflow; /* CRT-Controller:07h */
  57. unsigned char StartVertRetrace; /* CRT-Controller:10h */
  58. unsigned char EndVertRetrace; /* CRT-Controller:11h */
  59. unsigned char ModeControl; /* CRT-Controller:17h */
  60. unsigned char ClockingMode; /* Seq-Controller:01h */
  61. } vga_state;
  62. struct vgastate state;
  63. struct mutex open_lock;
  64. unsigned int ref_count;
  65. int palette_blanked, vesa_blanked, mode, isVGA;
  66. u8 misc, pel_msk, vss, clkdiv;
  67. u8 crtc[VGA_CRT_C];
  68. };
  69. /* --------------------------------------------------------------------- */
  70. static struct fb_var_screeninfo vga16fb_defined __initdata = {
  71. .xres = 640,
  72. .yres = 480,
  73. .xres_virtual = 640,
  74. .yres_virtual = 480,
  75. .bits_per_pixel = 4,
  76. .activate = FB_ACTIVATE_TEST,
  77. .height = -1,
  78. .width = -1,
  79. .pixclock = 39721,
  80. .left_margin = 48,
  81. .right_margin = 16,
  82. .upper_margin = 33,
  83. .lower_margin = 10,
  84. .hsync_len = 96,
  85. .vsync_len = 2,
  86. .vmode = FB_VMODE_NONINTERLACED,
  87. };
  88. /* name should not depend on EGA/VGA */
  89. static struct fb_fix_screeninfo vga16fb_fix __initdata = {
  90. .id = "VGA16 VGA",
  91. .smem_start = VGA_FB_PHYS,
  92. .smem_len = VGA_FB_PHYS_LEN,
  93. .type = FB_TYPE_VGA_PLANES,
  94. .type_aux = FB_AUX_VGA_PLANES_VGA4,
  95. .visual = FB_VISUAL_PSEUDOCOLOR,
  96. .xpanstep = 8,
  97. .ypanstep = 1,
  98. .line_length = 640/8,
  99. .accel = FB_ACCEL_NONE
  100. };
  101. /* The VGA's weird architecture often requires that we read a byte and
  102. write a byte to the same location. It doesn't matter *what* byte
  103. we write, however. This is because all the action goes on behind
  104. the scenes in the VGA's 32-bit latch register, and reading and writing
  105. video memory just invokes latch behavior.
  106. To avoid race conditions (is this necessary?), reading and writing
  107. the memory byte should be done with a single instruction. One
  108. suitable instruction is the x86 bitwise OR. The following
  109. read-modify-write routine should optimize to one such bitwise
  110. OR. */
  111. static inline void rmw(volatile char __iomem *p)
  112. {
  113. readb(p);
  114. writeb(1, p);
  115. }
  116. /* Set the Graphics Mode Register, and return its previous value.
  117. Bits 0-1 are write mode, bit 3 is read mode. */
  118. static inline int setmode(int mode)
  119. {
  120. int oldmode;
  121. vga_io_w(GRAPHICS_ADDR_REG, GRAPHICS_MODE_INDEX);
  122. oldmode = vga_io_r(GRAPHICS_DATA_REG);
  123. vga_io_w(GRAPHICS_DATA_REG, mode);
  124. return oldmode;
  125. }
  126. /* Select the Bit Mask Register and return its value. */
  127. static inline int selectmask(void)
  128. {
  129. return vga_io_rgfx(BIT_MASK_INDEX);
  130. }
  131. /* Set the value of the Bit Mask Register. It must already have been
  132. selected with selectmask(). */
  133. static inline void setmask(int mask)
  134. {
  135. vga_io_w(GRAPHICS_DATA_REG, mask);
  136. }
  137. /* Set the Data Rotate Register and return its old value.
  138. Bits 0-2 are rotate count, bits 3-4 are logical operation
  139. (0=NOP, 1=AND, 2=OR, 3=XOR). */
  140. static inline int setop(int op)
  141. {
  142. int oldop;
  143. vga_io_w(GRAPHICS_ADDR_REG, DATA_ROTATE_INDEX);
  144. oldop = vga_io_r(GRAPHICS_DATA_REG);
  145. vga_io_w(GRAPHICS_DATA_REG, op);
  146. return oldop;
  147. }
  148. /* Set the Enable Set/Reset Register and return its old value.
  149. The code here always uses value 0xf for thsi register. */
  150. static inline int setsr(int sr)
  151. {
  152. int oldsr;
  153. vga_io_w(GRAPHICS_ADDR_REG, ENABLE_SET_RESET_INDEX);
  154. oldsr = vga_io_r(GRAPHICS_DATA_REG);
  155. vga_io_w(GRAPHICS_DATA_REG, sr);
  156. return oldsr;
  157. }
  158. /* Set the Set/Reset Register and return its old value. */
  159. static inline int setcolor(int color)
  160. {
  161. int oldcolor;
  162. vga_io_w(GRAPHICS_ADDR_REG, SET_RESET_INDEX);
  163. oldcolor = vga_io_r(GRAPHICS_DATA_REG);
  164. vga_io_w(GRAPHICS_DATA_REG, color);
  165. return oldcolor;
  166. }
  167. /* Return the value in the Graphics Address Register. */
  168. static inline int getindex(void)
  169. {
  170. return vga_io_r(GRAPHICS_ADDR_REG);
  171. }
  172. /* Set the value in the Graphics Address Register. */
  173. static inline void setindex(int index)
  174. {
  175. vga_io_w(GRAPHICS_ADDR_REG, index);
  176. }
  177. static void vga16fb_pan_var(struct fb_info *info,
  178. struct fb_var_screeninfo *var)
  179. {
  180. struct vga16fb_par *par = info->par;
  181. u32 xoffset, pos;
  182. xoffset = var->xoffset;
  183. if (info->var.bits_per_pixel == 8) {
  184. pos = (info->var.xres_virtual * var->yoffset + xoffset) >> 2;
  185. } else if (par->mode & MODE_TEXT) {
  186. int fh = 16; // FIXME !!! font height. Fugde for now.
  187. pos = (info->var.xres_virtual * (var->yoffset / fh) + xoffset) >> 3;
  188. } else {
  189. if (info->var.nonstd)
  190. xoffset--;
  191. pos = (info->var.xres_virtual * var->yoffset + xoffset) >> 3;
  192. }
  193. vga_io_wcrt(VGA_CRTC_START_HI, pos >> 8);
  194. vga_io_wcrt(VGA_CRTC_START_LO, pos & 0xFF);
  195. /* if we support CFB4, then we must! support xoffset with pixel
  196. * granularity if someone supports xoffset in bit resolution */
  197. vga_io_r(VGA_IS1_RC); /* reset flip-flop */
  198. vga_io_w(VGA_ATT_IW, VGA_ATC_PEL);
  199. if (var->bits_per_pixel == 8)
  200. vga_io_w(VGA_ATT_IW, (xoffset & 3) << 1);
  201. else
  202. vga_io_w(VGA_ATT_IW, xoffset & 7);
  203. vga_io_r(VGA_IS1_RC);
  204. vga_io_w(VGA_ATT_IW, 0x20);
  205. }
  206. static void vga16fb_update_fix(struct fb_info *info)
  207. {
  208. if (info->var.bits_per_pixel == 4) {
  209. if (info->var.nonstd) {
  210. info->fix.type = FB_TYPE_PACKED_PIXELS;
  211. info->fix.line_length = info->var.xres_virtual / 2;
  212. } else {
  213. info->fix.type = FB_TYPE_VGA_PLANES;
  214. info->fix.type_aux = FB_AUX_VGA_PLANES_VGA4;
  215. info->fix.line_length = info->var.xres_virtual / 8;
  216. }
  217. } else if (info->var.bits_per_pixel == 0) {
  218. info->fix.type = FB_TYPE_TEXT;
  219. info->fix.type_aux = FB_AUX_TEXT_CGA;
  220. info->fix.line_length = info->var.xres_virtual / 4;
  221. } else { /* 8bpp */
  222. if (info->var.nonstd) {
  223. info->fix.type = FB_TYPE_VGA_PLANES;
  224. info->fix.type_aux = FB_AUX_VGA_PLANES_CFB8;
  225. info->fix.line_length = info->var.xres_virtual / 4;
  226. } else {
  227. info->fix.type = FB_TYPE_PACKED_PIXELS;
  228. info->fix.line_length = info->var.xres_virtual;
  229. }
  230. }
  231. }
  232. static void vga16fb_clock_chip(struct vga16fb_par *par,
  233. unsigned int pixclock,
  234. const struct fb_info *info,
  235. int mul, int div)
  236. {
  237. static const struct {
  238. u32 pixclock;
  239. u8 misc;
  240. u8 seq_clock_mode;
  241. } *ptr, *best, vgaclocks[] = {
  242. { 79442 /* 12.587 */, 0x00, 0x08},
  243. { 70616 /* 14.161 */, 0x04, 0x08},
  244. { 39721 /* 25.175 */, 0x00, 0x00},
  245. { 35308 /* 28.322 */, 0x04, 0x00},
  246. { 0 /* bad */, 0x00, 0x00}};
  247. int err;
  248. pixclock = (pixclock * mul) / div;
  249. best = vgaclocks;
  250. err = pixclock - best->pixclock;
  251. if (err < 0) err = -err;
  252. for (ptr = vgaclocks + 1; ptr->pixclock; ptr++) {
  253. int tmp;
  254. tmp = pixclock - ptr->pixclock;
  255. if (tmp < 0) tmp = -tmp;
  256. if (tmp < err) {
  257. err = tmp;
  258. best = ptr;
  259. }
  260. }
  261. par->misc |= best->misc;
  262. par->clkdiv = best->seq_clock_mode;
  263. pixclock = (best->pixclock * div) / mul;
  264. }
  265. #define FAIL(X) return -EINVAL
  266. static int vga16fb_open(struct fb_info *info, int user)
  267. {
  268. struct vga16fb_par *par = info->par;
  269. mutex_lock(&par->open_lock);
  270. if (!par->ref_count) {
  271. memset(&par->state, 0, sizeof(struct vgastate));
  272. par->state.flags = VGA_SAVE_FONTS | VGA_SAVE_MODE |
  273. VGA_SAVE_CMAP;
  274. save_vga(&par->state);
  275. }
  276. par->ref_count++;
  277. mutex_unlock(&par->open_lock);
  278. return 0;
  279. }
  280. static int vga16fb_release(struct fb_info *info, int user)
  281. {
  282. struct vga16fb_par *par = info->par;
  283. mutex_lock(&par->open_lock);
  284. if (!par->ref_count) {
  285. mutex_unlock(&par->open_lock);
  286. return -EINVAL;
  287. }
  288. if (par->ref_count == 1)
  289. restore_vga(&par->state);
  290. par->ref_count--;
  291. mutex_unlock(&par->open_lock);
  292. return 0;
  293. }
  294. static int vga16fb_check_var(struct fb_var_screeninfo *var,
  295. struct fb_info *info)
  296. {
  297. struct vga16fb_par *par = info->par;
  298. u32 xres, right, hslen, left, xtotal;
  299. u32 yres, lower, vslen, upper, ytotal;
  300. u32 vxres, xoffset, vyres, yoffset;
  301. u32 pos;
  302. u8 r7, rMode;
  303. int shift;
  304. int mode;
  305. u32 maxmem;
  306. par->pel_msk = 0xFF;
  307. if (var->bits_per_pixel == 4) {
  308. if (var->nonstd) {
  309. if (!par->isVGA)
  310. return -EINVAL;
  311. shift = 3;
  312. mode = MODE_SKIP4 | MODE_CFB;
  313. maxmem = 16384;
  314. par->pel_msk = 0x0F;
  315. } else {
  316. shift = 3;
  317. mode = 0;
  318. maxmem = 65536;
  319. }
  320. } else if (var->bits_per_pixel == 8) {
  321. if (!par->isVGA)
  322. return -EINVAL; /* no support on EGA */
  323. shift = 2;
  324. if (var->nonstd) {
  325. mode = MODE_8BPP | MODE_CFB;
  326. maxmem = 65536;
  327. } else {
  328. mode = MODE_SKIP4 | MODE_8BPP | MODE_CFB;
  329. maxmem = 16384;
  330. }
  331. } else
  332. return -EINVAL;
  333. xres = (var->xres + 7) & ~7;
  334. vxres = (var->xres_virtual + 0xF) & ~0xF;
  335. xoffset = (var->xoffset + 7) & ~7;
  336. left = (var->left_margin + 7) & ~7;
  337. right = (var->right_margin + 7) & ~7;
  338. hslen = (var->hsync_len + 7) & ~7;
  339. if (vxres < xres)
  340. vxres = xres;
  341. if (xres + xoffset > vxres)
  342. xoffset = vxres - xres;
  343. var->xres = xres;
  344. var->right_margin = right;
  345. var->hsync_len = hslen;
  346. var->left_margin = left;
  347. var->xres_virtual = vxres;
  348. var->xoffset = xoffset;
  349. xres >>= shift;
  350. right >>= shift;
  351. hslen >>= shift;
  352. left >>= shift;
  353. vxres >>= shift;
  354. xtotal = xres + right + hslen + left;
  355. if (xtotal >= 256)
  356. FAIL("xtotal too big");
  357. if (hslen > 32)
  358. FAIL("hslen too big");
  359. if (right + hslen + left > 64)
  360. FAIL("hblank too big");
  361. par->crtc[VGA_CRTC_H_TOTAL] = xtotal - 5;
  362. par->crtc[VGA_CRTC_H_BLANK_START] = xres - 1;
  363. par->crtc[VGA_CRTC_H_DISP] = xres - 1;
  364. pos = xres + right;
  365. par->crtc[VGA_CRTC_H_SYNC_START] = pos;
  366. pos += hslen;
  367. par->crtc[VGA_CRTC_H_SYNC_END] = pos & 0x1F;
  368. pos += left - 2; /* blank_end + 2 <= total + 5 */
  369. par->crtc[VGA_CRTC_H_BLANK_END] = (pos & 0x1F) | 0x80;
  370. if (pos & 0x20)
  371. par->crtc[VGA_CRTC_H_SYNC_END] |= 0x80;
  372. yres = var->yres;
  373. lower = var->lower_margin;
  374. vslen = var->vsync_len;
  375. upper = var->upper_margin;
  376. vyres = var->yres_virtual;
  377. yoffset = var->yoffset;
  378. if (yres > vyres)
  379. vyres = yres;
  380. if (vxres * vyres > maxmem) {
  381. vyres = maxmem / vxres;
  382. if (vyres < yres)
  383. return -ENOMEM;
  384. }
  385. if (yoffset + yres > vyres)
  386. yoffset = vyres - yres;
  387. var->yres = yres;
  388. var->lower_margin = lower;
  389. var->vsync_len = vslen;
  390. var->upper_margin = upper;
  391. var->yres_virtual = vyres;
  392. var->yoffset = yoffset;
  393. if (var->vmode & FB_VMODE_DOUBLE) {
  394. yres <<= 1;
  395. lower <<= 1;
  396. vslen <<= 1;
  397. upper <<= 1;
  398. }
  399. ytotal = yres + lower + vslen + upper;
  400. if (ytotal > 1024) {
  401. ytotal >>= 1;
  402. yres >>= 1;
  403. lower >>= 1;
  404. vslen >>= 1;
  405. upper >>= 1;
  406. rMode = 0x04;
  407. } else
  408. rMode = 0x00;
  409. if (ytotal > 1024)
  410. FAIL("ytotal too big");
  411. if (vslen > 16)
  412. FAIL("vslen too big");
  413. par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
  414. r7 = 0x10; /* disable linecompare */
  415. if (ytotal & 0x100) r7 |= 0x01;
  416. if (ytotal & 0x200) r7 |= 0x20;
  417. par->crtc[VGA_CRTC_PRESET_ROW] = 0;
  418. par->crtc[VGA_CRTC_MAX_SCAN] = 0x40; /* 1 scanline, no linecmp */
  419. if (var->vmode & FB_VMODE_DOUBLE)
  420. par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
  421. par->crtc[VGA_CRTC_CURSOR_START] = 0x20;
  422. par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
  423. if ((mode & (MODE_CFB | MODE_8BPP)) == MODE_CFB)
  424. xoffset--;
  425. pos = yoffset * vxres + (xoffset >> shift);
  426. par->crtc[VGA_CRTC_START_HI] = pos >> 8;
  427. par->crtc[VGA_CRTC_START_LO] = pos & 0xFF;
  428. par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
  429. par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
  430. pos = yres - 1;
  431. par->crtc[VGA_CRTC_V_DISP_END] = pos & 0xFF;
  432. par->crtc[VGA_CRTC_V_BLANK_START] = pos & 0xFF;
  433. if (pos & 0x100)
  434. r7 |= 0x0A; /* 0x02 -> DISP_END, 0x08 -> BLANK_START */
  435. if (pos & 0x200) {
  436. r7 |= 0x40; /* 0x40 -> DISP_END */
  437. par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20; /* BLANK_START */
  438. }
  439. pos += lower;
  440. par->crtc[VGA_CRTC_V_SYNC_START] = pos & 0xFF;
  441. if (pos & 0x100)
  442. r7 |= 0x04;
  443. if (pos & 0x200)
  444. r7 |= 0x80;
  445. pos += vslen;
  446. par->crtc[VGA_CRTC_V_SYNC_END] = (pos & 0x0F) & ~0x10; /* disabled IRQ */
  447. pos += upper - 1; /* blank_end + 1 <= ytotal + 2 */
  448. par->crtc[VGA_CRTC_V_BLANK_END] = pos & 0xFF; /* 0x7F for original VGA,
  449. but some SVGA chips requires all 8 bits to set */
  450. if (vxres >= 512)
  451. FAIL("vxres too long");
  452. par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
  453. if (mode & MODE_SKIP4)
  454. par->crtc[VGA_CRTC_UNDERLINE] = 0x5F; /* 256, cfb8 */
  455. else
  456. par->crtc[VGA_CRTC_UNDERLINE] = 0x1F; /* 16, vgap */
  457. par->crtc[VGA_CRTC_MODE] = rMode | ((mode & MODE_TEXT) ? 0xA3 : 0xE3);
  458. par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
  459. par->crtc[VGA_CRTC_OVERFLOW] = r7;
  460. par->vss = 0x00; /* 3DA */
  461. par->misc = 0xE3; /* enable CPU, ports 0x3Dx, positive sync */
  462. if (var->sync & FB_SYNC_HOR_HIGH_ACT)
  463. par->misc &= ~0x40;
  464. if (var->sync & FB_SYNC_VERT_HIGH_ACT)
  465. par->misc &= ~0x80;
  466. par->mode = mode;
  467. if (mode & MODE_8BPP)
  468. /* pixel clock == vga clock / 2 */
  469. vga16fb_clock_chip(par, var->pixclock, info, 1, 2);
  470. else
  471. /* pixel clock == vga clock */
  472. vga16fb_clock_chip(par, var->pixclock, info, 1, 1);
  473. var->red.offset = var->green.offset = var->blue.offset =
  474. var->transp.offset = 0;
  475. var->red.length = var->green.length = var->blue.length =
  476. (par->isVGA) ? 6 : 2;
  477. var->transp.length = 0;
  478. var->activate = FB_ACTIVATE_NOW;
  479. var->height = -1;
  480. var->width = -1;
  481. var->accel_flags = 0;
  482. return 0;
  483. }
  484. #undef FAIL
  485. static int vga16fb_set_par(struct fb_info *info)
  486. {
  487. struct vga16fb_par *par = info->par;
  488. u8 gdc[VGA_GFX_C];
  489. u8 seq[VGA_SEQ_C];
  490. u8 atc[VGA_ATT_C];
  491. int fh, i;
  492. seq[VGA_SEQ_CLOCK_MODE] = 0x01 | par->clkdiv;
  493. if (par->mode & MODE_TEXT)
  494. seq[VGA_SEQ_PLANE_WRITE] = 0x03;
  495. else
  496. seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
  497. seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
  498. if (par->mode & MODE_TEXT)
  499. seq[VGA_SEQ_MEMORY_MODE] = 0x03;
  500. else if (par->mode & MODE_SKIP4)
  501. seq[VGA_SEQ_MEMORY_MODE] = 0x0E;
  502. else
  503. seq[VGA_SEQ_MEMORY_MODE] = 0x06;
  504. gdc[VGA_GFX_SR_VALUE] = 0x00;
  505. gdc[VGA_GFX_SR_ENABLE] = 0x00;
  506. gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
  507. gdc[VGA_GFX_DATA_ROTATE] = 0x00;
  508. gdc[VGA_GFX_PLANE_READ] = 0;
  509. if (par->mode & MODE_TEXT) {
  510. gdc[VGA_GFX_MODE] = 0x10;
  511. gdc[VGA_GFX_MISC] = 0x06;
  512. } else {
  513. if (par->mode & MODE_CFB)
  514. gdc[VGA_GFX_MODE] = 0x40;
  515. else
  516. gdc[VGA_GFX_MODE] = 0x00;
  517. gdc[VGA_GFX_MISC] = 0x05;
  518. }
  519. gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
  520. gdc[VGA_GFX_BIT_MASK] = 0xFF;
  521. for (i = 0x00; i < 0x10; i++)
  522. atc[i] = i;
  523. if (par->mode & MODE_TEXT)
  524. atc[VGA_ATC_MODE] = 0x04;
  525. else if (par->mode & MODE_8BPP)
  526. atc[VGA_ATC_MODE] = 0x41;
  527. else
  528. atc[VGA_ATC_MODE] = 0x81;
  529. atc[VGA_ATC_OVERSCAN] = 0x00; /* 0 for EGA, 0xFF for VGA */
  530. atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
  531. if (par->mode & MODE_8BPP)
  532. atc[VGA_ATC_PEL] = (info->var.xoffset & 3) << 1;
  533. else
  534. atc[VGA_ATC_PEL] = info->var.xoffset & 7;
  535. atc[VGA_ATC_COLOR_PAGE] = 0x00;
  536. if (par->mode & MODE_TEXT) {
  537. fh = 16; // FIXME !!! Fudge font height.
  538. par->crtc[VGA_CRTC_MAX_SCAN] = (par->crtc[VGA_CRTC_MAX_SCAN]
  539. & ~0x1F) | (fh - 1);
  540. }
  541. vga_io_w(VGA_MIS_W, vga_io_r(VGA_MIS_R) | 0x01);
  542. /* Enable graphics register modification */
  543. if (!par->isVGA) {
  544. vga_io_w(EGA_GFX_E0, 0x00);
  545. vga_io_w(EGA_GFX_E1, 0x01);
  546. }
  547. /* update misc output register */
  548. vga_io_w(VGA_MIS_W, par->misc);
  549. /* synchronous reset on */
  550. vga_io_wseq(0x00, 0x01);
  551. if (par->isVGA)
  552. vga_io_w(VGA_PEL_MSK, par->pel_msk);
  553. /* write sequencer registers */
  554. vga_io_wseq(VGA_SEQ_CLOCK_MODE, seq[VGA_SEQ_CLOCK_MODE] | 0x20);
  555. for (i = 2; i < VGA_SEQ_C; i++) {
  556. vga_io_wseq(i, seq[i]);
  557. }
  558. /* synchronous reset off */
  559. vga_io_wseq(0x00, 0x03);
  560. /* deprotect CRT registers 0-7 */
  561. vga_io_wcrt(VGA_CRTC_V_SYNC_END, par->crtc[VGA_CRTC_V_SYNC_END]);
  562. /* write CRT registers */
  563. for (i = 0; i < VGA_CRTC_REGS; i++) {
  564. vga_io_wcrt(i, par->crtc[i]);
  565. }
  566. /* write graphics controller registers */
  567. for (i = 0; i < VGA_GFX_C; i++) {
  568. vga_io_wgfx(i, gdc[i]);
  569. }
  570. /* write attribute controller registers */
  571. for (i = 0; i < VGA_ATT_C; i++) {
  572. vga_io_r(VGA_IS1_RC); /* reset flip-flop */
  573. vga_io_wattr(i, atc[i]);
  574. }
  575. /* Wait for screen to stabilize. */
  576. mdelay(50);
  577. vga_io_wseq(VGA_SEQ_CLOCK_MODE, seq[VGA_SEQ_CLOCK_MODE]);
  578. vga_io_r(VGA_IS1_RC);
  579. vga_io_w(VGA_ATT_IW, 0x20);
  580. vga16fb_update_fix(info);
  581. return 0;
  582. }
  583. static void ega16_setpalette(int regno, unsigned red, unsigned green, unsigned blue)
  584. {
  585. static const unsigned char map[] = { 000, 001, 010, 011 };
  586. int val;
  587. if (regno >= 16)
  588. return;
  589. val = map[red>>14] | ((map[green>>14]) << 1) | ((map[blue>>14]) << 2);
  590. vga_io_r(VGA_IS1_RC); /* ! 0x3BA */
  591. vga_io_wattr(regno, val);
  592. vga_io_r(VGA_IS1_RC); /* some clones need it */
  593. vga_io_w(VGA_ATT_IW, 0x20); /* unblank screen */
  594. }
  595. static void vga16_setpalette(int regno, unsigned red, unsigned green, unsigned blue)
  596. {
  597. outb(regno, dac_reg);
  598. outb(red >> 10, dac_val);
  599. outb(green >> 10, dac_val);
  600. outb(blue >> 10, dac_val);
  601. }
  602. static int vga16fb_setcolreg(unsigned regno, unsigned red, unsigned green,
  603. unsigned blue, unsigned transp,
  604. struct fb_info *info)
  605. {
  606. struct vga16fb_par *par = info->par;
  607. int gray;
  608. /*
  609. * Set a single color register. The values supplied are
  610. * already rounded down to the hardware's capabilities
  611. * (according to the entries in the `var' structure). Return
  612. * != 0 for invalid regno.
  613. */
  614. if (regno >= 256)
  615. return 1;
  616. gray = info->var.grayscale;
  617. if (gray) {
  618. /* gray = 0.30*R + 0.59*G + 0.11*B */
  619. red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
  620. }
  621. if (par->isVGA)
  622. vga16_setpalette(regno,red,green,blue);
  623. else
  624. ega16_setpalette(regno,red,green,blue);
  625. return 0;
  626. }
  627. static int vga16fb_pan_display(struct fb_var_screeninfo *var,
  628. struct fb_info *info)
  629. {
  630. vga16fb_pan_var(info, var);
  631. return 0;
  632. }
  633. /* The following VESA blanking code is taken from vgacon.c. The VGA
  634. blanking code was originally by Huang shi chao, and modified by
  635. Christoph Rimek (chrimek@toppoint.de) and todd j. derr
  636. (tjd@barefoot.org) for Linux. */
  637. #define attrib_port VGA_ATC_IW
  638. #define seq_port_reg VGA_SEQ_I
  639. #define seq_port_val VGA_SEQ_D
  640. #define gr_port_reg VGA_GFX_I
  641. #define gr_port_val VGA_GFX_D
  642. #define video_misc_rd VGA_MIS_R
  643. #define video_misc_wr VGA_MIS_W
  644. #define vga_video_port_reg VGA_CRT_IC
  645. #define vga_video_port_val VGA_CRT_DC
  646. static void vga_vesa_blank(struct vga16fb_par *par, int mode)
  647. {
  648. unsigned char SeqCtrlIndex;
  649. unsigned char CrtCtrlIndex;
  650. //cli();
  651. SeqCtrlIndex = vga_io_r(seq_port_reg);
  652. CrtCtrlIndex = vga_io_r(vga_video_port_reg);
  653. /* save original values of VGA controller registers */
  654. if(!par->vesa_blanked) {
  655. par->vga_state.CrtMiscIO = vga_io_r(video_misc_rd);
  656. //sti();
  657. par->vga_state.HorizontalTotal = vga_io_rcrt(0x00); /* HorizontalTotal */
  658. par->vga_state.HorizDisplayEnd = vga_io_rcrt(0x01); /* HorizDisplayEnd */
  659. par->vga_state.StartHorizRetrace = vga_io_rcrt(0x04); /* StartHorizRetrace */
  660. par->vga_state.EndHorizRetrace = vga_io_rcrt(0x05); /* EndHorizRetrace */
  661. par->vga_state.Overflow = vga_io_rcrt(0x07); /* Overflow */
  662. par->vga_state.StartVertRetrace = vga_io_rcrt(0x10); /* StartVertRetrace */
  663. par->vga_state.EndVertRetrace = vga_io_rcrt(0x11); /* EndVertRetrace */
  664. par->vga_state.ModeControl = vga_io_rcrt(0x17); /* ModeControl */
  665. par->vga_state.ClockingMode = vga_io_rseq(0x01); /* ClockingMode */
  666. }
  667. /* assure that video is enabled */
  668. /* "0x20" is VIDEO_ENABLE_bit in register 01 of sequencer */
  669. //cli();
  670. vga_io_wseq(0x01, par->vga_state.ClockingMode | 0x20);
  671. /* test for vertical retrace in process.... */
  672. if ((par->vga_state.CrtMiscIO & 0x80) == 0x80)
  673. vga_io_w(video_misc_wr, par->vga_state.CrtMiscIO & 0xef);
  674. /*
  675. * Set <End of vertical retrace> to minimum (0) and
  676. * <Start of vertical Retrace> to maximum (incl. overflow)
  677. * Result: turn off vertical sync (VSync) pulse.
  678. */
  679. if (mode & FB_BLANK_VSYNC_SUSPEND) {
  680. outb_p(0x10,vga_video_port_reg); /* StartVertRetrace */
  681. outb_p(0xff,vga_video_port_val); /* maximum value */
  682. outb_p(0x11,vga_video_port_reg); /* EndVertRetrace */
  683. outb_p(0x40,vga_video_port_val); /* minimum (bits 0..3) */
  684. outb_p(0x07,vga_video_port_reg); /* Overflow */
  685. outb_p(par->vga_state.Overflow | 0x84,vga_video_port_val); /* bits 9,10 of vert. retrace */
  686. }
  687. if (mode & FB_BLANK_HSYNC_SUSPEND) {
  688. /*
  689. * Set <End of horizontal retrace> to minimum (0) and
  690. * <Start of horizontal Retrace> to maximum
  691. * Result: turn off horizontal sync (HSync) pulse.
  692. */
  693. outb_p(0x04,vga_video_port_reg); /* StartHorizRetrace */
  694. outb_p(0xff,vga_video_port_val); /* maximum */
  695. outb_p(0x05,vga_video_port_reg); /* EndHorizRetrace */
  696. outb_p(0x00,vga_video_port_val); /* minimum (0) */
  697. }
  698. /* restore both index registers */
  699. outb_p(SeqCtrlIndex,seq_port_reg);
  700. outb_p(CrtCtrlIndex,vga_video_port_reg);
  701. //sti();
  702. }
  703. static void vga_vesa_unblank(struct vga16fb_par *par)
  704. {
  705. unsigned char SeqCtrlIndex;
  706. unsigned char CrtCtrlIndex;
  707. //cli();
  708. SeqCtrlIndex = vga_io_r(seq_port_reg);
  709. CrtCtrlIndex = vga_io_r(vga_video_port_reg);
  710. /* restore original values of VGA controller registers */
  711. vga_io_w(video_misc_wr, par->vga_state.CrtMiscIO);
  712. /* HorizontalTotal */
  713. vga_io_wcrt(0x00, par->vga_state.HorizontalTotal);
  714. /* HorizDisplayEnd */
  715. vga_io_wcrt(0x01, par->vga_state.HorizDisplayEnd);
  716. /* StartHorizRetrace */
  717. vga_io_wcrt(0x04, par->vga_state.StartHorizRetrace);
  718. /* EndHorizRetrace */
  719. vga_io_wcrt(0x05, par->vga_state.EndHorizRetrace);
  720. /* Overflow */
  721. vga_io_wcrt(0x07, par->vga_state.Overflow);
  722. /* StartVertRetrace */
  723. vga_io_wcrt(0x10, par->vga_state.StartVertRetrace);
  724. /* EndVertRetrace */
  725. vga_io_wcrt(0x11, par->vga_state.EndVertRetrace);
  726. /* ModeControl */
  727. vga_io_wcrt(0x17, par->vga_state.ModeControl);
  728. /* ClockingMode */
  729. vga_io_wseq(0x01, par->vga_state.ClockingMode);
  730. /* restore index/control registers */
  731. vga_io_w(seq_port_reg, SeqCtrlIndex);
  732. vga_io_w(vga_video_port_reg, CrtCtrlIndex);
  733. //sti();
  734. }
  735. static void vga_pal_blank(void)
  736. {
  737. int i;
  738. for (i=0; i<16; i++) {
  739. outb_p (i, dac_reg) ;
  740. outb_p (0, dac_val) ;
  741. outb_p (0, dac_val) ;
  742. outb_p (0, dac_val) ;
  743. }
  744. }
  745. /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
  746. static int vga16fb_blank(int blank, struct fb_info *info)
  747. {
  748. struct vga16fb_par *par = info->par;
  749. switch (blank) {
  750. case FB_BLANK_UNBLANK: /* Unblank */
  751. if (par->vesa_blanked) {
  752. vga_vesa_unblank(par);
  753. par->vesa_blanked = 0;
  754. }
  755. if (par->palette_blanked) {
  756. par->palette_blanked = 0;
  757. }
  758. break;
  759. case FB_BLANK_NORMAL: /* blank */
  760. vga_pal_blank();
  761. par->palette_blanked = 1;
  762. break;
  763. default: /* VESA blanking */
  764. vga_vesa_blank(par, blank);
  765. par->vesa_blanked = 1;
  766. break;
  767. }
  768. return 0;
  769. }
  770. static void vga_8planes_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  771. {
  772. u32 dx = rect->dx, width = rect->width;
  773. char oldindex = getindex();
  774. char oldmode = setmode(0x40);
  775. char oldmask = selectmask();
  776. int line_ofs, height;
  777. char oldop, oldsr;
  778. char __iomem *where;
  779. dx /= 4;
  780. where = info->screen_base + dx + rect->dy * info->fix.line_length;
  781. if (rect->rop == ROP_COPY) {
  782. oldop = setop(0);
  783. oldsr = setsr(0);
  784. width /= 4;
  785. line_ofs = info->fix.line_length - width;
  786. setmask(0xff);
  787. height = rect->height;
  788. while (height--) {
  789. int x;
  790. /* we can do memset... */
  791. for (x = width; x > 0; --x) {
  792. writeb(rect->color, where);
  793. where++;
  794. }
  795. where += line_ofs;
  796. }
  797. } else {
  798. char oldcolor = setcolor(0xf);
  799. int y;
  800. oldop = setop(0x18);
  801. oldsr = setsr(0xf);
  802. setmask(0x0F);
  803. for (y = 0; y < rect->height; y++) {
  804. rmw(where);
  805. rmw(where+1);
  806. where += info->fix.line_length;
  807. }
  808. setcolor(oldcolor);
  809. }
  810. setmask(oldmask);
  811. setsr(oldsr);
  812. setop(oldop);
  813. setmode(oldmode);
  814. setindex(oldindex);
  815. }
  816. static void vga16fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  817. {
  818. int x, x2, y2, vxres, vyres, width, height, line_ofs;
  819. char __iomem *dst;
  820. vxres = info->var.xres_virtual;
  821. vyres = info->var.yres_virtual;
  822. if (!rect->width || !rect->height || rect->dx > vxres || rect->dy > vyres)
  823. return;
  824. /* We could use hardware clipping but on many cards you get around
  825. * hardware clipping by writing to framebuffer directly. */
  826. x2 = rect->dx + rect->width;
  827. y2 = rect->dy + rect->height;
  828. x2 = x2 < vxres ? x2 : vxres;
  829. y2 = y2 < vyres ? y2 : vyres;
  830. width = x2 - rect->dx;
  831. switch (info->fix.type) {
  832. case FB_TYPE_VGA_PLANES:
  833. if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
  834. height = y2 - rect->dy;
  835. width = rect->width/8;
  836. line_ofs = info->fix.line_length - width;
  837. dst = info->screen_base + (rect->dx/8) + rect->dy * info->fix.line_length;
  838. switch (rect->rop) {
  839. case ROP_COPY:
  840. setmode(0);
  841. setop(0);
  842. setsr(0xf);
  843. setcolor(rect->color);
  844. selectmask();
  845. setmask(0xff);
  846. while (height--) {
  847. for (x = 0; x < width; x++) {
  848. writeb(0, dst);
  849. dst++;
  850. }
  851. dst += line_ofs;
  852. }
  853. break;
  854. case ROP_XOR:
  855. setmode(0);
  856. setop(0x18);
  857. setsr(0xf);
  858. setcolor(0xf);
  859. selectmask();
  860. setmask(0xff);
  861. while (height--) {
  862. for (x = 0; x < width; x++) {
  863. rmw(dst);
  864. dst++;
  865. }
  866. dst += line_ofs;
  867. }
  868. break;
  869. }
  870. } else
  871. vga_8planes_fillrect(info, rect);
  872. break;
  873. case FB_TYPE_PACKED_PIXELS:
  874. default:
  875. cfb_fillrect(info, rect);
  876. break;
  877. }
  878. }
  879. static void vga_8planes_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  880. {
  881. char oldindex = getindex();
  882. char oldmode = setmode(0x41);
  883. char oldop = setop(0);
  884. char oldsr = setsr(0xf);
  885. int height, line_ofs, x;
  886. u32 sx, dx, width;
  887. char __iomem *dest;
  888. char __iomem *src;
  889. height = area->height;
  890. sx = area->sx / 4;
  891. dx = area->dx / 4;
  892. width = area->width / 4;
  893. if (area->dy < area->sy || (area->dy == area->sy && dx < sx)) {
  894. line_ofs = info->fix.line_length - width;
  895. dest = info->screen_base + dx + area->dy * info->fix.line_length;
  896. src = info->screen_base + sx + area->sy * info->fix.line_length;
  897. while (height--) {
  898. for (x = 0; x < width; x++) {
  899. readb(src);
  900. writeb(0, dest);
  901. src++;
  902. dest++;
  903. }
  904. src += line_ofs;
  905. dest += line_ofs;
  906. }
  907. } else {
  908. line_ofs = info->fix.line_length - width;
  909. dest = info->screen_base + dx + width +
  910. (area->dy + height - 1) * info->fix.line_length;
  911. src = info->screen_base + sx + width +
  912. (area->sy + height - 1) * info->fix.line_length;
  913. while (height--) {
  914. for (x = 0; x < width; x++) {
  915. --src;
  916. --dest;
  917. readb(src);
  918. writeb(0, dest);
  919. }
  920. src -= line_ofs;
  921. dest -= line_ofs;
  922. }
  923. }
  924. setsr(oldsr);
  925. setop(oldop);
  926. setmode(oldmode);
  927. setindex(oldindex);
  928. }
  929. static void vga16fb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  930. {
  931. u32 dx = area->dx, dy = area->dy, sx = area->sx, sy = area->sy;
  932. int x, x2, y2, old_dx, old_dy, vxres, vyres;
  933. int height, width, line_ofs;
  934. char __iomem *dst = NULL;
  935. char __iomem *src = NULL;
  936. vxres = info->var.xres_virtual;
  937. vyres = info->var.yres_virtual;
  938. if (area->dx > vxres || area->sx > vxres || area->dy > vyres ||
  939. area->sy > vyres)
  940. return;
  941. /* clip the destination */
  942. old_dx = area->dx;
  943. old_dy = area->dy;
  944. /*
  945. * We could use hardware clipping but on many cards you get around
  946. * hardware clipping by writing to framebuffer directly.
  947. */
  948. x2 = area->dx + area->width;
  949. y2 = area->dy + area->height;
  950. dx = area->dx > 0 ? area->dx : 0;
  951. dy = area->dy > 0 ? area->dy : 0;
  952. x2 = x2 < vxres ? x2 : vxres;
  953. y2 = y2 < vyres ? y2 : vyres;
  954. width = x2 - dx;
  955. height = y2 - dy;
  956. /* update sx1,sy1 */
  957. sx += (dx - old_dx);
  958. sy += (dy - old_dy);
  959. /* the source must be completely inside the virtual screen */
  960. if (sx < 0 || sy < 0 || (sx + width) > vxres || (sy + height) > vyres)
  961. return;
  962. switch (info->fix.type) {
  963. case FB_TYPE_VGA_PLANES:
  964. if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
  965. width = width/8;
  966. height = height;
  967. line_ofs = info->fix.line_length - width;
  968. setmode(1);
  969. setop(0);
  970. setsr(0xf);
  971. if (dy < sy || (dy == sy && dx < sx)) {
  972. dst = info->screen_base + (dx/8) + dy * info->fix.line_length;
  973. src = info->screen_base + (sx/8) + sy * info->fix.line_length;
  974. while (height--) {
  975. for (x = 0; x < width; x++) {
  976. readb(src);
  977. writeb(0, dst);
  978. dst++;
  979. src++;
  980. }
  981. src += line_ofs;
  982. dst += line_ofs;
  983. }
  984. } else {
  985. dst = info->screen_base + (dx/8) + width +
  986. (dy + height - 1) * info->fix.line_length;
  987. src = info->screen_base + (sx/8) + width +
  988. (sy + height - 1) * info->fix.line_length;
  989. while (height--) {
  990. for (x = 0; x < width; x++) {
  991. dst--;
  992. src--;
  993. readb(src);
  994. writeb(0, dst);
  995. }
  996. src -= line_ofs;
  997. dst -= line_ofs;
  998. }
  999. }
  1000. } else
  1001. vga_8planes_copyarea(info, area);
  1002. break;
  1003. case FB_TYPE_PACKED_PIXELS:
  1004. default:
  1005. cfb_copyarea(info, area);
  1006. break;
  1007. }
  1008. }
  1009. #define TRANS_MASK_LOW {0x0,0x8,0x4,0xC,0x2,0xA,0x6,0xE,0x1,0x9,0x5,0xD,0x3,0xB,0x7,0xF}
  1010. #define TRANS_MASK_HIGH {0x000, 0x800, 0x400, 0xC00, 0x200, 0xA00, 0x600, 0xE00, \
  1011. 0x100, 0x900, 0x500, 0xD00, 0x300, 0xB00, 0x700, 0xF00}
  1012. #if defined(__LITTLE_ENDIAN)
  1013. static const u16 transl_l[] = TRANS_MASK_LOW;
  1014. static const u16 transl_h[] = TRANS_MASK_HIGH;
  1015. #elif defined(__BIG_ENDIAN)
  1016. static const u16 transl_l[] = TRANS_MASK_HIGH;
  1017. static const u16 transl_h[] = TRANS_MASK_LOW;
  1018. #else
  1019. #error "Only __BIG_ENDIAN and __LITTLE_ENDIAN are supported in vga-planes"
  1020. #endif
  1021. static void vga_8planes_imageblit(struct fb_info *info, const struct fb_image *image)
  1022. {
  1023. char oldindex = getindex();
  1024. char oldmode = setmode(0x40);
  1025. char oldop = setop(0);
  1026. char oldsr = setsr(0);
  1027. char oldmask = selectmask();
  1028. const char *cdat = image->data;
  1029. u32 dx = image->dx;
  1030. char __iomem *where;
  1031. int y;
  1032. dx /= 4;
  1033. where = info->screen_base + dx + image->dy * info->fix.line_length;
  1034. setmask(0xff);
  1035. writeb(image->bg_color, where);
  1036. readb(where);
  1037. selectmask();
  1038. setmask(image->fg_color ^ image->bg_color);
  1039. setmode(0x42);
  1040. setop(0x18);
  1041. for (y = 0; y < image->height; y++, where += info->fix.line_length)
  1042. writew(transl_h[cdat[y]&0xF] | transl_l[cdat[y] >> 4], where);
  1043. setmask(oldmask);
  1044. setsr(oldsr);
  1045. setop(oldop);
  1046. setmode(oldmode);
  1047. setindex(oldindex);
  1048. }
  1049. static void vga_imageblit_expand(struct fb_info *info, const struct fb_image *image)
  1050. {
  1051. char __iomem *where = info->screen_base + (image->dx/8) +
  1052. image->dy * info->fix.line_length;
  1053. struct vga16fb_par *par = info->par;
  1054. char *cdat = (char *) image->data;
  1055. char __iomem *dst;
  1056. int x, y;
  1057. switch (info->fix.type) {
  1058. case FB_TYPE_VGA_PLANES:
  1059. if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4) {
  1060. if (par->isVGA) {
  1061. setmode(2);
  1062. setop(0);
  1063. setsr(0xf);
  1064. setcolor(image->fg_color);
  1065. selectmask();
  1066. setmask(0xff);
  1067. writeb(image->bg_color, where);
  1068. rmb();
  1069. readb(where); /* fill latches */
  1070. setmode(3);
  1071. wmb();
  1072. for (y = 0; y < image->height; y++) {
  1073. dst = where;
  1074. for (x = image->width/8; x--;)
  1075. writeb(*cdat++, dst++);
  1076. where += info->fix.line_length;
  1077. }
  1078. wmb();
  1079. } else {
  1080. setmode(0);
  1081. setop(0);
  1082. setsr(0xf);
  1083. setcolor(image->bg_color);
  1084. selectmask();
  1085. setmask(0xff);
  1086. for (y = 0; y < image->height; y++) {
  1087. dst = where;
  1088. for (x=image->width/8; x--;){
  1089. rmw(dst);
  1090. setcolor(image->fg_color);
  1091. selectmask();
  1092. if (*cdat) {
  1093. setmask(*cdat++);
  1094. rmw(dst++);
  1095. }
  1096. }
  1097. where += info->fix.line_length;
  1098. }
  1099. }
  1100. } else
  1101. vga_8planes_imageblit(info, image);
  1102. break;
  1103. case FB_TYPE_PACKED_PIXELS:
  1104. default:
  1105. cfb_imageblit(info, image);
  1106. break;
  1107. }
  1108. }
  1109. static void vga_imageblit_color(struct fb_info *info, const struct fb_image *image)
  1110. {
  1111. /*
  1112. * Draw logo
  1113. */
  1114. struct vga16fb_par *par = info->par;
  1115. char __iomem *where =
  1116. info->screen_base + image->dy * info->fix.line_length +
  1117. image->dx/8;
  1118. const char *cdat = image->data;
  1119. char __iomem *dst;
  1120. int x, y;
  1121. switch (info->fix.type) {
  1122. case FB_TYPE_VGA_PLANES:
  1123. if (info->fix.type_aux == FB_AUX_VGA_PLANES_VGA4 &&
  1124. par->isVGA) {
  1125. setsr(0xf);
  1126. setop(0);
  1127. setmode(0);
  1128. for (y = 0; y < image->height; y++) {
  1129. for (x = 0; x < image->width; x++) {
  1130. dst = where + x/8;
  1131. setcolor(*cdat);
  1132. selectmask();
  1133. setmask(1 << (7 - (x % 8)));
  1134. fb_readb(dst);
  1135. fb_writeb(0, dst);
  1136. cdat++;
  1137. }
  1138. where += info->fix.line_length;
  1139. }
  1140. }
  1141. break;
  1142. case FB_TYPE_PACKED_PIXELS:
  1143. cfb_imageblit(info, image);
  1144. break;
  1145. default:
  1146. break;
  1147. }
  1148. }
  1149. static void vga16fb_imageblit(struct fb_info *info, const struct fb_image *image)
  1150. {
  1151. if (image->depth == 1)
  1152. vga_imageblit_expand(info, image);
  1153. else
  1154. vga_imageblit_color(info, image);
  1155. }
  1156. static struct fb_ops vga16fb_ops = {
  1157. .owner = THIS_MODULE,
  1158. .fb_open = vga16fb_open,
  1159. .fb_release = vga16fb_release,
  1160. .fb_check_var = vga16fb_check_var,
  1161. .fb_set_par = vga16fb_set_par,
  1162. .fb_setcolreg = vga16fb_setcolreg,
  1163. .fb_pan_display = vga16fb_pan_display,
  1164. .fb_blank = vga16fb_blank,
  1165. .fb_fillrect = vga16fb_fillrect,
  1166. .fb_copyarea = vga16fb_copyarea,
  1167. .fb_imageblit = vga16fb_imageblit,
  1168. };
  1169. #ifndef MODULE
  1170. static int vga16fb_setup(char *options)
  1171. {
  1172. char *this_opt;
  1173. if (!options || !*options)
  1174. return 0;
  1175. while ((this_opt = strsep(&options, ",")) != NULL) {
  1176. if (!*this_opt) continue;
  1177. }
  1178. return 0;
  1179. }
  1180. #endif
  1181. static int __init vga16fb_probe(struct platform_device *dev)
  1182. {
  1183. struct fb_info *info;
  1184. struct vga16fb_par *par;
  1185. int i;
  1186. int ret = 0;
  1187. printk(KERN_DEBUG "vga16fb: initializing\n");
  1188. info = framebuffer_alloc(sizeof(struct vga16fb_par), &dev->dev);
  1189. if (!info) {
  1190. ret = -ENOMEM;
  1191. goto err_fb_alloc;
  1192. }
  1193. /* XXX share VGA_FB_PHYS and I/O region with vgacon and others */
  1194. info->screen_base = (void __iomem *)VGA_MAP_MEM(VGA_FB_PHYS, 0);
  1195. if (!info->screen_base) {
  1196. printk(KERN_ERR "vga16fb: unable to map device\n");
  1197. ret = -ENOMEM;
  1198. goto err_ioremap;
  1199. }
  1200. printk(KERN_INFO "vga16fb: mapped to 0x%p\n", info->screen_base);
  1201. par = info->par;
  1202. mutex_init(&par->open_lock);
  1203. par->isVGA = ORIG_VIDEO_ISVGA;
  1204. par->palette_blanked = 0;
  1205. par->vesa_blanked = 0;
  1206. i = par->isVGA? 6 : 2;
  1207. vga16fb_defined.red.length = i;
  1208. vga16fb_defined.green.length = i;
  1209. vga16fb_defined.blue.length = i;
  1210. /* name should not depend on EGA/VGA */
  1211. info->fbops = &vga16fb_ops;
  1212. info->var = vga16fb_defined;
  1213. info->fix = vga16fb_fix;
  1214. info->flags = FBINFO_FLAG_DEFAULT |
  1215. FBINFO_HWACCEL_YPAN;
  1216. i = (info->var.bits_per_pixel == 8) ? 256 : 16;
  1217. ret = fb_alloc_cmap(&info->cmap, i, 0);
  1218. if (ret) {
  1219. printk(KERN_ERR "vga16fb: unable to allocate colormap\n");
  1220. ret = -ENOMEM;
  1221. goto err_alloc_cmap;
  1222. }
  1223. if (vga16fb_check_var(&info->var, info)) {
  1224. printk(KERN_ERR "vga16fb: unable to validate variable\n");
  1225. ret = -EINVAL;
  1226. goto err_check_var;
  1227. }
  1228. vga16fb_update_fix(info);
  1229. if (register_framebuffer(info) < 0) {
  1230. printk(KERN_ERR "vga16fb: unable to register framebuffer\n");
  1231. ret = -EINVAL;
  1232. goto err_check_var;
  1233. }
  1234. printk(KERN_INFO "fb%d: %s frame buffer device\n",
  1235. info->node, info->fix.id);
  1236. platform_set_drvdata(dev, info);
  1237. return 0;
  1238. err_check_var:
  1239. fb_dealloc_cmap(&info->cmap);
  1240. err_alloc_cmap:
  1241. iounmap(info->screen_base);
  1242. err_ioremap:
  1243. framebuffer_release(info);
  1244. err_fb_alloc:
  1245. return ret;
  1246. }
  1247. static int vga16fb_remove(struct platform_device *dev)
  1248. {
  1249. struct fb_info *info = platform_get_drvdata(dev);
  1250. if (info) {
  1251. unregister_framebuffer(info);
  1252. iounmap(info->screen_base);
  1253. fb_dealloc_cmap(&info->cmap);
  1254. /* XXX unshare VGA regions */
  1255. framebuffer_release(info);
  1256. }
  1257. return 0;
  1258. }
  1259. static struct platform_driver vga16fb_driver = {
  1260. .probe = vga16fb_probe,
  1261. .remove = vga16fb_remove,
  1262. .driver = {
  1263. .name = "vga16fb",
  1264. },
  1265. };
  1266. static struct platform_device *vga16fb_device;
  1267. static int __init vga16fb_init(void)
  1268. {
  1269. int ret;
  1270. #ifndef MODULE
  1271. char *option = NULL;
  1272. if (fb_get_options("vga16fb", &option))
  1273. return -ENODEV;
  1274. vga16fb_setup(option);
  1275. #endif
  1276. ret = platform_driver_register(&vga16fb_driver);
  1277. if (!ret) {
  1278. vga16fb_device = platform_device_alloc("vga16fb", 0);
  1279. if (vga16fb_device)
  1280. ret = platform_device_add(vga16fb_device);
  1281. else
  1282. ret = -ENOMEM;
  1283. if (ret) {
  1284. platform_device_put(vga16fb_device);
  1285. platform_driver_unregister(&vga16fb_driver);
  1286. }
  1287. }
  1288. return ret;
  1289. }
  1290. static void __exit vga16fb_exit(void)
  1291. {
  1292. platform_device_unregister(vga16fb_device);
  1293. platform_driver_unregister(&vga16fb_driver);
  1294. }
  1295. MODULE_LICENSE("GPL");
  1296. module_init(vga16fb_init);
  1297. module_exit(vga16fb_exit);
  1298. /*
  1299. * Overrides for Emacs so that we follow Linus's tabbing style.
  1300. * ---------------------------------------------------------------------------
  1301. * Local variables:
  1302. * c-basic-offset: 8
  1303. * End:
  1304. */