tridentfb.c 31 KB

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  1. /*
  2. * Frame buffer driver for Trident Blade and Image series
  3. *
  4. * Copyright 2001,2002 - Jani Monoses <jani@iv.ro>
  5. *
  6. *
  7. * CREDITS:(in order of appearance)
  8. * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
  9. * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
  10. * much inspired by the XFree86 4.x Trident driver sources by Alan Hourihane
  11. * the FreeVGA project
  12. * Francesco Salvestrini <salvestrini@users.sf.net> XP support,code,suggestions
  13. * TODO:
  14. * timing value tweaking so it looks good on every monitor in every mode
  15. * TGUI acceleration
  16. */
  17. #include <linux/module.h>
  18. #include <linux/fb.h>
  19. #include <linux/init.h>
  20. #include <linux/pci.h>
  21. #include <linux/delay.h>
  22. #include <video/trident.h>
  23. #define VERSION "0.7.8-NEWAPI"
  24. struct tridentfb_par {
  25. int vclk; //in MHz
  26. void __iomem * io_virt; //iospace virtual memory address
  27. };
  28. static unsigned char eng_oper; //engine operation...
  29. static struct fb_ops tridentfb_ops;
  30. static struct tridentfb_par default_par;
  31. /* FIXME:kmalloc these 3 instead */
  32. static struct fb_info fb_info;
  33. static u32 pseudo_pal[16];
  34. static struct fb_var_screeninfo default_var;
  35. static struct fb_fix_screeninfo tridentfb_fix = {
  36. .id = "Trident",
  37. .type = FB_TYPE_PACKED_PIXELS,
  38. .ypanstep = 1,
  39. .visual = FB_VISUAL_PSEUDOCOLOR,
  40. .accel = FB_ACCEL_NONE,
  41. };
  42. static int chip_id;
  43. static int defaultaccel;
  44. static int displaytype;
  45. /* defaults which are normally overriden by user values */
  46. /* video mode */
  47. static char * mode = "640x480";
  48. static int bpp = 8;
  49. static int noaccel;
  50. static int center;
  51. static int stretch;
  52. static int fp;
  53. static int crt;
  54. static int memsize;
  55. static int memdiff;
  56. static int nativex;
  57. module_param(mode, charp, 0);
  58. module_param(bpp, int, 0);
  59. module_param(center, int, 0);
  60. module_param(stretch, int, 0);
  61. module_param(noaccel, int, 0);
  62. module_param(memsize, int, 0);
  63. module_param(memdiff, int, 0);
  64. module_param(nativex, int, 0);
  65. module_param(fp, int, 0);
  66. module_param(crt, int, 0);
  67. static int chip3D;
  68. static int chipcyber;
  69. static int is3Dchip(int id)
  70. {
  71. return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
  72. (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
  73. (id == CYBER9397) || (id == CYBER9397DVD) ||
  74. (id == CYBER9520) || (id == CYBER9525DVD) ||
  75. (id == IMAGE975) || (id == IMAGE985) ||
  76. (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
  77. (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
  78. (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
  79. (id == CYBERBLADEXPAi1));
  80. }
  81. static int iscyber(int id)
  82. {
  83. switch (id) {
  84. case CYBER9388:
  85. case CYBER9382:
  86. case CYBER9385:
  87. case CYBER9397:
  88. case CYBER9397DVD:
  89. case CYBER9520:
  90. case CYBER9525DVD:
  91. case CYBERBLADEE4:
  92. case CYBERBLADEi7D:
  93. case CYBERBLADEi1:
  94. case CYBERBLADEi1D:
  95. case CYBERBLADEAi1:
  96. case CYBERBLADEAi1D:
  97. case CYBERBLADEXPAi1:
  98. return 1;
  99. case CYBER9320:
  100. case TGUI9660:
  101. case IMAGE975:
  102. case IMAGE985:
  103. case BLADE3D:
  104. case CYBERBLADEi7: /* VIA MPV4 integrated version */
  105. default:
  106. /* case CYBERBLDAEXPm8: Strange */
  107. /* case CYBERBLDAEXPm16: Strange */
  108. return 0;
  109. }
  110. }
  111. #define CRT 0x3D0 //CRTC registers offset for color display
  112. #ifndef TRIDENT_MMIO
  113. #define TRIDENT_MMIO 1
  114. #endif
  115. #if TRIDENT_MMIO
  116. #define t_outb(val,reg) writeb(val,((struct tridentfb_par *)(fb_info.par))->io_virt + reg)
  117. #define t_inb(reg) readb(((struct tridentfb_par*)(fb_info.par))->io_virt + reg)
  118. #else
  119. #define t_outb(val,reg) outb(val,reg)
  120. #define t_inb(reg) inb(reg)
  121. #endif
  122. static struct accel_switch {
  123. void (*init_accel)(int,int);
  124. void (*wait_engine)(void);
  125. void (*fill_rect)(__u32,__u32,__u32,__u32,__u32,__u32);
  126. void (*copy_rect)(__u32,__u32,__u32,__u32,__u32,__u32);
  127. } *acc;
  128. #define writemmr(r,v) writel(v, ((struct tridentfb_par *)fb_info.par)->io_virt + r)
  129. #define readmmr(r) readl(((struct tridentfb_par *)fb_info.par)->io_virt + r)
  130. /*
  131. * Blade specific acceleration.
  132. */
  133. #define point(x,y) ((y)<<16|(x))
  134. #define STA 0x2120
  135. #define CMD 0x2144
  136. #define ROP 0x2148
  137. #define CLR 0x2160
  138. #define SR1 0x2100
  139. #define SR2 0x2104
  140. #define DR1 0x2108
  141. #define DR2 0x210C
  142. #define ROP_S 0xCC
  143. static void blade_init_accel(int pitch,int bpp)
  144. {
  145. int v1 = (pitch>>3)<<20;
  146. int tmp = 0,v2;
  147. switch (bpp) {
  148. case 8:tmp = 0;break;
  149. case 15:tmp = 5;break;
  150. case 16:tmp = 1;break;
  151. case 24:
  152. case 32:tmp = 2;break;
  153. }
  154. v2 = v1 | (tmp<<29);
  155. writemmr(0x21C0,v2);
  156. writemmr(0x21C4,v2);
  157. writemmr(0x21B8,v2);
  158. writemmr(0x21BC,v2);
  159. writemmr(0x21D0,v1);
  160. writemmr(0x21D4,v1);
  161. writemmr(0x21C8,v1);
  162. writemmr(0x21CC,v1);
  163. writemmr(0x216C,0);
  164. }
  165. static void blade_wait_engine(void)
  166. {
  167. while(readmmr(STA) & 0xFA800000);
  168. }
  169. static void blade_fill_rect(__u32 x,__u32 y,__u32 w,__u32 h,__u32 c,__u32 rop)
  170. {
  171. writemmr(CLR,c);
  172. writemmr(ROP,rop ? 0x66:ROP_S);
  173. writemmr(CMD,0x20000000|1<<19|1<<4|2<<2);
  174. writemmr(DR1,point(x,y));
  175. writemmr(DR2,point(x+w-1,y+h-1));
  176. }
  177. static void blade_copy_rect(__u32 x1,__u32 y1,__u32 x2,__u32 y2,__u32 w,__u32 h)
  178. {
  179. __u32 s1,s2,d1,d2;
  180. int direction = 2;
  181. s1 = point(x1,y1);
  182. s2 = point(x1+w-1,y1+h-1);
  183. d1 = point(x2,y2);
  184. d2 = point(x2+w-1,y2+h-1);
  185. if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
  186. direction = 0;
  187. writemmr(ROP,ROP_S);
  188. writemmr(CMD,0xE0000000|1<<19|1<<4|1<<2|direction);
  189. writemmr(SR1,direction?s2:s1);
  190. writemmr(SR2,direction?s1:s2);
  191. writemmr(DR1,direction?d2:d1);
  192. writemmr(DR2,direction?d1:d2);
  193. }
  194. static struct accel_switch accel_blade = {
  195. blade_init_accel,
  196. blade_wait_engine,
  197. blade_fill_rect,
  198. blade_copy_rect,
  199. };
  200. /*
  201. * BladeXP specific acceleration functions
  202. */
  203. #define ROP_P 0xF0
  204. #define masked_point(x,y) ((y & 0xffff)<<16|(x & 0xffff))
  205. static void xp_init_accel(int pitch,int bpp)
  206. {
  207. int tmp = 0,v1;
  208. unsigned char x = 0;
  209. switch (bpp) {
  210. case 8: x = 0; break;
  211. case 16: x = 1; break;
  212. case 24: x = 3; break;
  213. case 32: x = 2; break;
  214. }
  215. switch (pitch << (bpp >> 3)) {
  216. case 8192:
  217. case 512: x |= 0x00; break;
  218. case 1024: x |= 0x04; break;
  219. case 2048: x |= 0x08; break;
  220. case 4096: x |= 0x0C; break;
  221. }
  222. t_outb(x,0x2125);
  223. eng_oper = x | 0x40;
  224. switch (bpp) {
  225. case 8: tmp = 18; break;
  226. case 15:
  227. case 16: tmp = 19; break;
  228. case 24:
  229. case 32: tmp = 20; break;
  230. }
  231. v1 = pitch << tmp;
  232. writemmr(0x2154,v1);
  233. writemmr(0x2150,v1);
  234. t_outb(3,0x2126);
  235. }
  236. static void xp_wait_engine(void)
  237. {
  238. int busy;
  239. int count, timeout;
  240. count = 0;
  241. timeout = 0;
  242. for (;;) {
  243. busy = t_inb(STA) & 0x80;
  244. if (busy != 0x80)
  245. return;
  246. count++;
  247. if (count == 10000000) {
  248. /* Timeout */
  249. count = 9990000;
  250. timeout++;
  251. if (timeout == 8) {
  252. /* Reset engine */
  253. t_outb(0x00, 0x2120);
  254. return;
  255. }
  256. }
  257. }
  258. }
  259. static void xp_fill_rect(__u32 x,__u32 y,__u32 w,__u32 h,__u32 c,__u32 rop)
  260. {
  261. writemmr(0x2127,ROP_P);
  262. writemmr(0x2158,c);
  263. writemmr(0x2128,0x4000);
  264. writemmr(0x2140,masked_point(h,w));
  265. writemmr(0x2138,masked_point(y,x));
  266. t_outb(0x01,0x2124);
  267. t_outb(eng_oper,0x2125);
  268. }
  269. static void xp_copy_rect(__u32 x1,__u32 y1,__u32 x2,__u32 y2,__u32 w,__u32 h)
  270. {
  271. int direction;
  272. __u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
  273. direction = 0x0004;
  274. if ((x1 < x2) && (y1 == y2)) {
  275. direction |= 0x0200;
  276. x1_tmp = x1 + w - 1;
  277. x2_tmp = x2 + w - 1;
  278. } else {
  279. x1_tmp = x1;
  280. x2_tmp = x2;
  281. }
  282. if (y1 < y2) {
  283. direction |= 0x0100;
  284. y1_tmp = y1 + h - 1;
  285. y2_tmp = y2 + h - 1;
  286. } else {
  287. y1_tmp = y1;
  288. y2_tmp = y2;
  289. }
  290. writemmr(0x2128,direction);
  291. t_outb(ROP_S,0x2127);
  292. writemmr(0x213C,masked_point(y1_tmp,x1_tmp));
  293. writemmr(0x2138,masked_point(y2_tmp,x2_tmp));
  294. writemmr(0x2140,masked_point(h,w));
  295. t_outb(0x01,0x2124);
  296. }
  297. static struct accel_switch accel_xp = {
  298. xp_init_accel,
  299. xp_wait_engine,
  300. xp_fill_rect,
  301. xp_copy_rect,
  302. };
  303. /*
  304. * Image specific acceleration functions
  305. */
  306. static void image_init_accel(int pitch,int bpp)
  307. {
  308. int tmp = 0;
  309. switch (bpp) {
  310. case 8:tmp = 0;break;
  311. case 15:tmp = 5;break;
  312. case 16:tmp = 1;break;
  313. case 24:
  314. case 32:tmp = 2;break;
  315. }
  316. writemmr(0x2120, 0xF0000000);
  317. writemmr(0x2120, 0x40000000|tmp);
  318. writemmr(0x2120, 0x80000000);
  319. writemmr(0x2144, 0x00000000);
  320. writemmr(0x2148, 0x00000000);
  321. writemmr(0x2150, 0x00000000);
  322. writemmr(0x2154, 0x00000000);
  323. writemmr(0x2120, 0x60000000|(pitch<<16) |pitch);
  324. writemmr(0x216C, 0x00000000);
  325. writemmr(0x2170, 0x00000000);
  326. writemmr(0x217C, 0x00000000);
  327. writemmr(0x2120, 0x10000000);
  328. writemmr(0x2130, (2047 << 16) | 2047);
  329. }
  330. static void image_wait_engine(void)
  331. {
  332. while(readmmr(0x2164) & 0xF0000000);
  333. }
  334. static void image_fill_rect(__u32 x, __u32 y, __u32 w, __u32 h, __u32 c, __u32 rop)
  335. {
  336. writemmr(0x2120,0x80000000);
  337. writemmr(0x2120,0x90000000|ROP_S);
  338. writemmr(0x2144,c);
  339. writemmr(DR1,point(x,y));
  340. writemmr(DR2,point(x+w-1,y+h-1));
  341. writemmr(0x2124,0x80000000|3<<22|1<<10|1<<9);
  342. }
  343. static void image_copy_rect(__u32 x1,__u32 y1,__u32 x2,__u32 y2,__u32 w,__u32 h)
  344. {
  345. __u32 s1,s2,d1,d2;
  346. int direction = 2;
  347. s1 = point(x1,y1);
  348. s2 = point(x1+w-1,y1+h-1);
  349. d1 = point(x2,y2);
  350. d2 = point(x2+w-1,y2+h-1);
  351. if ((y1 > y2) || ((y1 == y2) && (x1 >x2)))
  352. direction = 0;
  353. writemmr(0x2120,0x80000000);
  354. writemmr(0x2120,0x90000000|ROP_S);
  355. writemmr(SR1,direction?s2:s1);
  356. writemmr(SR2,direction?s1:s2);
  357. writemmr(DR1,direction?d2:d1);
  358. writemmr(DR2,direction?d1:d2);
  359. writemmr(0x2124,0x80000000|1<<22|1<<10|1<<7|direction);
  360. }
  361. static struct accel_switch accel_image = {
  362. image_init_accel,
  363. image_wait_engine,
  364. image_fill_rect,
  365. image_copy_rect,
  366. };
  367. /*
  368. * Accel functions called by the upper layers
  369. */
  370. #ifdef CONFIG_FB_TRIDENT_ACCEL
  371. static void tridentfb_fillrect(struct fb_info * info, const struct fb_fillrect *fr)
  372. {
  373. int bpp = info->var.bits_per_pixel;
  374. int col = 0;
  375. switch (bpp) {
  376. default:
  377. case 8: col |= fr->color;
  378. col |= col << 8;
  379. col |= col << 16;
  380. break;
  381. case 16: col = ((u32 *)(info->pseudo_palette))[fr->color];
  382. break;
  383. case 32: col = ((u32 *)(info->pseudo_palette))[fr->color];
  384. break;
  385. }
  386. acc->fill_rect(fr->dx, fr->dy, fr->width, fr->height, col, fr->rop);
  387. acc->wait_engine();
  388. }
  389. static void tridentfb_copyarea(struct fb_info *info, const struct fb_copyarea *ca)
  390. {
  391. acc->copy_rect(ca->sx,ca->sy,ca->dx,ca->dy,ca->width,ca->height);
  392. acc->wait_engine();
  393. }
  394. #else /* !CONFIG_FB_TRIDENT_ACCEL */
  395. #define tridentfb_fillrect cfb_fillrect
  396. #define tridentfb_copyarea cfb_copyarea
  397. #endif /* CONFIG_FB_TRIDENT_ACCEL */
  398. /*
  399. * Hardware access functions
  400. */
  401. static inline unsigned char read3X4(int reg)
  402. {
  403. struct tridentfb_par * par = (struct tridentfb_par *)fb_info.par;
  404. writeb(reg, par->io_virt + CRT + 4);
  405. return readb( par->io_virt + CRT + 5);
  406. }
  407. static inline void write3X4(int reg, unsigned char val)
  408. {
  409. struct tridentfb_par * par = (struct tridentfb_par *)fb_info.par;
  410. writeb(reg, par->io_virt + CRT + 4);
  411. writeb(val, par->io_virt + CRT + 5);
  412. }
  413. static inline unsigned char read3C4(int reg)
  414. {
  415. t_outb(reg, 0x3C4);
  416. return t_inb(0x3C5);
  417. }
  418. static inline void write3C4(int reg, unsigned char val)
  419. {
  420. t_outb(reg, 0x3C4);
  421. t_outb(val, 0x3C5);
  422. }
  423. static inline unsigned char read3CE(int reg)
  424. {
  425. t_outb(reg, 0x3CE);
  426. return t_inb(0x3CF);
  427. }
  428. static inline void writeAttr(int reg, unsigned char val)
  429. {
  430. readb(((struct tridentfb_par *)fb_info.par)->io_virt + CRT + 0x0A); //flip-flop to index
  431. t_outb(reg, 0x3C0);
  432. t_outb(val, 0x3C0);
  433. }
  434. static inline void write3CE(int reg, unsigned char val)
  435. {
  436. t_outb(reg, 0x3CE);
  437. t_outb(val, 0x3CF);
  438. }
  439. static inline void enable_mmio(void)
  440. {
  441. /* Goto New Mode */
  442. outb(0x0B, 0x3C4);
  443. inb(0x3C5);
  444. /* Unprotect registers */
  445. outb(NewMode1, 0x3C4);
  446. outb(0x80, 0x3C5);
  447. /* Enable MMIO */
  448. outb(PCIReg, 0x3D4);
  449. outb(inb(0x3D5) | 0x01, 0x3D5);
  450. }
  451. #define crtc_unlock() write3X4(CRTVSyncEnd, read3X4(CRTVSyncEnd) & 0x7F)
  452. /* Return flat panel's maximum x resolution */
  453. static int __devinit get_nativex(void)
  454. {
  455. int x,y,tmp;
  456. if (nativex)
  457. return nativex;
  458. tmp = (read3CE(VertStretch) >> 4) & 3;
  459. switch (tmp) {
  460. case 0: x = 1280; y = 1024; break;
  461. case 2: x = 1024; y = 768; break;
  462. case 3: x = 800; y = 600; break;
  463. case 4: x = 1400; y = 1050; break;
  464. case 1:
  465. default:x = 640; y = 480; break;
  466. }
  467. output("%dx%d flat panel found\n", x, y);
  468. return x;
  469. }
  470. /* Set pitch */
  471. static void set_lwidth(int width)
  472. {
  473. write3X4(Offset, width & 0xFF);
  474. write3X4(AddColReg, (read3X4(AddColReg) & 0xCF) | ((width & 0x300) >>4));
  475. }
  476. /* For resolutions smaller than FP resolution stretch */
  477. static void screen_stretch(void)
  478. {
  479. if (chip_id != CYBERBLADEXPAi1)
  480. write3CE(BiosReg,0);
  481. else
  482. write3CE(BiosReg,8);
  483. write3CE(VertStretch,(read3CE(VertStretch) & 0x7C) | 1);
  484. write3CE(HorStretch,(read3CE(HorStretch) & 0x7C) | 1);
  485. }
  486. /* For resolutions smaller than FP resolution center */
  487. static void screen_center(void)
  488. {
  489. write3CE(VertStretch,(read3CE(VertStretch) & 0x7C) | 0x80);
  490. write3CE(HorStretch,(read3CE(HorStretch) & 0x7C) | 0x80);
  491. }
  492. /* Address of first shown pixel in display memory */
  493. static void set_screen_start(int base)
  494. {
  495. write3X4(StartAddrLow, base & 0xFF);
  496. write3X4(StartAddrHigh, (base & 0xFF00) >> 8);
  497. write3X4(CRTCModuleTest, (read3X4(CRTCModuleTest) & 0xDF) | ((base & 0x10000) >> 11));
  498. write3X4(CRTHiOrd, (read3X4(CRTHiOrd) & 0xF8) | ((base & 0xE0000) >> 17));
  499. }
  500. /* Use 20.12 fixed-point for NTSC value and frequency calculation */
  501. #define calc_freq(n,m,k) ( ((unsigned long)0xE517 * (n+8) / ((m+2)*(1<<k))) >> 12 )
  502. /* Set dotclock frequency */
  503. static void set_vclk(int freq)
  504. {
  505. int m,n,k;
  506. int f,fi,d,di;
  507. unsigned char lo=0,hi=0;
  508. d = 20;
  509. for(k = 2;k>=0;k--)
  510. for(m = 0;m<63;m++)
  511. for(n = 0;n<128;n++) {
  512. fi = calc_freq(n,m,k);
  513. if ((di = abs(fi - freq)) < d) {
  514. d = di;
  515. f = fi;
  516. lo = n;
  517. hi = (k<<6) | m;
  518. }
  519. }
  520. if (chip3D) {
  521. write3C4(ClockHigh,hi);
  522. write3C4(ClockLow,lo);
  523. } else {
  524. outb(lo,0x43C8);
  525. outb(hi,0x43C9);
  526. }
  527. debug("VCLK = %X %X\n",hi,lo);
  528. }
  529. /* Set number of lines for flat panels*/
  530. static void set_number_of_lines(int lines)
  531. {
  532. int tmp = read3CE(CyberEnhance) & 0x8F;
  533. if (lines > 1024)
  534. tmp |= 0x50;
  535. else if (lines > 768)
  536. tmp |= 0x30;
  537. else if (lines > 600)
  538. tmp |= 0x20;
  539. else if (lines > 480)
  540. tmp |= 0x10;
  541. write3CE(CyberEnhance, tmp);
  542. }
  543. /*
  544. * If we see that FP is active we assume we have one.
  545. * Otherwise we have a CRT display.User can override.
  546. */
  547. static unsigned int __devinit get_displaytype(void)
  548. {
  549. if (fp)
  550. return DISPLAY_FP;
  551. if (crt || !chipcyber)
  552. return DISPLAY_CRT;
  553. return (read3CE(FPConfig) & 0x10)?DISPLAY_FP:DISPLAY_CRT;
  554. }
  555. /* Try detecting the video memory size */
  556. static unsigned int __devinit get_memsize(void)
  557. {
  558. unsigned char tmp, tmp2;
  559. unsigned int k;
  560. /* If memory size provided by user */
  561. if (memsize)
  562. k = memsize * Kb;
  563. else
  564. switch (chip_id) {
  565. case CYBER9525DVD: k = 2560 * Kb; break;
  566. default:
  567. tmp = read3X4(SPR) & 0x0F;
  568. switch (tmp) {
  569. case 0x01: k = 512; break;
  570. case 0x02: k = 6 * Mb; break; /* XP */
  571. case 0x03: k = 1 * Mb; break;
  572. case 0x04: k = 8 * Mb; break;
  573. case 0x06: k = 10 * Mb; break; /* XP */
  574. case 0x07: k = 2 * Mb; break;
  575. case 0x08: k = 12 * Mb; break; /* XP */
  576. case 0x0A: k = 14 * Mb; break; /* XP */
  577. case 0x0C: k = 16 * Mb; break; /* XP */
  578. case 0x0E: /* XP */
  579. tmp2 = read3C4(0xC1);
  580. switch (tmp2) {
  581. case 0x00: k = 20 * Mb; break;
  582. case 0x01: k = 24 * Mb; break;
  583. case 0x10: k = 28 * Mb; break;
  584. case 0x11: k = 32 * Mb; break;
  585. default: k = 1 * Mb; break;
  586. }
  587. break;
  588. case 0x0F: k = 4 * Mb; break;
  589. default: k = 1 * Mb;
  590. }
  591. }
  592. k -= memdiff * Kb;
  593. output("framebuffer size = %d Kb\n", k/Kb);
  594. return k;
  595. }
  596. /* See if we can handle the video mode described in var */
  597. static int tridentfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  598. {
  599. int bpp = var->bits_per_pixel;
  600. debug("enter\n");
  601. /* check color depth */
  602. if (bpp == 24 )
  603. bpp = var->bits_per_pixel = 32;
  604. /* check whether resolution fits on panel and in memory*/
  605. if (flatpanel && nativex && var->xres > nativex)
  606. return -EINVAL;
  607. if (var->xres * var->yres_virtual * bpp/8 > info->fix.smem_len)
  608. return -EINVAL;
  609. switch (bpp) {
  610. case 8:
  611. var->red.offset = 0;
  612. var->green.offset = 0;
  613. var->blue.offset = 0;
  614. var->red.length = 6;
  615. var->green.length = 6;
  616. var->blue.length = 6;
  617. break;
  618. case 16:
  619. var->red.offset = 11;
  620. var->green.offset = 5;
  621. var->blue.offset = 0;
  622. var->red.length = 5;
  623. var->green.length = 6;
  624. var->blue.length = 5;
  625. break;
  626. case 32:
  627. var->red.offset = 16;
  628. var->green.offset = 8;
  629. var->blue.offset = 0;
  630. var->red.length = 8;
  631. var->green.length = 8;
  632. var->blue.length = 8;
  633. break;
  634. default:
  635. return -EINVAL;
  636. }
  637. debug("exit\n");
  638. return 0;
  639. }
  640. /* Pan the display */
  641. static int tridentfb_pan_display(struct fb_var_screeninfo *var,
  642. struct fb_info *info)
  643. {
  644. unsigned int offset;
  645. debug("enter\n");
  646. offset = (var->xoffset + (var->yoffset * var->xres))
  647. * var->bits_per_pixel/32;
  648. info->var.xoffset = var->xoffset;
  649. info->var.yoffset = var->yoffset;
  650. set_screen_start(offset);
  651. debug("exit\n");
  652. return 0;
  653. }
  654. #define shadowmode_on() write3CE(CyberControl,read3CE(CyberControl) | 0x81)
  655. #define shadowmode_off() write3CE(CyberControl,read3CE(CyberControl) & 0x7E)
  656. /* Set the hardware to the requested video mode */
  657. static int tridentfb_set_par(struct fb_info *info)
  658. {
  659. struct tridentfb_par * par = (struct tridentfb_par *)(info->par);
  660. u32 htotal,hdispend,hsyncstart,hsyncend,hblankstart,hblankend,
  661. vtotal,vdispend,vsyncstart,vsyncend,vblankstart,vblankend;
  662. struct fb_var_screeninfo *var = &info->var;
  663. int bpp = var->bits_per_pixel;
  664. unsigned char tmp;
  665. debug("enter\n");
  666. htotal = (var->xres + var->left_margin + var->right_margin + var->hsync_len)/8 - 10;
  667. hdispend = var->xres/8 - 1;
  668. hsyncstart = (var->xres + var->right_margin)/8;
  669. hsyncend = var->hsync_len/8;
  670. hblankstart = hdispend + 1;
  671. hblankend = htotal + 5;
  672. vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len - 2;
  673. vdispend = var->yres - 1;
  674. vsyncstart = var->yres + var->lower_margin;
  675. vsyncend = var->vsync_len;
  676. vblankstart = var->yres;
  677. vblankend = vtotal + 2;
  678. enable_mmio();
  679. crtc_unlock();
  680. write3CE(CyberControl,8);
  681. if (flatpanel && var->xres < nativex) {
  682. /*
  683. * on flat panels with native size larger
  684. * than requested resolution decide whether
  685. * we stretch or center
  686. */
  687. t_outb(0xEB,0x3C2);
  688. shadowmode_on();
  689. if (center)
  690. screen_center();
  691. else if (stretch)
  692. screen_stretch();
  693. } else {
  694. t_outb(0x2B,0x3C2);
  695. write3CE(CyberControl,8);
  696. }
  697. /* vertical timing values */
  698. write3X4(CRTVTotal, vtotal & 0xFF);
  699. write3X4(CRTVDispEnd, vdispend & 0xFF);
  700. write3X4(CRTVSyncStart, vsyncstart & 0xFF);
  701. write3X4(CRTVSyncEnd, (vsyncend & 0x0F));
  702. write3X4(CRTVBlankStart, vblankstart & 0xFF);
  703. write3X4(CRTVBlankEnd, 0/*p->vblankend & 0xFF*/);
  704. /* horizontal timing values */
  705. write3X4(CRTHTotal, htotal & 0xFF);
  706. write3X4(CRTHDispEnd, hdispend & 0xFF);
  707. write3X4(CRTHSyncStart, hsyncstart & 0xFF);
  708. write3X4(CRTHSyncEnd, (hsyncend & 0x1F) | ((hblankend & 0x20)<<2));
  709. write3X4(CRTHBlankStart, hblankstart & 0xFF);
  710. write3X4(CRTHBlankEnd, 0/*(p->hblankend & 0x1F)*/);
  711. /* higher bits of vertical timing values */
  712. tmp = 0x10;
  713. if (vtotal & 0x100) tmp |= 0x01;
  714. if (vdispend & 0x100) tmp |= 0x02;
  715. if (vsyncstart & 0x100) tmp |= 0x04;
  716. if (vblankstart & 0x100) tmp |= 0x08;
  717. if (vtotal & 0x200) tmp |= 0x20;
  718. if (vdispend & 0x200) tmp |= 0x40;
  719. if (vsyncstart & 0x200) tmp |= 0x80;
  720. write3X4(CRTOverflow, tmp);
  721. tmp = read3X4(CRTHiOrd) | 0x08; //line compare bit 10
  722. if (vtotal & 0x400) tmp |= 0x80;
  723. if (vblankstart & 0x400) tmp |= 0x40;
  724. if (vsyncstart & 0x400) tmp |= 0x20;
  725. if (vdispend & 0x400) tmp |= 0x10;
  726. write3X4(CRTHiOrd, tmp);
  727. tmp = 0;
  728. if (htotal & 0x800) tmp |= 0x800 >> 11;
  729. if (hblankstart & 0x800) tmp |= 0x800 >> 7;
  730. write3X4(HorizOverflow, tmp);
  731. tmp = 0x40;
  732. if (vblankstart & 0x200) tmp |= 0x20;
  733. //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; //double scan for 200 line modes
  734. write3X4(CRTMaxScanLine, tmp);
  735. write3X4(CRTLineCompare,0xFF);
  736. write3X4(CRTPRowScan,0);
  737. write3X4(CRTModeControl,0xC3);
  738. write3X4(LinearAddReg,0x20); //enable linear addressing
  739. tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84:0x80;
  740. write3X4(CRTCModuleTest,tmp); //enable access extended memory
  741. write3X4(GraphEngReg, 0x80); //enable GE for text acceleration
  742. #ifdef CONFIG_FB_TRIDENT_ACCEL
  743. acc->init_accel(info->var.xres,bpp);
  744. #endif
  745. switch (bpp) {
  746. case 8: tmp = 0x00; break;
  747. case 16: tmp = 0x05; break;
  748. case 24: tmp = 0x29; break;
  749. case 32: tmp = 0x09;
  750. }
  751. write3X4(PixelBusReg, tmp);
  752. tmp = 0x10;
  753. if (chipcyber)
  754. tmp |= 0x20;
  755. write3X4(DRAMControl, tmp); //both IO,linear enable
  756. write3X4(InterfaceSel, read3X4(InterfaceSel) | 0x40);
  757. write3X4(Performance,0x92);
  758. write3X4(PCIReg,0x07); //MMIO & PCI read and write burst enable
  759. /* convert from picoseconds to MHz */
  760. par->vclk = 1000000/info->var.pixclock;
  761. if (bpp == 32)
  762. par->vclk *=2;
  763. set_vclk(par->vclk);
  764. write3C4(0,3);
  765. write3C4(1,1); //set char clock 8 dots wide
  766. write3C4(2,0x0F); //enable 4 maps because needed in chain4 mode
  767. write3C4(3,0);
  768. write3C4(4,0x0E); //memory mode enable bitmaps ??
  769. write3CE(MiscExtFunc,(bpp==32)?0x1A:0x12); //divide clock by 2 if 32bpp
  770. //chain4 mode display and CPU path
  771. write3CE(0x5,0x40); //no CGA compat,allow 256 col
  772. write3CE(0x6,0x05); //graphics mode
  773. write3CE(0x7,0x0F); //planes?
  774. if (chip_id == CYBERBLADEXPAi1) {
  775. /* This fixes snow-effect in 32 bpp */
  776. write3X4(CRTHSyncStart,0x84);
  777. }
  778. writeAttr(0x10,0x41); //graphics mode and support 256 color modes
  779. writeAttr(0x12,0x0F); //planes
  780. writeAttr(0x13,0); //horizontal pel panning
  781. //colors
  782. for(tmp = 0;tmp < 0x10;tmp++)
  783. writeAttr(tmp,tmp);
  784. readb(par->io_virt + CRT + 0x0A); //flip-flop to index
  785. t_outb(0x20, 0x3C0); //enable attr
  786. switch (bpp) {
  787. case 8: tmp = 0;break; //256 colors
  788. case 15: tmp = 0x10;break;
  789. case 16: tmp = 0x30;break; //hicolor
  790. case 24: //truecolor
  791. case 32: tmp = 0xD0;break;
  792. }
  793. t_inb(0x3C8);
  794. t_inb(0x3C6);
  795. t_inb(0x3C6);
  796. t_inb(0x3C6);
  797. t_inb(0x3C6);
  798. t_outb(tmp,0x3C6);
  799. t_inb(0x3C8);
  800. if (flatpanel)
  801. set_number_of_lines(info->var.yres);
  802. set_lwidth(info->var.xres * bpp/(4*16));
  803. info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  804. info->fix.line_length = info->var.xres * (bpp >> 3);
  805. info->cmap.len = (bpp == 8) ? 256: 16;
  806. debug("exit\n");
  807. return 0;
  808. }
  809. /* Set one color register */
  810. static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
  811. unsigned blue, unsigned transp,
  812. struct fb_info *info)
  813. {
  814. int bpp = info->var.bits_per_pixel;
  815. if (regno >= info->cmap.len)
  816. return 1;
  817. if (bpp==8) {
  818. t_outb(0xFF,0x3C6);
  819. t_outb(regno,0x3C8);
  820. t_outb(red>>10,0x3C9);
  821. t_outb(green>>10,0x3C9);
  822. t_outb(blue>>10,0x3C9);
  823. } else if (bpp == 16) { /* RGB 565 */
  824. u32 col;
  825. col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
  826. ((blue & 0xF800) >> 11);
  827. col |= col << 16;
  828. ((u32 *)(info->pseudo_palette))[regno] = col;
  829. } else if (bpp == 32) /* ARGB 8888 */
  830. ((u32*)info->pseudo_palette)[regno] =
  831. ((transp & 0xFF00) <<16) |
  832. ((red & 0xFF00) << 8) |
  833. ((green & 0xFF00)) |
  834. ((blue & 0xFF00)>>8);
  835. // debug("exit\n");
  836. return 0;
  837. }
  838. /* Try blanking the screen.For flat panels it does nothing */
  839. static int tridentfb_blank(int blank_mode, struct fb_info *info)
  840. {
  841. unsigned char PMCont,DPMSCont;
  842. debug("enter\n");
  843. if (flatpanel)
  844. return 0;
  845. t_outb(0x04,0x83C8); /* Read DPMS Control */
  846. PMCont = t_inb(0x83C6) & 0xFC;
  847. DPMSCont = read3CE(PowerStatus) & 0xFC;
  848. switch (blank_mode)
  849. {
  850. case FB_BLANK_UNBLANK:
  851. /* Screen: On, HSync: On, VSync: On */
  852. case FB_BLANK_NORMAL:
  853. /* Screen: Off, HSync: On, VSync: On */
  854. PMCont |= 0x03;
  855. DPMSCont |= 0x00;
  856. break;
  857. case FB_BLANK_HSYNC_SUSPEND:
  858. /* Screen: Off, HSync: Off, VSync: On */
  859. PMCont |= 0x02;
  860. DPMSCont |= 0x01;
  861. break;
  862. case FB_BLANK_VSYNC_SUSPEND:
  863. /* Screen: Off, HSync: On, VSync: Off */
  864. PMCont |= 0x02;
  865. DPMSCont |= 0x02;
  866. break;
  867. case FB_BLANK_POWERDOWN:
  868. /* Screen: Off, HSync: Off, VSync: Off */
  869. PMCont |= 0x00;
  870. DPMSCont |= 0x03;
  871. break;
  872. }
  873. write3CE(PowerStatus,DPMSCont);
  874. t_outb(4,0x83C8);
  875. t_outb(PMCont,0x83C6);
  876. debug("exit\n");
  877. /* let fbcon do a softblank for us */
  878. return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
  879. }
  880. static int __devinit trident_pci_probe(struct pci_dev * dev, const struct pci_device_id * id)
  881. {
  882. int err;
  883. unsigned char revision;
  884. err = pci_enable_device(dev);
  885. if (err)
  886. return err;
  887. chip_id = id->device;
  888. if(chip_id == CYBERBLADEi1)
  889. output("*** Please do use cyblafb, Cyberblade/i1 support "
  890. "will soon be removed from tridentfb!\n");
  891. /* If PCI id is 0x9660 then further detect chip type */
  892. if (chip_id == TGUI9660) {
  893. outb(RevisionID,0x3C4);
  894. revision = inb(0x3C5);
  895. switch (revision) {
  896. case 0x22:
  897. case 0x23: chip_id = CYBER9397;break;
  898. case 0x2A: chip_id = CYBER9397DVD;break;
  899. case 0x30:
  900. case 0x33:
  901. case 0x34:
  902. case 0x35:
  903. case 0x38:
  904. case 0x3A:
  905. case 0xB3: chip_id = CYBER9385;break;
  906. case 0x40 ... 0x43: chip_id = CYBER9382;break;
  907. case 0x4A: chip_id = CYBER9388;break;
  908. default:break;
  909. }
  910. }
  911. chip3D = is3Dchip(chip_id);
  912. chipcyber = iscyber(chip_id);
  913. if (is_xp(chip_id)) {
  914. acc = &accel_xp;
  915. } else
  916. if (is_blade(chip_id)) {
  917. acc = &accel_blade;
  918. } else {
  919. acc = &accel_image;
  920. }
  921. /* acceleration is on by default for 3D chips */
  922. defaultaccel = chip3D && !noaccel;
  923. fb_info.par = &default_par;
  924. /* setup MMIO region */
  925. tridentfb_fix.mmio_start = pci_resource_start(dev,1);
  926. tridentfb_fix.mmio_len = chip3D ? 0x20000:0x10000;
  927. if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
  928. debug("request_region failed!\n");
  929. return -1;
  930. }
  931. default_par.io_virt = ioremap_nocache(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
  932. if (!default_par.io_virt) {
  933. release_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
  934. debug("ioremap failed\n");
  935. return -1;
  936. }
  937. enable_mmio();
  938. /* setup framebuffer memory */
  939. tridentfb_fix.smem_start = pci_resource_start(dev,0);
  940. tridentfb_fix.smem_len = get_memsize();
  941. if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
  942. debug("request_mem_region failed!\n");
  943. err = -1;
  944. goto out_unmap;
  945. }
  946. fb_info.screen_base = ioremap_nocache(tridentfb_fix.smem_start,
  947. tridentfb_fix.smem_len);
  948. if (!fb_info.screen_base) {
  949. release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
  950. debug("ioremap failed\n");
  951. err = -1;
  952. goto out_unmap;
  953. }
  954. output("%s board found\n", pci_name(dev));
  955. #if 0
  956. output("Trident board found : mem = %X,io = %X, mem_v = %X, io_v = %X\n",
  957. tridentfb_fix.smem_start, tridentfb_fix.mmio_start, fb_info.screen_base, default_par.io_virt);
  958. #endif
  959. displaytype = get_displaytype();
  960. if(flatpanel)
  961. nativex = get_nativex();
  962. fb_info.fix = tridentfb_fix;
  963. fb_info.fbops = &tridentfb_ops;
  964. fb_info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  965. #ifdef CONFIG_FB_TRIDENT_ACCEL
  966. fb_info.flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
  967. #endif
  968. fb_info.pseudo_palette = pseudo_pal;
  969. if (!fb_find_mode(&default_var,&fb_info,mode,NULL,0,NULL,bpp)) {
  970. err = -EINVAL;
  971. goto out_unmap;
  972. }
  973. fb_alloc_cmap(&fb_info.cmap,256,0);
  974. if (defaultaccel && acc)
  975. default_var.accel_flags |= FB_ACCELF_TEXT;
  976. else
  977. default_var.accel_flags &= ~FB_ACCELF_TEXT;
  978. default_var.activate |= FB_ACTIVATE_NOW;
  979. fb_info.var = default_var;
  980. fb_info.device = &dev->dev;
  981. if (register_framebuffer(&fb_info) < 0) {
  982. printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
  983. err = -EINVAL;
  984. goto out_unmap;
  985. }
  986. output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
  987. fb_info.node, fb_info.fix.id,default_var.xres,
  988. default_var.yres,default_var.bits_per_pixel);
  989. return 0;
  990. out_unmap:
  991. if (default_par.io_virt)
  992. iounmap(default_par.io_virt);
  993. if (fb_info.screen_base)
  994. iounmap(fb_info.screen_base);
  995. return err;
  996. }
  997. static void __devexit trident_pci_remove(struct pci_dev * dev)
  998. {
  999. struct tridentfb_par *par = (struct tridentfb_par*)fb_info.par;
  1000. unregister_framebuffer(&fb_info);
  1001. iounmap(par->io_virt);
  1002. iounmap(fb_info.screen_base);
  1003. release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
  1004. release_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
  1005. }
  1006. /* List of boards that we are trying to support */
  1007. static struct pci_device_id trident_devices[] = {
  1008. {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1009. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1010. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1011. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1012. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1013. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1014. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1015. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1016. {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1017. {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1018. {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1019. {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1020. {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1021. {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1022. {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1023. {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1024. {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1025. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1026. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1027. {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID,PCI_ANY_ID,0,0,0},
  1028. {0,}
  1029. };
  1030. MODULE_DEVICE_TABLE(pci,trident_devices);
  1031. static struct pci_driver tridentfb_pci_driver = {
  1032. .name = "tridentfb",
  1033. .id_table = trident_devices,
  1034. .probe = trident_pci_probe,
  1035. .remove = __devexit_p(trident_pci_remove)
  1036. };
  1037. /*
  1038. * Parse user specified options (`video=trident:')
  1039. * example:
  1040. * video=trident:800x600,bpp=16,noaccel
  1041. */
  1042. #ifndef MODULE
  1043. static int tridentfb_setup(char *options)
  1044. {
  1045. char * opt;
  1046. if (!options || !*options)
  1047. return 0;
  1048. while((opt = strsep(&options,",")) != NULL ) {
  1049. if (!*opt) continue;
  1050. if (!strncmp(opt,"noaccel",7))
  1051. noaccel = 1;
  1052. else if (!strncmp(opt,"fp",2))
  1053. displaytype = DISPLAY_FP;
  1054. else if (!strncmp(opt,"crt",3))
  1055. displaytype = DISPLAY_CRT;
  1056. else if (!strncmp(opt,"bpp=",4))
  1057. bpp = simple_strtoul(opt+4,NULL,0);
  1058. else if (!strncmp(opt,"center",6))
  1059. center = 1;
  1060. else if (!strncmp(opt,"stretch",7))
  1061. stretch = 1;
  1062. else if (!strncmp(opt,"memsize=",8))
  1063. memsize = simple_strtoul(opt+8,NULL,0);
  1064. else if (!strncmp(opt,"memdiff=",8))
  1065. memdiff = simple_strtoul(opt+8,NULL,0);
  1066. else if (!strncmp(opt,"nativex=",8))
  1067. nativex = simple_strtoul(opt+8,NULL,0);
  1068. else
  1069. mode = opt;
  1070. }
  1071. return 0;
  1072. }
  1073. #endif
  1074. static int __init tridentfb_init(void)
  1075. {
  1076. #ifndef MODULE
  1077. char *option = NULL;
  1078. if (fb_get_options("tridentfb", &option))
  1079. return -ENODEV;
  1080. tridentfb_setup(option);
  1081. #endif
  1082. output("Trident framebuffer %s initializing\n", VERSION);
  1083. return pci_register_driver(&tridentfb_pci_driver);
  1084. }
  1085. static void __exit tridentfb_exit(void)
  1086. {
  1087. pci_unregister_driver(&tridentfb_pci_driver);
  1088. }
  1089. static struct fb_ops tridentfb_ops = {
  1090. .owner = THIS_MODULE,
  1091. .fb_setcolreg = tridentfb_setcolreg,
  1092. .fb_pan_display = tridentfb_pan_display,
  1093. .fb_blank = tridentfb_blank,
  1094. .fb_check_var = tridentfb_check_var,
  1095. .fb_set_par = tridentfb_set_par,
  1096. .fb_fillrect = tridentfb_fillrect,
  1097. .fb_copyarea= tridentfb_copyarea,
  1098. .fb_imageblit = cfb_imageblit,
  1099. };
  1100. module_init(tridentfb_init);
  1101. module_exit(tridentfb_exit);
  1102. MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
  1103. MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
  1104. MODULE_LICENSE("GPL");