svgalib.c 18 KB

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  1. /*
  2. * Common utility functions for VGA-based graphics cards.
  3. *
  4. * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file COPYING in the main directory of this archive for
  8. * more details.
  9. *
  10. * Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
  11. */
  12. #include <linux/module.h>
  13. #include <linux/kernel.h>
  14. #include <linux/string.h>
  15. #include <linux/fb.h>
  16. #include <linux/svga.h>
  17. #include <linux/slab.h>
  18. #include <asm/types.h>
  19. #include <asm/io.h>
  20. /* Write a CRT register value spread across multiple registers */
  21. void svga_wcrt_multi(const struct vga_regset *regset, u32 value) {
  22. u8 regval, bitval, bitnum;
  23. while (regset->regnum != VGA_REGSET_END_VAL) {
  24. regval = vga_rcrt(NULL, regset->regnum);
  25. bitnum = regset->lowbit;
  26. while (bitnum <= regset->highbit) {
  27. bitval = 1 << bitnum;
  28. regval = regval & ~bitval;
  29. if (value & 1) regval = regval | bitval;
  30. bitnum ++;
  31. value = value >> 1;
  32. }
  33. vga_wcrt(NULL, regset->regnum, regval);
  34. regset ++;
  35. }
  36. }
  37. /* Write a sequencer register value spread across multiple registers */
  38. void svga_wseq_multi(const struct vga_regset *regset, u32 value) {
  39. u8 regval, bitval, bitnum;
  40. while (regset->regnum != VGA_REGSET_END_VAL) {
  41. regval = vga_rseq(NULL, regset->regnum);
  42. bitnum = regset->lowbit;
  43. while (bitnum <= regset->highbit) {
  44. bitval = 1 << bitnum;
  45. regval = regval & ~bitval;
  46. if (value & 1) regval = regval | bitval;
  47. bitnum ++;
  48. value = value >> 1;
  49. }
  50. vga_wseq(NULL, regset->regnum, regval);
  51. regset ++;
  52. }
  53. }
  54. static unsigned int svga_regset_size(const struct vga_regset *regset)
  55. {
  56. u8 count = 0;
  57. while (regset->regnum != VGA_REGSET_END_VAL) {
  58. count += regset->highbit - regset->lowbit + 1;
  59. regset ++;
  60. }
  61. return 1 << count;
  62. }
  63. /* ------------------------------------------------------------------------- */
  64. /* Set graphics controller registers to sane values */
  65. void svga_set_default_gfx_regs(void)
  66. {
  67. /* All standard GFX registers (GR00 - GR08) */
  68. vga_wgfx(NULL, VGA_GFX_SR_VALUE, 0x00);
  69. vga_wgfx(NULL, VGA_GFX_SR_ENABLE, 0x00);
  70. vga_wgfx(NULL, VGA_GFX_COMPARE_VALUE, 0x00);
  71. vga_wgfx(NULL, VGA_GFX_DATA_ROTATE, 0x00);
  72. vga_wgfx(NULL, VGA_GFX_PLANE_READ, 0x00);
  73. vga_wgfx(NULL, VGA_GFX_MODE, 0x00);
  74. /* vga_wgfx(NULL, VGA_GFX_MODE, 0x20); */
  75. /* vga_wgfx(NULL, VGA_GFX_MODE, 0x40); */
  76. vga_wgfx(NULL, VGA_GFX_MISC, 0x05);
  77. /* vga_wgfx(NULL, VGA_GFX_MISC, 0x01); */
  78. vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x0F);
  79. vga_wgfx(NULL, VGA_GFX_BIT_MASK, 0xFF);
  80. }
  81. /* Set attribute controller registers to sane values */
  82. void svga_set_default_atc_regs(void)
  83. {
  84. u8 count;
  85. vga_r(NULL, 0x3DA);
  86. vga_w(NULL, VGA_ATT_W, 0x00);
  87. /* All standard ATC registers (AR00 - AR14) */
  88. for (count = 0; count <= 0xF; count ++)
  89. svga_wattr(count, count);
  90. svga_wattr(VGA_ATC_MODE, 0x01);
  91. /* svga_wattr(VGA_ATC_MODE, 0x41); */
  92. svga_wattr(VGA_ATC_OVERSCAN, 0x00);
  93. svga_wattr(VGA_ATC_PLANE_ENABLE, 0x0F);
  94. svga_wattr(VGA_ATC_PEL, 0x00);
  95. svga_wattr(VGA_ATC_COLOR_PAGE, 0x00);
  96. vga_r(NULL, 0x3DA);
  97. vga_w(NULL, VGA_ATT_W, 0x20);
  98. }
  99. /* Set sequencer registers to sane values */
  100. void svga_set_default_seq_regs(void)
  101. {
  102. /* Standard sequencer registers (SR01 - SR04), SR00 is not set */
  103. vga_wseq(NULL, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
  104. vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
  105. vga_wseq(NULL, VGA_SEQ_CHARACTER_MAP, 0x00);
  106. /* vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
  107. vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
  108. }
  109. /* Set CRTC registers to sane values */
  110. void svga_set_default_crt_regs(void)
  111. {
  112. /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */
  113. svga_wcrt_mask(0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */
  114. vga_wcrt(NULL, VGA_CRTC_PRESET_ROW, 0);
  115. svga_wcrt_mask(VGA_CRTC_MAX_SCAN, 0, 0x1F);
  116. vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0);
  117. vga_wcrt(NULL, VGA_CRTC_MODE, 0xE3);
  118. }
  119. void svga_set_textmode_vga_regs(void)
  120. {
  121. /* svga_wseq_mask(0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */
  122. vga_wseq(NULL, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
  123. vga_wseq(NULL, VGA_SEQ_PLANE_WRITE, 0x03);
  124. vga_wcrt(NULL, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */
  125. vga_wcrt(NULL, VGA_CRTC_UNDERLINE, 0x1f);
  126. svga_wcrt_mask(VGA_CRTC_MODE, 0x23, 0x7f);
  127. vga_wcrt(NULL, VGA_CRTC_CURSOR_START, 0x0d);
  128. vga_wcrt(NULL, VGA_CRTC_CURSOR_END, 0x0e);
  129. vga_wcrt(NULL, VGA_CRTC_CURSOR_HI, 0x00);
  130. vga_wcrt(NULL, VGA_CRTC_CURSOR_LO, 0x00);
  131. vga_wgfx(NULL, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */
  132. vga_wgfx(NULL, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */
  133. vga_wgfx(NULL, VGA_GFX_COMPARE_MASK, 0x00);
  134. vga_r(NULL, 0x3DA);
  135. vga_w(NULL, VGA_ATT_W, 0x00);
  136. svga_wattr(0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */
  137. svga_wattr(0x13, 0x08); /* Horizontal Pixel Panning Register */
  138. vga_r(NULL, 0x3DA);
  139. vga_w(NULL, VGA_ATT_W, 0x20);
  140. }
  141. #if 0
  142. void svga_dump_var(struct fb_var_screeninfo *var, int node)
  143. {
  144. pr_debug("fb%d: var.vmode : 0x%X\n", node, var->vmode);
  145. pr_debug("fb%d: var.xres : %d\n", node, var->xres);
  146. pr_debug("fb%d: var.yres : %d\n", node, var->yres);
  147. pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel);
  148. pr_debug("fb%d: var.xres_virtual : %d\n", node, var->xres_virtual);
  149. pr_debug("fb%d: var.yres_virtual : %d\n", node, var->yres_virtual);
  150. pr_debug("fb%d: var.left_margin : %d\n", node, var->left_margin);
  151. pr_debug("fb%d: var.right_margin : %d\n", node, var->right_margin);
  152. pr_debug("fb%d: var.upper_margin : %d\n", node, var->upper_margin);
  153. pr_debug("fb%d: var.lower_margin : %d\n", node, var->lower_margin);
  154. pr_debug("fb%d: var.hsync_len : %d\n", node, var->hsync_len);
  155. pr_debug("fb%d: var.vsync_len : %d\n", node, var->vsync_len);
  156. pr_debug("fb%d: var.sync : 0x%X\n", node, var->sync);
  157. pr_debug("fb%d: var.pixclock : %d\n\n", node, var->pixclock);
  158. }
  159. #endif /* 0 */
  160. /* ------------------------------------------------------------------------- */
  161. void svga_settile(struct fb_info *info, struct fb_tilemap *map)
  162. {
  163. const u8 *font = map->data;
  164. u8* fb = (u8 *) info->screen_base;
  165. int i, c;
  166. if ((map->width != 8) || (map->height != 16) ||
  167. (map->depth != 1) || (map->length != 256)) {
  168. printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
  169. info->node, map->width, map->height, map->depth, map->length);
  170. return;
  171. }
  172. fb += 2;
  173. for (c = 0; c < map->length; c++) {
  174. for (i = 0; i < map->height; i++) {
  175. fb[i * 4] = font[i];
  176. }
  177. fb += 128;
  178. font += map->height;
  179. }
  180. }
  181. /* Copy area in text (tileblit) mode */
  182. void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area)
  183. {
  184. int dx, dy;
  185. /* colstride is halved in this function because u16 are used */
  186. int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
  187. int rowstride = colstride * (info->var.xres_virtual / 8);
  188. u16 *fb = (u16 *) info->screen_base;
  189. u16 *src, *dst;
  190. if ((area->sy > area->dy) ||
  191. ((area->sy == area->dy) && (area->sx > area->dx))) {
  192. src = fb + area->sx * colstride + area->sy * rowstride;
  193. dst = fb + area->dx * colstride + area->dy * rowstride;
  194. } else {
  195. src = fb + (area->sx + area->width - 1) * colstride
  196. + (area->sy + area->height - 1) * rowstride;
  197. dst = fb + (area->dx + area->width - 1) * colstride
  198. + (area->dy + area->height - 1) * rowstride;
  199. colstride = -colstride;
  200. rowstride = -rowstride;
  201. }
  202. for (dy = 0; dy < area->height; dy++) {
  203. u16* src2 = src;
  204. u16* dst2 = dst;
  205. for (dx = 0; dx < area->width; dx++) {
  206. *dst2 = *src2;
  207. src2 += colstride;
  208. dst2 += colstride;
  209. }
  210. src += rowstride;
  211. dst += rowstride;
  212. }
  213. }
  214. /* Fill area in text (tileblit) mode */
  215. void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect)
  216. {
  217. int dx, dy;
  218. int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
  219. int rowstride = colstride * (info->var.xres_virtual / 8);
  220. int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg);
  221. u8 *fb = (u8 *) info->screen_base;
  222. fb += rect->sx * colstride + rect->sy * rowstride;
  223. for (dy = 0; dy < rect->height; dy++) {
  224. u8* fb2 = fb;
  225. for (dx = 0; dx < rect->width; dx++) {
  226. fb2[0] = rect->index;
  227. fb2[1] = attr;
  228. fb2 += colstride;
  229. }
  230. fb += rowstride;
  231. }
  232. }
  233. /* Write text in text (tileblit) mode */
  234. void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit)
  235. {
  236. int dx, dy, i;
  237. int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
  238. int rowstride = colstride * (info->var.xres_virtual / 8);
  239. int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg);
  240. u8* fb = (u8 *) info->screen_base;
  241. fb += blit->sx * colstride + blit->sy * rowstride;
  242. i=0;
  243. for (dy=0; dy < blit->height; dy ++) {
  244. u8* fb2 = fb;
  245. for (dx = 0; dx < blit->width; dx ++) {
  246. fb2[0] = blit->indices[i];
  247. fb2[1] = attr;
  248. fb2 += colstride;
  249. i ++;
  250. if (i == blit->length) return;
  251. }
  252. fb += rowstride;
  253. }
  254. }
  255. /* Set cursor in text (tileblit) mode */
  256. void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor)
  257. {
  258. u8 cs = 0x0d;
  259. u8 ce = 0x0e;
  260. u16 pos = cursor->sx + (info->var.xoffset / 8)
  261. + (cursor->sy + (info->var.yoffset / 16))
  262. * (info->var.xres_virtual / 8);
  263. if (! cursor -> mode)
  264. return;
  265. svga_wcrt_mask(0x0A, 0x20, 0x20); /* disable cursor */
  266. if (cursor -> shape == FB_TILE_CURSOR_NONE)
  267. return;
  268. switch (cursor -> shape) {
  269. case FB_TILE_CURSOR_UNDERLINE:
  270. cs = 0x0d;
  271. break;
  272. case FB_TILE_CURSOR_LOWER_THIRD:
  273. cs = 0x09;
  274. break;
  275. case FB_TILE_CURSOR_LOWER_HALF:
  276. cs = 0x07;
  277. break;
  278. case FB_TILE_CURSOR_TWO_THIRDS:
  279. cs = 0x05;
  280. break;
  281. case FB_TILE_CURSOR_BLOCK:
  282. cs = 0x01;
  283. break;
  284. }
  285. /* set cursor position */
  286. vga_wcrt(NULL, 0x0E, pos >> 8);
  287. vga_wcrt(NULL, 0x0F, pos & 0xFF);
  288. vga_wcrt(NULL, 0x0B, ce); /* set cursor end */
  289. vga_wcrt(NULL, 0x0A, cs); /* set cursor start and enable it */
  290. }
  291. /* ------------------------------------------------------------------------- */
  292. /*
  293. * Compute PLL settings (M, N, R)
  294. * F_VCO = (F_BASE * M) / N
  295. * F_OUT = F_VCO / (2^R)
  296. */
  297. static inline u32 abs_diff(u32 a, u32 b)
  298. {
  299. return (a > b) ? (a - b) : (b - a);
  300. }
  301. int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node)
  302. {
  303. u16 am, an, ar;
  304. u32 f_vco, f_current, delta_current, delta_best;
  305. pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int) f_wanted);
  306. ar = pll->r_max;
  307. f_vco = f_wanted << ar;
  308. /* overflow check */
  309. if ((f_vco >> ar) != f_wanted)
  310. return -EINVAL;
  311. /* It is usually better to have greater VCO clock
  312. because of better frequency stability.
  313. So first try r_max, then r smaller. */
  314. while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
  315. ar--;
  316. f_vco = f_vco >> 1;
  317. }
  318. /* VCO bounds check */
  319. if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
  320. return -EINVAL;
  321. delta_best = 0xFFFFFFFF;
  322. *m = 0;
  323. *n = 0;
  324. *r = ar;
  325. am = pll->m_min;
  326. an = pll->n_min;
  327. while ((am <= pll->m_max) && (an <= pll->n_max)) {
  328. f_current = (pll->f_base * am) / an;
  329. delta_current = abs_diff (f_current, f_vco);
  330. if (delta_current < delta_best) {
  331. delta_best = delta_current;
  332. *m = am;
  333. *n = an;
  334. }
  335. if (f_current <= f_vco) {
  336. am ++;
  337. } else {
  338. an ++;
  339. }
  340. }
  341. f_current = (pll->f_base * *m) / *n;
  342. pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int) (f_current >> ar), (int) f_current);
  343. pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int) *m, (unsigned int) *n, (unsigned int) *r);
  344. return 0;
  345. }
  346. /* ------------------------------------------------------------------------- */
  347. /* Check CRT timing values */
  348. int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node)
  349. {
  350. u32 value;
  351. var->xres = (var->xres+7)&~7;
  352. var->left_margin = (var->left_margin+7)&~7;
  353. var->right_margin = (var->right_margin+7)&~7;
  354. var->hsync_len = (var->hsync_len+7)&~7;
  355. /* Check horizontal total */
  356. value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
  357. if (((value / 8) - 5) >= svga_regset_size (tm->h_total_regs))
  358. return -EINVAL;
  359. /* Check horizontal display and blank start */
  360. value = var->xres;
  361. if (((value / 8) - 1) >= svga_regset_size (tm->h_display_regs))
  362. return -EINVAL;
  363. if (((value / 8) - 1) >= svga_regset_size (tm->h_blank_start_regs))
  364. return -EINVAL;
  365. /* Check horizontal sync start */
  366. value = var->xres + var->right_margin;
  367. if (((value / 8) - 1) >= svga_regset_size (tm->h_sync_start_regs))
  368. return -EINVAL;
  369. /* Check horizontal blank end (or length) */
  370. value = var->left_margin + var->right_margin + var->hsync_len;
  371. if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_blank_end_regs)))
  372. return -EINVAL;
  373. /* Check horizontal sync end (or length) */
  374. value = var->hsync_len;
  375. if ((value == 0) || ((value / 8) >= svga_regset_size (tm->h_sync_end_regs)))
  376. return -EINVAL;
  377. /* Check vertical total */
  378. value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
  379. if ((value - 1) >= svga_regset_size(tm->v_total_regs))
  380. return -EINVAL;
  381. /* Check vertical display and blank start */
  382. value = var->yres;
  383. if ((value - 1) >= svga_regset_size(tm->v_display_regs))
  384. return -EINVAL;
  385. if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs))
  386. return -EINVAL;
  387. /* Check vertical sync start */
  388. value = var->yres + var->lower_margin;
  389. if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs))
  390. return -EINVAL;
  391. /* Check vertical blank end (or length) */
  392. value = var->upper_margin + var->lower_margin + var->vsync_len;
  393. if ((value == 0) || (value >= svga_regset_size (tm->v_blank_end_regs)))
  394. return -EINVAL;
  395. /* Check vertical sync end (or length) */
  396. value = var->vsync_len;
  397. if ((value == 0) || (value >= svga_regset_size (tm->v_sync_end_regs)))
  398. return -EINVAL;
  399. return 0;
  400. }
  401. /* Set CRT timing registers */
  402. void svga_set_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var,
  403. u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
  404. {
  405. u8 regval;
  406. u32 value;
  407. value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
  408. value = (value * hmul) / hdiv;
  409. pr_debug("fb%d: horizontal total : %d\n", node, value);
  410. svga_wcrt_multi(tm->h_total_regs, (value / 8) - 5);
  411. value = var->xres;
  412. value = (value * hmul) / hdiv;
  413. pr_debug("fb%d: horizontal display : %d\n", node, value);
  414. svga_wcrt_multi(tm->h_display_regs, (value / 8) - 1);
  415. value = var->xres;
  416. value = (value * hmul) / hdiv;
  417. pr_debug("fb%d: horizontal blank start: %d\n", node, value);
  418. svga_wcrt_multi(tm->h_blank_start_regs, (value / 8) - 1 + hborder);
  419. value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
  420. value = (value * hmul) / hdiv;
  421. pr_debug("fb%d: horizontal blank end : %d\n", node, value);
  422. svga_wcrt_multi(tm->h_blank_end_regs, (value / 8) - 1 - hborder);
  423. value = var->xres + var->right_margin;
  424. value = (value * hmul) / hdiv;
  425. pr_debug("fb%d: horizontal sync start : %d\n", node, value);
  426. svga_wcrt_multi(tm->h_sync_start_regs, (value / 8));
  427. value = var->xres + var->right_margin + var->hsync_len;
  428. value = (value * hmul) / hdiv;
  429. pr_debug("fb%d: horizontal sync end : %d\n", node, value);
  430. svga_wcrt_multi(tm->h_sync_end_regs, (value / 8));
  431. value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
  432. value = (value * vmul) / vdiv;
  433. pr_debug("fb%d: vertical total : %d\n", node, value);
  434. svga_wcrt_multi(tm->v_total_regs, value - 2);
  435. value = var->yres;
  436. value = (value * vmul) / vdiv;
  437. pr_debug("fb%d: vertical display : %d\n", node, value);
  438. svga_wcrt_multi(tm->v_display_regs, value - 1);
  439. value = var->yres;
  440. value = (value * vmul) / vdiv;
  441. pr_debug("fb%d: vertical blank start : %d\n", node, value);
  442. svga_wcrt_multi(tm->v_blank_start_regs, value);
  443. value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
  444. value = (value * vmul) / vdiv;
  445. pr_debug("fb%d: vertical blank end : %d\n", node, value);
  446. svga_wcrt_multi(tm->v_blank_end_regs, value - 2);
  447. value = var->yres + var->lower_margin;
  448. value = (value * vmul) / vdiv;
  449. pr_debug("fb%d: vertical sync start : %d\n", node, value);
  450. svga_wcrt_multi(tm->v_sync_start_regs, value);
  451. value = var->yres + var->lower_margin + var->vsync_len;
  452. value = (value * vmul) / vdiv;
  453. pr_debug("fb%d: vertical sync end : %d\n", node, value);
  454. svga_wcrt_multi(tm->v_sync_end_regs, value);
  455. /* Set horizontal and vertical sync pulse polarity in misc register */
  456. regval = vga_r(NULL, VGA_MIS_R);
  457. if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
  458. pr_debug("fb%d: positive horizontal sync\n", node);
  459. regval = regval & ~0x80;
  460. } else {
  461. pr_debug("fb%d: negative horizontal sync\n", node);
  462. regval = regval | 0x80;
  463. }
  464. if (var->sync & FB_SYNC_VERT_HIGH_ACT) {
  465. pr_debug("fb%d: positive vertical sync\n", node);
  466. regval = regval & ~0x40;
  467. } else {
  468. pr_debug("fb%d: negative vertical sync\n\n", node);
  469. regval = regval | 0x40;
  470. }
  471. vga_w(NULL, VGA_MIS_W, regval);
  472. }
  473. /* ------------------------------------------------------------------------- */
  474. int svga_match_format(const struct svga_fb_format *frm, struct fb_var_screeninfo *var, struct fb_fix_screeninfo *fix)
  475. {
  476. int i = 0;
  477. while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL)
  478. {
  479. if ((var->bits_per_pixel == frm->bits_per_pixel) &&
  480. (var->red.length <= frm->red.length) &&
  481. (var->green.length <= frm->green.length) &&
  482. (var->blue.length <= frm->blue.length) &&
  483. (var->transp.length <= frm->transp.length) &&
  484. (var->nonstd == frm->nonstd)) {
  485. var->bits_per_pixel = frm->bits_per_pixel;
  486. var->red = frm->red;
  487. var->green = frm->green;
  488. var->blue = frm->blue;
  489. var->transp = frm->transp;
  490. var->nonstd = frm->nonstd;
  491. if (fix != NULL) {
  492. fix->type = frm->type;
  493. fix->type_aux = frm->type_aux;
  494. fix->visual = frm->visual;
  495. fix->xpanstep = frm->xpanstep;
  496. }
  497. return i;
  498. }
  499. i++;
  500. frm++;
  501. }
  502. return -EINVAL;
  503. }
  504. EXPORT_SYMBOL(svga_wcrt_multi);
  505. EXPORT_SYMBOL(svga_wseq_multi);
  506. EXPORT_SYMBOL(svga_set_default_gfx_regs);
  507. EXPORT_SYMBOL(svga_set_default_atc_regs);
  508. EXPORT_SYMBOL(svga_set_default_seq_regs);
  509. EXPORT_SYMBOL(svga_set_default_crt_regs);
  510. EXPORT_SYMBOL(svga_set_textmode_vga_regs);
  511. EXPORT_SYMBOL(svga_settile);
  512. EXPORT_SYMBOL(svga_tilecopy);
  513. EXPORT_SYMBOL(svga_tilefill);
  514. EXPORT_SYMBOL(svga_tileblit);
  515. EXPORT_SYMBOL(svga_tilecursor);
  516. EXPORT_SYMBOL(svga_compute_pll);
  517. EXPORT_SYMBOL(svga_check_timings);
  518. EXPORT_SYMBOL(svga_set_timings);
  519. EXPORT_SYMBOL(svga_match_format);
  520. MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>");
  521. MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards");
  522. MODULE_LICENSE("GPL");