s3c_lte480wv.c 56 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/errno.h>
  4. #include <linux/string.h>
  5. #include <linux/mm.h>
  6. #include <linux/tty.h>
  7. #include <linux/slab.h>
  8. #include <linux/delay.h>
  9. #include <linux/fb.h>
  10. #include <linux/init.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/string.h>
  13. #include <linux/ioctl.h>
  14. #include <linux/clk.h>
  15. #include <asm/io.h>
  16. #include <asm/uaccess.h>
  17. #include <asm/mach/map.h>
  18. #include <asm/arch/regs-lcd.h>
  19. #include <asm/arch/regs-gpio.h>
  20. #if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  21. #include <asm/arch/regs-s3c2450-clock.h>
  22. #elif defined(CONFIG_CPU_S3C6400)
  23. #include <asm/arch/regs-s3c6400-clock.h>
  24. #elif defined(CONFIG_CPU_S3C6410)
  25. #include <asm/arch/regs-s3c6410-clock.h>
  26. #endif
  27. #include "s3cfb.h"
  28. #define ON 1
  29. #define OFF 0
  30. #define DEFAULT_BACKLIGHT_LEVEL 2
  31. #define H_FP 8 /* front porch */
  32. #define H_SW 3 /* Hsync width */
  33. #define H_BP 13 /* Back porch */
  34. #define V_FP 5 /* front porch */
  35. #define V_SW 1 /* Vsync width */
  36. #define V_BP 7 /* Back porch */
  37. extern struct s3c_fb_info info[S3C_FB_NUM];
  38. s3c_win_info_t window_info;
  39. //------------------ Virtual Screen -----------------------
  40. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  41. vs_info_t vs_info;
  42. #define START_VIRTUAL_LCD 11
  43. #define STOP_VIRTUAL_LCD 10
  44. #define SET_VIRTUAL_LCD 12
  45. #define VS_MOVE_LEFT 15
  46. #define VS_MOVE_RIGHT 16
  47. #define VS_MOVE_UP 17
  48. #define VS_MOVE_DOWN 18
  49. #define MAX_DISPLAY_OFFSET 200
  50. #define DEF_DISPLAY_OFFSET 100
  51. int virtual_display_offset = DEF_DISPLAY_OFFSET;
  52. #endif
  53. //------------------ OSD (On Screen Display) -----------------------
  54. #define START_OSD 1
  55. #define STOP_OSD 0
  56. // QCIF OSD image
  57. #define H_RESOLUTION_OSD 800 /* horizon pixel x resolition */
  58. #define V_RESOLUTION_OSD 480 /* line cnt y resolution */
  59. #define ALPHA_UP 3
  60. #define ALPHA_DOWN 4
  61. #define MOVE_LEFT 5
  62. #define MOVE_RIGHT 6
  63. #define MOVE_UP 7
  64. #define MOVE_DOWN 8
  65. #define MAX_ALPHA_LEVEL 0x0f
  66. int osd_alpha_level = MAX_ALPHA_LEVEL;
  67. int osd_left_top_x = 0;
  68. int osd_left_top_y = 0;
  69. int osd_right_bottom_x = H_RESOLUTION_OSD-1;
  70. int osd_left_bottom_y = V_RESOLUTION_OSD -1;
  71. //------------------------------------------------------------------------
  72. #define H_RESOLUTION 800 /* horizon pixel x resolition */
  73. #define V_RESOLUTION 480 /* line cnt y resolution */
  74. #define H_RESOLUTION_VIRTUAL 800 /* horizon pixel x resolition */
  75. #define V_RESOLUTION_VIRTUAL 960 /* line cnt y resolution */
  76. #define VFRAME_FREQ 60 /* frame rate freq */
  77. #define PIXEL_BPP8 8
  78. #define PIXEL_BPP16 16 /* RGB 5-6-5 format for SMDK EVAL BOARD */
  79. #define PIXEL_BPP24 24 /* RGB 8-8-8 format for SMDK EVAL BOARD */
  80. #define LCD_PIXEL_CLOCK (VFRAME_FREQ *(H_FP+H_SW+H_BP+H_RESOLUTION) * (V_FP+V_SW+V_BP+V_RESOLUTION))
  81. #define PIXEL_CLOCK VFRAME_FREQ * LCD_PIXEL_CLOCK /* vclk = frame * pixel_count */
  82. #define MAX_DISPLAY_BRIGHTNESS 9
  83. #define DEF_DISPLAY_BRIGHTNESS 4
  84. int display_brightness = DEF_DISPLAY_BRIGHTNESS;
  85. void set_brightness(int);
  86. struct s3c_fb_mach_info mach_info = {
  87. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  88. .vidcon0= S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_VCLKEN_ENABLE |S3C_VIDCON0_CLKSEL_F_HCLK,
  89. .vidcon1= S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT,
  90. .vidtcon0= S3C_VIDTCON0_VBPD(V_BP-1) | S3C_VIDTCON0_VFPD(V_FP-1) | S3C_VIDTCON0_VSPW(V_SW-1),
  91. .vidtcon1= S3C_VIDTCON1_HBPD(H_BP-1) | S3C_VIDTCON1_HFPD(H_FP-1 ) | S3C_VIDTCON1_HSPW(H_SW-1),
  92. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  93. .vidcon0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_L1_DATA16_SUB_16_MODE
  94. | S3C_VIDCON0_L0_DATA16_MAIN_16_MODE | S3C_VIDCON0_PNRMODE_RGB_P
  95. | S3C_VIDCON0_CLKVALUP_ALWAYS | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_CLKSEL_F_HCLK |
  96. S3C_VIDCON0_ENVID_DISABLE | S3C_VIDCON0_ENVID_F_DISABLE,
  97. .vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT |S3C_VIDCON1_IVDEN_NORMAL,
  98. .vidtcon0 = S3C_VIDTCON0_VBPDE(0) | S3C_VIDTCON0_VBPD(V_BP-1) | S3C_VIDTCON0_VFPD(V_FP-1) | S3C_VIDTCON0_VSPW(V_SW-1),
  99. .vidtcon1 = S3C_VIDTCON1_VFPDE(0) | S3C_VIDTCON1_HBPD(H_BP-1) | S3C_VIDTCON1_HFPD(H_FP-1) | S3C_VIDTCON1_HSPW(H_SW-1),
  100. #endif
  101. .vidtcon2= S3C_VIDTCON2_LINEVAL(V_RESOLUTION-1) | S3C_VIDTCON2_HOZVAL(H_RESOLUTION-1),
  102. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  103. .dithmode = ( S3C_DITHMODE_RDITHPOS_5BIT |S3C_DITHMODE_GDITHPOS_6BIT | S3C_DITHMODE_BDITHPOS_5BIT ) & S3C_DITHMODE_DITHERING_DISABLE,
  104. #endif
  105. #if defined (CONFIG_FB_BPP_8)
  106. .wincon0= S3C_WINCONx_BYTSWP_ENABLE |S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL, // 4word burst, 8bpp-palletized,
  107. .wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  108. //.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_A555 | S3C_WINCONx_BLD_PIX_PIXEL| S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  109. #elif defined (CONFIG_FB_BPP_16)
  110. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  111. .wincon0= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565, // 4word burst, 16bpp,
  112. .wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  113. //.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_A555 | S3C_WINCONx_BLD_PIX_PIXEL| S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  114. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  115. // .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  116. .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_1 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  117. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  118. S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  119. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  120. //S3C_WINCONx_BUFAUTOEN_ENABLE |
  121. #endif
  122. S3C_WINCONx_ENWIN_F_DISABLE, // 4word burst, 16bpp,
  123. .wincon1 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  124. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE |
  125. S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  126. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  127. //S3C_WINCONx_BUFAUTOEN_ENABLE |
  128. #endif
  129. S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, // 4word burst, 16bpp,
  130. .wincon2 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BITSWP_DISABLE |
  131. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  132. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  133. S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  134. .wincon3 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE |
  135. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE |
  136. S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  137. .wincon4 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  138. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE |
  139. S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  140. #endif
  141. #elif defined (CONFIG_FB_BPP_24)
  142. .wincon0= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888, // 4word burst, 24bpp,
  143. .wincon1= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 24bpp for OSD
  144. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  145. .wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  146. .wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  147. .wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  148. #endif
  149. #endif
  150. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  151. .vidosd0a= S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  152. .vidosd0b= S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION-1),
  153. .vidosd1a= S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  154. .vidosd1b= S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  155. .vidosd1c= S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  156. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  157. .vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  158. .vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION-1),
  159. .vidosd0c = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  160. .vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  161. .vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  162. .vidosd1c= S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  163. .vidosd1d = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  164. .vidosd2a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  165. .vidosd2b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  166. .vidosd2c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  167. .vidosd2d = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  168. .vidosd3a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  169. .vidosd3b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  170. .vidosd3c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  171. .vidosd4a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  172. .vidosd4b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  173. .vidosd4c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  174. #endif
  175. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  176. .vidintcon= S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_ENABLE | S3C_VIDINTCON0_INTEN_ENABLE,
  177. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  178. // .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_BACK | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_DISABLE,
  179. .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_ENABLE,
  180. .vidintcon1 = 0,
  181. #endif
  182. .width= H_RESOLUTION,
  183. .height= V_RESOLUTION,
  184. .xres= H_RESOLUTION,
  185. .yres= V_RESOLUTION,
  186. .xoffset= 0,
  187. .yoffset= 0,
  188. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  189. .xres_virtual = H_RESOLUTION_VIRTUAL,
  190. .yres_virtual = V_RESOLUTION_VIRTUAL,
  191. #else
  192. .xres_virtual = H_RESOLUTION,
  193. .yres_virtual = V_RESOLUTION,
  194. #endif
  195. .osd_width= H_RESOLUTION_OSD,
  196. .osd_height= V_RESOLUTION_OSD,
  197. .osd_xres= H_RESOLUTION_OSD,
  198. .osd_yres= V_RESOLUTION_OSD,
  199. .osd_xres_virtual= H_RESOLUTION_OSD,
  200. .osd_yres_virtual= V_RESOLUTION_OSD,
  201. #if defined (CONFIG_FB_BPP_8)
  202. .bpp= PIXEL_BPP8,
  203. .bytes_per_pixel= 1,
  204. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  205. .wpalcon= W0PAL_24BIT,
  206. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  207. .wpalcon= W0PAL_16BIT,
  208. #endif
  209. #elif defined (CONFIG_FB_BPP_16)
  210. .bpp= PIXEL_BPP16,
  211. .bytes_per_pixel= 2,
  212. #elif defined (CONFIG_FB_BPP_24)
  213. .bpp= PIXEL_BPP24,
  214. .bytes_per_pixel= 4,
  215. #endif
  216. .pixclock= PIXEL_CLOCK,
  217. .w1keycon0= S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE |
  218. S3C_WxKEYCON0_COMPKEY(0x0),
  219. .w1keycon1= S3C_WxKEYCON1_COLVAL(0xffffff),
  220. .w2keycon0= S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE |
  221. S3C_WxKEYCON0_COMPKEY(0x0),
  222. .w2keycon1= S3C_WxKEYCON1_COLVAL(0xffffff),
  223. .w3keycon0= S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE |
  224. S3C_WxKEYCON0_COMPKEY(0x0),
  225. .w3keycon1= S3C_WxKEYCON1_COLVAL(0xffffff),
  226. .w4keycon0= S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE |
  227. S3C_WxKEYCON0_COMPKEY(0x0),
  228. .w4keycon1= S3C_WxKEYCON1_COLVAL(0xffffff),
  229. .hsync_len= H_SW,
  230. .vsync_len= V_SW,
  231. .left_margin= H_FP,
  232. .upper_margin= V_FP,
  233. .right_margin= H_BP,
  234. .lower_margin= V_BP,
  235. .sync= 0,
  236. .cmap_static= 1,
  237. };
  238. #if defined(CONFIG_S3C6400_PWM) || defined(CONFIG_S3C2450_PWM) || defined(CONFIG_S3C2416_PWM)
  239. void set_brightness(int val)
  240. {
  241. #if defined(CONFIG_S3C6400_PWM)
  242. int channel = 1; // must use channel-1
  243. #elif defined(CONFIG_S3C2450_PWM) || defined(CONFIG_S3C2416_PWM)
  244. int channel = 3; // must use channel-3
  245. #endif
  246. int usec = 0; // don't care value
  247. unsigned long tcnt=1000;
  248. unsigned long tcmp=0;
  249. if(val < 0) val=0;
  250. if(val > MAX_DISPLAY_BRIGHTNESS) val=MAX_DISPLAY_BRIGHTNESS;
  251. display_brightness = val;
  252. switch (val) {
  253. case 0:
  254. tcmp= 0;
  255. break;
  256. case 1:
  257. tcmp= 50;
  258. break;
  259. case 2:
  260. tcmp= 100;
  261. break;
  262. case 3:
  263. tcmp= 150;
  264. break;
  265. case 4:
  266. tcmp= 200;
  267. break;
  268. case 5:
  269. tcmp= 250;
  270. break;
  271. case 6:
  272. tcmp= 300;
  273. break;
  274. case 7:
  275. tcmp= 350;
  276. break;
  277. case 8:
  278. tcmp= 400;
  279. break;
  280. case 9:
  281. tcmp= 450;
  282. break;
  283. } // end of switch (level)
  284. #if defined(CONFIG_S3C6400_PWM)
  285. s3c6400_timer_setup (channel, usec, tcnt, tcmp);
  286. #else
  287. s3c2450_timer_setup (channel, usec, tcnt, tcmp);
  288. #endif
  289. }
  290. #endif
  291. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  292. void set_virtual_display_offset(int val)
  293. {
  294. if(val < 1)
  295. val = 1;
  296. if(val > MAX_DISPLAY_OFFSET)
  297. val = MAX_DISPLAY_OFFSET;
  298. virtual_display_offset = val;
  299. }
  300. int set_vs_info(vs_info_t vs_info_from_app )
  301. {
  302. /* check invalid value */
  303. if(vs_info_from_app.width != H_RESOLUTION || vs_info_from_app.height != V_RESOLUTION ){
  304. return 1;
  305. }
  306. if(!(vs_info_from_app.bpp==8 ||vs_info_from_app.bpp==16 ||vs_info_from_app.bpp==24 || vs_info_from_app.bpp==32) ){
  307. return 1;
  308. }
  309. if(vs_info_from_app.offset<0){
  310. return 1;
  311. }
  312. if(vs_info_from_app.v_width != H_RESOLUTION_VIRTUAL || vs_info_from_app.v_height != V_RESOLUTION_VIRTUAL){
  313. return 1;
  314. }
  315. /* save virtual screen information */
  316. vs_info = vs_info_from_app;
  317. set_virtual_display_offset(vs_info.offset);
  318. return 0;
  319. }
  320. int set_virtual_display_register(int vs_cmd)
  321. {
  322. int PageWidth, Offset;
  323. int ShiftValue;
  324. PageWidth = mach_info.xres * mach_info.bytes_per_pixel;
  325. Offset = (mach_info.xres_virtual - mach_info.xres) * mach_info.bytes_per_pixel;
  326. switch(vs_cmd){
  327. case SET_VIRTUAL_LCD:
  328. /* size of buffer */
  329. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  330. mach_info.vidw00add2b0 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  331. mach_info.vidw00add2b1 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  332. __raw_writel(mach_info.vidw00add2b0, S3C_VIDW00ADD2B0);
  333. __raw_writel(mach_info.vidw00add2b1, S3C_VIDW00ADD2B1);
  334. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  335. mach_info.vidw00add2 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  336. __raw_writel(mach_info.vidw00add2, S3C_VIDW00ADD2);
  337. #endif
  338. break;
  339. case VS_MOVE_LEFT:
  340. if(mach_info.xoffset < virtual_display_offset){
  341. ShiftValue = mach_info.xoffset;
  342. }
  343. else ShiftValue = virtual_display_offset;
  344. mach_info.xoffset -= ShiftValue;
  345. /* For buffer start address */
  346. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 - ShiftValue*mach_info.bytes_per_pixel;
  347. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 - ShiftValue*mach_info.bytes_per_pixel;
  348. break;
  349. case VS_MOVE_RIGHT:
  350. if((vs_info.v_width - (mach_info.xoffset + vs_info.width) )< (virtual_display_offset)){
  351. ShiftValue = vs_info.v_width - (mach_info.xoffset + vs_info.width);
  352. }
  353. else ShiftValue = virtual_display_offset;
  354. mach_info.xoffset += ShiftValue;
  355. /* For buffer start address */
  356. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 + ShiftValue*mach_info.bytes_per_pixel;
  357. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 + ShiftValue*mach_info.bytes_per_pixel;
  358. break;
  359. case VS_MOVE_UP:
  360. if(mach_info.yoffset < virtual_display_offset){
  361. ShiftValue = mach_info.yoffset;
  362. }
  363. else ShiftValue = virtual_display_offset;
  364. mach_info.yoffset -= ShiftValue;
  365. /* For buffer start address */
  366. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 - ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  367. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 - ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  368. break;
  369. case VS_MOVE_DOWN:
  370. if((vs_info.v_height - (mach_info.yoffset + vs_info.height) )< (virtual_display_offset)){
  371. ShiftValue = vs_info.v_height - (mach_info.yoffset + vs_info.height);
  372. }
  373. else ShiftValue = virtual_display_offset;
  374. mach_info.yoffset += ShiftValue;
  375. /* For buffer start address */
  376. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 + ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  377. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 + ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  378. break;
  379. default:
  380. return -EINVAL;
  381. }
  382. /* End address */
  383. mach_info.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F(mach_info.vidw00add0b0 + (PageWidth + Offset) * (mach_info.yres));
  384. mach_info.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F(mach_info.vidw00add0b1 + (PageWidth + Offset) * (mach_info.yres));
  385. __raw_writel(mach_info.vidw00add0b0, S3C_VIDW00ADD0B0);
  386. __raw_writel(mach_info.vidw00add0b1, S3C_VIDW00ADD0B1);
  387. __raw_writel(mach_info.vidw00add1b0, S3C_VIDW00ADD1B0);
  388. __raw_writel(mach_info.vidw00add1b1, S3C_VIDW00ADD1B1);
  389. return 0;
  390. }
  391. #endif
  392. /*
  393. * As LCD-Brightness is best related to Display and hence FrameBuffer,
  394. * so we put the brightness control in /dev/fb.
  395. */
  396. #define GET_DISPLAY_BRIGHTNESS _IOR('F', 1, u_int) /* get brightness */
  397. #define SET_DISPLAY_BRIGHTNESS _IOW('F', 2, u_int) /* set brightness */
  398. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  399. #define SET_VS_START _IO('F', 103)
  400. #define SET_VS_STOP _IO('F', 104)
  401. #define SET_VS_INFO _IOW('F', 105, vs_info_t)
  402. #define SET_VS_MOVE _IOW('F', 106, u_int)
  403. #endif
  404. #define SET_OSD_START _IO('F', 201)
  405. #define SET_OSD_STOP _IO('F', 202)
  406. #define SET_OSD_ALPHA_UP _IO('F', 203)
  407. #define SET_OSD_ALPHA_DOWN _IO('F', 204)
  408. #define SET_OSD_MOVE_LEFT _IO('F', 205)
  409. #define SET_OSD_MOVE_RIGHT _IO('F', 206)
  410. #define SET_OSD_MOVE_UP _IO('F', 207)
  411. #define SET_OSD_MOVE_DOWN _IO('F', 208)
  412. #define SET_OSD_INFO _IOW('F', 209, s3c_win_info_t)
  413. #if 0
  414. #define SET_OSD_BRIGHT _IOW('F', 210, int)
  415. #endif
  416. #define SET_COLOR_KEY_START _IO('F', 300)
  417. #define SET_COLOR_KEY_STOP _IO('F', 301)
  418. #define SET_COLOR_KEY_ALPHA_START _IO('F', 302)
  419. #define SET_COLOR_KEY_ALPHA_STOP _IO('F', 303)
  420. #define SET_COLOR_KEY_INFO _IOW('F', 304, s3c_color_key_info_t)
  421. #define SET_COLOR_KEY_COLVAL _IOW('F', 305, s3c_color_val_info_t)
  422. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  423. #define GET_FB_NUM _IOWR('F', 306, u_int)
  424. #endif
  425. #if defined(CONFIG_G3D)
  426. #define S3C_FBIO_CHANGE_FB _IOW('F', 81,int)
  427. #endif
  428. #define GET_FB_INFO _IOR('F', 307, struct s3c_fb_dma_info)
  429. #define SET_FB_CHANGE_REQ _IOW('F', 308, int)
  430. #define SET_VSYNC_INT _IOW('F', 309, int)
  431. #define VIRT_TO_PHYS _IOWR('F', 310, u_int)
  432. int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  433. {
  434. struct s3c_fb_info *fbi = container_of(info, struct s3c_fb_info, fb);
  435. struct fb_var_screeninfo *var= &fbi->fb.var;
  436. struct s3c_fb_dma_info dma_info;
  437. struct vm_area_struct *tvma;
  438. struct page *tpage;
  439. u_int virt_addr, phys_addr, offset;
  440. struct mm_struct *mm = current->mm;
  441. #if defined(CONFIG_G3D)
  442. int value;
  443. int sizeof_fb;
  444. unsigned int start1;
  445. unsigned int end1;
  446. unsigned int start2;
  447. unsigned int end2;
  448. unsigned int start3;
  449. unsigned int end3;
  450. unsigned int TargetFBStartReg;
  451. unsigned int TargetFBEndReg;
  452. unsigned int TargetFBSel;
  453. int currentDrawing;
  454. #endif
  455. int brightness;
  456. s3c_win_info_t win_info_from_app;
  457. s3c_color_key_info_t colkey_info;
  458. s3c_color_val_info_t colval_info;
  459. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  460. u_int f_num_val;
  461. #endif
  462. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  463. vs_info_t vs_info_from_app;
  464. #endif
  465. switch(cmd){
  466. case VIRT_TO_PHYS:
  467. if(copy_from_user((void *)&virt_addr, (const void *)arg, sizeof(u_int)))
  468. return -EFAULT;
  469. //printk("\n KERNEL : virt addr = 0x%p\n", virt_addr);
  470. offset = virt_addr & ~PAGE_MASK;
  471. //printk(" KERNEL : offset = 0x%x\n", offset);
  472. tvma = find_vma(mm, virt_addr);
  473. if (tvma->vm_start <= mm->start_brk && tvma->vm_end >= mm->brk) {
  474. printk("This virt address is on heap !\n");
  475. //printk("heap start :0x%p !\n", mm->start_brk);
  476. //printk("heap end :0x%p !\n", mm->brk);
  477. }
  478. tpage = follow_page(tvma, virt_addr, FOLL_GET);
  479. phys_addr = (page_to_pfn(tpage) << PAGE_SHIFT) + offset;
  480. //printk(" KERNEL : phys addr: %p \n", phys_addr);
  481. if(copy_to_user((void *)arg, (const void *) &phys_addr, sizeof(u_int)))
  482. return -EFAULT;
  483. return phys_addr;
  484. case GET_FB_INFO:
  485. dma_info.map_dma_f1 = fbi->map_dma_f1;
  486. dma_info.map_dma_f2 = fbi->map_dma_f2;
  487. if(copy_to_user((void *) arg, (const void *) &dma_info, sizeof(struct s3c_fb_dma_info)))
  488. return -EFAULT;
  489. break;
  490. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  491. case SET_VSYNC_INT:
  492. mach_info.vidintcon0 &= ~S3C_VIDINTCON0_FRAMESEL0_MASK;
  493. mach_info.vidintcon0 |= S3C_VIDINTCON0_FRAMESEL0_VSYNC;
  494. if (arg)
  495. mach_info.vidintcon0 |= S3C_VIDINTCON0_INTFRMEN_ENABLE;
  496. else
  497. mach_info.vidintcon0 &= ~S3C_VIDINTCON0_INTFRMEN_ENABLE;
  498. __raw_writel(mach_info.vidintcon0, S3C_VIDINTCON0);
  499. break;
  500. #endif
  501. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  502. case SET_VS_START:
  503. mach_info.wincon0 &= ~(S3C_WINCONx_ENWIN_F_ENABLE);
  504. __raw_writel(mach_info.wincon0|S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
  505. fbi->fb.var.xoffset = mach_info.xoffset;
  506. fbi->fb.var.yoffset = mach_info.yoffset;
  507. break;
  508. case SET_VS_STOP:
  509. break;
  510. case SET_VS_INFO:
  511. if(copy_from_user(&vs_info_from_app, (vs_info_t *) arg, sizeof(vs_info_t)))
  512. return -EFAULT;
  513. if(set_vs_info(vs_info_from_app)){
  514. printk("Error SET_VS_INFO\n");
  515. return -EINVAL;
  516. }
  517. set_virtual_display_register(SET_VIRTUAL_LCD);
  518. fbi->fb.var.xoffset = mach_info.xoffset;
  519. fbi->fb.var.yoffset = mach_info.yoffset;
  520. break;
  521. case SET_VS_MOVE:
  522. set_virtual_display_register(arg);
  523. fbi->fb.var.xoffset = mach_info.xoffset;
  524. fbi->fb.var.yoffset = mach_info.yoffset;
  525. break;
  526. #endif
  527. case SET_OSD_INFO :
  528. if(copy_from_user
  529. (&win_info_from_app, (s3c_win_info_t *) arg,
  530. sizeof(s3c_win_info_t)))
  531. return -EFAULT;
  532. s3c_fb_init_win(fbi, win_info_from_app.Bpp,
  533. win_info_from_app.LeftTop_x, win_info_from_app.LeftTop_y, win_info_from_app.Width, win_info_from_app.Height, OFF);
  534. break;
  535. case SET_OSD_START :
  536. s3c_fb_win_onoff(fbi, ON); // on
  537. break;
  538. case SET_OSD_STOP:
  539. s3c_fb_win_onoff(fbi, OFF); // off
  540. break;
  541. case SET_OSD_ALPHA_UP:
  542. if(osd_alpha_level < MAX_ALPHA_LEVEL) osd_alpha_level ++;
  543. s3c_fb_set_alpha_level(fbi);
  544. break;
  545. case SET_OSD_ALPHA_DOWN:
  546. if(osd_alpha_level > 0) osd_alpha_level --;
  547. s3c_fb_set_alpha_level(fbi);
  548. break;
  549. case SET_OSD_MOVE_LEFT:
  550. if(var->xoffset>0) var->xoffset--;
  551. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  552. break;
  553. case SET_OSD_MOVE_RIGHT:
  554. if(var->xoffset < (H_RESOLUTION - var->xres)) var->xoffset ++;
  555. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  556. break;
  557. case SET_OSD_MOVE_UP:
  558. if(var->yoffset>0) var->yoffset--;
  559. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  560. break;
  561. case SET_OSD_MOVE_DOWN:
  562. if(var->yoffset < (V_RESOLUTION - var->yres)) var->yoffset ++;
  563. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  564. break;
  565. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  566. case GET_FB_NUM:
  567. if(copy_from_user((void *)&f_num_val, (const void *)arg, sizeof(u_int)))
  568. return -EFAULT;
  569. if(copy_to_user((void *)arg, (const void *) &f_num_val, sizeof(u_int)))
  570. return -EFAULT;
  571. break;
  572. case SET_FB_CHANGE_REQ:
  573. s3c_fb_change_buff(0, (int) arg);
  574. break;
  575. #endif
  576. #if defined(CONFIG_G3D)
  577. case S3C_FBIO_CHANGE_FB:
  578. if (copy_from_user(&value, (__user void *)arg, sizeof(int)))
  579. return(-EFAULT);
  580. currentDrawing = __raw_readl(S3C_WINCON0);
  581. currentDrawing = currentDrawing & (1<<20);
  582. sizeof_fb = var->xres_virtual * var->yres_virtual * mach_info.bytes_per_pixel;
  583. start1 = (unsigned int)fbi->map_dma_f1;
  584. end1 = (start1+(unsigned int)sizeof_fb)&0x00ffffff;
  585. start2 = (unsigned int)fbi->map_dma_f1+sizeof_fb;
  586. end2 = (start2+(unsigned int)sizeof_fb)&0x00ffffff;
  587. start3 = (unsigned int)fbi->map_dma_f1+sizeof_fb+sizeof_fb;
  588. end3 = (start3+(unsigned int)sizeof_fb)&0x00ffffff;
  589. if(currentDrawing!=0)
  590. {
  591. TargetFBStartReg=S3C_VIDW00ADD0B0;
  592. TargetFBEndReg=S3C_VIDW00ADD1B0;
  593. TargetFBSel =__raw_readl(S3C_WINCON0);
  594. TargetFBSel = TargetFBSel & ~(1<<20);
  595. }
  596. else
  597. {
  598. TargetFBStartReg=S3C_VIDW00ADD0B1;
  599. TargetFBEndReg=S3C_VIDW00ADD1B1;
  600. TargetFBSel =__raw_readl(S3C_WINCON0);
  601. TargetFBSel = TargetFBSel | (1<<20);
  602. }
  603. if(value==0)
  604. {
  605. // printk("s3c_fb set fb0 Saddr=0x%x Eaddr=0x%x\n",start1,end1);
  606. __raw_writel(start1,TargetFBStartReg);
  607. __raw_writel(end1,TargetFBEndReg);
  608. __raw_writel(TargetFBSel,S3C_WINCON0);
  609. }
  610. else if(value==1)
  611. {
  612. // printk("s3c_fb set fb1 Saddr=0x%x Eaddr=0x%x\n",start2,end2);
  613. __raw_writel(start2,TargetFBStartReg);
  614. __raw_writel(end2,TargetFBEndReg);
  615. __raw_writel(TargetFBSel,S3C_WINCON0);
  616. }
  617. else
  618. {
  619. // printk("s3c_fb set fb2 Saddr=0x%x Eaddr=0x%x\n",start3,end3);
  620. __raw_writel(start3,TargetFBStartReg);
  621. __raw_writel(end3,TargetFBEndReg);
  622. __raw_writel(TargetFBSel,S3C_WINCON0);
  623. }
  624. break;
  625. #endif
  626. case SET_DISPLAY_BRIGHTNESS:
  627. if(copy_from_user(&brightness, (int *) arg, sizeof(int)))
  628. return -EFAULT;
  629. #if defined(CONFIG_S3C6400_PWM) || defined(CONFIG_S3C2450_PWM) || defined(CONFIG_S3C2416_PWM)
  630. set_brightness(brightness);
  631. #endif
  632. break;
  633. case GET_DISPLAY_BRIGHTNESS:
  634. if(copy_to_user((void *)arg, (const void *) &display_brightness, sizeof(int)))
  635. return -EFAULT;
  636. break;
  637. //(WAITFORVSYNC)
  638. case FBIO_WAITFORVSYNC:
  639. {
  640. u_int32_t crt;
  641. if (get_user(crt, (u_int32_t __user *)arg))
  642. return -EFAULT;
  643. return s3cfb_wait_for_sync(crt);
  644. }
  645. //(WAITFORVSYNC)
  646. case SET_COLOR_KEY_START:
  647. s3c_fb_color_key_onoff(fbi, ON);
  648. break;
  649. case SET_COLOR_KEY_STOP:
  650. s3c_fb_color_key_onoff(fbi, OFF);
  651. break;
  652. case SET_COLOR_KEY_ALPHA_START:
  653. s3c_fb_color_key_alpha_onoff(fbi, ON);
  654. break;
  655. case SET_COLOR_KEY_ALPHA_STOP:
  656. s3c_fb_color_key_alpha_onoff(fbi, OFF);
  657. break;
  658. case SET_COLOR_KEY_INFO:
  659. if(copy_from_user(&colkey_info, (s3c_color_key_info_t *) arg,
  660. sizeof(s3c_color_key_info_t)))
  661. return -EFAULT;
  662. s3c_fb_setup_color_key_register(fbi, colkey_info);
  663. break;
  664. case SET_COLOR_KEY_COLVAL:
  665. if(copy_from_user(&colval_info, (s3c_color_val_info_t *) arg,
  666. sizeof(s3c_color_val_info_t)))
  667. return -EFAULT;
  668. s3c_fb_set_color_value(fbi, colval_info);
  669. break;
  670. default:
  671. return -EINVAL;
  672. }
  673. return 0;
  674. }
  675. /*
  676. * s3c_fb_map_video_memory():
  677. * Allocates the DRAM memory for the frame buffer. This buffer is
  678. * remapped into a non-cached, non-buffered, memory region to
  679. * allow palette and pixel writes to occur without flushing the
  680. * cache. Once this area is remapped, all virtual memory
  681. * access to the video memory should occur at the new region.
  682. */
  683. int __init s3c_fb_map_video_memory(struct s3c_fb_info *fbi)
  684. {
  685. dprintk("map_video_memory(fbi=%p)\n", fbi);
  686. fbi->map_size_f1 = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
  687. fbi->map_cpu_f1 = dma_alloc_writecombine(fbi->dev, fbi->map_size_f1,
  688. &fbi->map_dma_f1, GFP_KERNEL);
  689. fbi->map_size_f1 = fbi->fb.fix.smem_len;
  690. if (fbi->map_cpu_f1) {
  691. /* prevent initial garbage on screen */
  692. printk("Window[%d]- FB1 : map_video_memory: clear %p:%08x\n",
  693. fbi->win_id, fbi->map_cpu_f1, fbi->map_size_f1);
  694. memset(fbi->map_cpu_f1, 0xf0, fbi->map_size_f1);
  695. fbi->screen_dma_f1 = fbi->map_dma_f1;
  696. fbi->fb.screen_base = fbi->map_cpu_f1;
  697. fbi->fb.fix.smem_start = fbi->screen_dma_f1;
  698. printk(" FB1 : map_video_memory: dma=%08x cpu=%p size=%08x\n",
  699. fbi->map_dma_f1, fbi->map_cpu_f1, fbi->fb.fix.smem_len);
  700. }
  701. if( !fbi->map_cpu_f1)
  702. return -ENOMEM;
  703. //#if !defined(CONFIG_FB_VIRTUAL_SCREEN) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  704. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  705. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  706. if(fbi->win_id<1){ // WIN0 support double-buffer
  707. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  708. if(fbi->win_id<2){ // WIN0, WIN1 support double-buffer
  709. #endif
  710. fbi->map_size_f2 = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
  711. fbi->map_cpu_f2 = dma_alloc_writecombine(fbi->dev, fbi->map_size_f2,
  712. &fbi->map_dma_f2, GFP_KERNEL);
  713. fbi->map_size_f2 = fbi->fb.fix.smem_len;
  714. if (fbi->map_cpu_f2) {
  715. /* prevent initial garbage on screen */
  716. printk("Window[%d] - FB2 : map_video_memory: clear %p:%08x\n",
  717. fbi->win_id, fbi->map_cpu_f2, fbi->map_size_f2);
  718. memset(fbi->map_cpu_f2, 0xf0, fbi->map_size_f2);
  719. fbi->screen_dma_f2 = fbi->map_dma_f2;
  720. printk(" FB2 : map_video_memory: dma=%08x cpu=%p size=%08x\n",
  721. fbi->map_dma_f2, fbi->map_cpu_f2, fbi->fb.fix.smem_len);
  722. }
  723. if( !fbi->map_cpu_f2)
  724. return -ENOMEM;
  725. }
  726. #endif
  727. return 0;
  728. }
  729. void s3c_fb_unmap_video_memory(struct s3c_fb_info *fbi)
  730. {
  731. dma_free_writecombine(fbi->dev, fbi->map_size_f1, fbi->map_cpu_f1, fbi->map_dma_f1);
  732. //#if !defined(CONFIG_FB_VIRTUAL_SCREEN) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  733. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  734. dma_free_writecombine(fbi->dev, fbi->map_size_f2, fbi->map_cpu_f2, fbi->map_dma_f2);
  735. #endif
  736. }
  737. /*
  738. * s3c_fb_init_registers - Initialise all LCD-related registers
  739. */
  740. int s3c_fb_init_registers(struct s3c_fb_info *fbi)
  741. {
  742. u_long flags = 0;
  743. u_long PageWidth = 0, Offset = 0;
  744. int win_num = fbi->win_id;
  745. struct clk *lcd_clock;
  746. struct fb_var_screeninfo *var= &fbi->fb.var;
  747. unsigned long VideoPhysicalTemp_f1 = fbi->screen_dma_f1;
  748. unsigned long VideoPhysicalTemp_f2 = fbi->screen_dma_f2;
  749. /* Initialise LCD with values from hare */
  750. local_irq_save(flags);
  751. if(win_num==0){
  752. mach_info.vidcon0 = mach_info.vidcon0 & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE);
  753. __raw_writel(mach_info.vidcon0, S3C_VIDCON0);
  754. lcd_clock = clk_get(NULL, "lcd");
  755. mach_info.vidcon0 |= S3C_VIDCON0_CLKVAL_F((int)((clk_get_rate(lcd_clock) / LCD_PIXEL_CLOCK) - 1));
  756. }
  757. /* For buffer start address */
  758. __raw_writel(VideoPhysicalTemp_f1, S3C_VIDW00ADD0B0+(0x08*win_num));
  759. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  760. if(win_num==0) __raw_writel(VideoPhysicalTemp_f2, S3C_VIDW00ADD0B1);
  761. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  762. if(win_num<2) __raw_writel(VideoPhysicalTemp_f2, S3C_VIDW00ADD0B1+(0x08*win_num));
  763. #endif
  764. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  765. if(win_num==0){
  766. mach_info.vidw00add0b0=VideoPhysicalTemp_f1;
  767. mach_info.vidw00add0b1=VideoPhysicalTemp_f2;
  768. }
  769. #endif
  770. PageWidth = var->xres * mach_info.bytes_per_pixel;
  771. Offset = (var->xres_virtual - var->xres) * mach_info.bytes_per_pixel;
  772. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  773. if(win_num==0) Offset=0;
  774. #endif
  775. /* End address */
  776. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f1 + (PageWidth + Offset) * (var->yres)),
  777. S3C_VIDW00ADD1B0+(0x08*win_num));
  778. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  779. if(win_num==0)
  780. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres)),
  781. S3C_VIDW00ADD1B1);
  782. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  783. if(win_num<2)
  784. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres)),
  785. S3C_VIDW00ADD1B1+(0x08*win_num));
  786. #endif
  787. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  788. if(win_num==0){
  789. mach_info.vidw00add1b0=S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f1 + (PageWidth + Offset) * (var->yres));
  790. mach_info.vidw00add1b1=S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres));
  791. }
  792. #endif
  793. /* size of buffer */
  794. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  795. __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2B0+(0x08*win_num));
  796. if(win_num==0) __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2B1);
  797. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  798. __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2+(0x04*win_num));
  799. #endif
  800. switch(win_num){
  801. case 0:
  802. __raw_writel(mach_info.wincon0, S3C_WINCON0);
  803. __raw_writel(mach_info.vidcon0, S3C_VIDCON0);
  804. __raw_writel(mach_info.vidcon1, S3C_VIDCON1);
  805. __raw_writel(mach_info.vidtcon0, S3C_VIDTCON0);
  806. __raw_writel(mach_info.vidtcon1, S3C_VIDTCON1);
  807. __raw_writel(mach_info.vidtcon2, S3C_VIDTCON2);
  808. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  809. __raw_writel(mach_info.vidintcon, S3C_VIDINTCON);
  810. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  811. __raw_writel(mach_info.dithmode, S3C_DITHMODE);
  812. __raw_writel(mach_info.vidintcon0, S3C_VIDINTCON0);
  813. __raw_writel(mach_info.vidintcon1, S3C_VIDINTCON1);
  814. #endif
  815. __raw_writel(mach_info.vidosd0a, S3C_VIDOSD0A);
  816. __raw_writel(mach_info.vidosd0b, S3C_VIDOSD0B);
  817. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  818. __raw_writel(mach_info.vidosd0c, S3C_VIDOSD0C);
  819. #endif
  820. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  821. s3c_fb_win_onoff(fbi, ON);
  822. break;
  823. case 1:
  824. __raw_writel(mach_info.wincon1, S3C_WINCON1);
  825. __raw_writel(mach_info.vidosd1a, S3C_VIDOSD1A);
  826. __raw_writel(mach_info.vidosd1b, S3C_VIDOSD1B);
  827. __raw_writel(mach_info.vidosd1c, S3C_VIDOSD1C);
  828. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  829. __raw_writel(mach_info.vidosd1d, S3C_VIDOSD1D);
  830. #endif
  831. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  832. s3c_fb_win_onoff(fbi, OFF);
  833. break;
  834. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  835. case 2:
  836. __raw_writel(mach_info.wincon2, S3C_WINCON2);
  837. __raw_writel(mach_info.vidosd2a, S3C_VIDOSD2A);
  838. __raw_writel(mach_info.vidosd2b, S3C_VIDOSD2B);
  839. __raw_writel(mach_info.vidosd2c, S3C_VIDOSD2C);
  840. __raw_writel(mach_info.vidosd2d, S3C_VIDOSD2D);
  841. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  842. s3c_fb_win_onoff(fbi, OFF);
  843. break;
  844. case 3:
  845. __raw_writel(mach_info.wincon3, S3C_WINCON3);
  846. __raw_writel(mach_info.vidosd3a, S3C_VIDOSD3A);
  847. __raw_writel(mach_info.vidosd3b, S3C_VIDOSD3B);
  848. __raw_writel(mach_info.vidosd3c, S3C_VIDOSD3C);
  849. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  850. s3c_fb_win_onoff(fbi, OFF);
  851. break;
  852. case 4:
  853. __raw_writel(mach_info.wincon4, S3C_WINCON4);
  854. __raw_writel(mach_info.vidosd4a, S3C_VIDOSD4A);
  855. __raw_writel(mach_info.vidosd4b, S3C_VIDOSD4B);
  856. __raw_writel(mach_info.vidosd4c, S3C_VIDOSD4C);
  857. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  858. s3c_fb_win_onoff(fbi, OFF);
  859. break;
  860. #endif
  861. }
  862. local_irq_restore(flags);
  863. return 0;
  864. }
  865. /* s3c_fb_set_lcdaddr
  866. *
  867. * initialise lcd controller address pointers
  868. */
  869. void s3c_fb_set_lcdaddr(struct s3c_fb_info *fbi)
  870. {
  871. u32 start;
  872. unsigned long VideoPhysicalTemp_f1 = fbi->screen_dma_f1;
  873. start = fbi->fb.fix.line_length * fbi->fb.var.yoffset;
  874. /* For buffer start address */
  875. mach_info.vidw00add0b0 = VideoPhysicalTemp_f1+start;
  876. mach_info.vidw00add1b0 = mach_info.vidw00add0b0+(fbi->fb.fix.line_length*fbi->fb.var.yres);
  877. __raw_writel(mach_info.vidw00add0b0, S3C_VIDW00ADD0B0);
  878. __raw_writel(mach_info.vidw00add1b0, S3C_VIDW00ADD1B0);
  879. }
  880. void s3c_fb_set_fb_change(int req_fb) {
  881. info[req_fb].fb_change_ready = 0;
  882. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  883. // Software-based trigger
  884. __raw_writel((1<<0), S3C_CPUTRIGCON2);
  885. #elif (defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  886. // Software-based trigger
  887. __raw_writel((3<<0), S3C_TRIGCON);
  888. #endif // #if defined(CONFIG_CPU_S3C2443)
  889. }
  890. /* s3c_fb_activate_var
  891. *
  892. * activate (set) the controller from the given framebuffer
  893. * information
  894. */
  895. void s3c_fb_activate_var(struct s3c_fb_info *fbi,
  896. struct fb_var_screeninfo *var)
  897. {
  898. dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
  899. switch (var->bits_per_pixel) {
  900. case 8:
  901. mach_info.wincon0= S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL; // 4word burst, 8bpp-palletized,
  902. mach_info.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  903. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  904. mach_info.wincon2= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  905. mach_info.wincon3= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  906. mach_info.wincon4= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  907. #endif
  908. mach_info.bpp= PIXEL_BPP8;
  909. mach_info.bytes_per_pixel= 1;
  910. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  911. mach_info.wpalcon= S3C_WPALCON_W0PAL_24BIT;
  912. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  913. mach_info.wpalcon= S3C_WPALCON_W0PAL_16BIT;
  914. #endif
  915. break;
  916. case 16:
  917. mach_info.wincon0= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565; // 4word burst, 16bpp,
  918. mach_info.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  919. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  920. mach_info.wincon2= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  921. mach_info.wincon3= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  922. mach_info.wincon4= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  923. #endif
  924. mach_info.bpp= PIXEL_BPP16;
  925. mach_info.bytes_per_pixel= 2;
  926. break;
  927. case 24:
  928. mach_info.wincon0= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888; // 4word burst, 24bpp,,
  929. mach_info.wincon1= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  930. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  931. mach_info.wincon2= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  932. mach_info.wincon3= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  933. mach_info.wincon4= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  934. #endif
  935. mach_info.bpp= PIXEL_BPP24;
  936. mach_info.bytes_per_pixel= 4;
  937. break;
  938. case 32:
  939. mach_info.bytes_per_pixel= 4;
  940. break;
  941. }
  942. /* write new registers */
  943. __raw_writel(mach_info.wincon0, S3C_WINCON0);
  944. __raw_writel(mach_info.wincon1, S3C_WINCON1);
  945. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  946. __raw_writel(mach_info.wincon2, S3C_WINCON2);
  947. __raw_writel(mach_info.wincon3, S3C_WINCON3);
  948. __raw_writel(mach_info.wincon4, S3C_WINCON4);
  949. #endif
  950. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  951. #if 0
  952. /* set lcd address pointers */
  953. s3c_fb_set_lcdaddr(fbi);
  954. #endif
  955. //__raw_writel(mach_info.wincon0|S3C_WINCONx_ENWIN_F_ENABLE|S3C_WINCONx_BUFAUTOEN_ENABLE, S3C_WINCON0); /* Double buffer auto enable bit */
  956. __raw_writel(mach_info.wincon0|S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
  957. __raw_writel(mach_info.vidcon0|S3C_VIDCON0_ENVID_ENABLE|S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
  958. }
  959. int s3c_fb_init_win (struct s3c_fb_info *fbi, int Bpp, int LeftTop_x, int LeftTop_y, int Width, int Height, int OnOff)
  960. {
  961. s3c_fb_win_onoff(fbi, OFF); // off
  962. s3c_fb_set_bpp(fbi, Bpp);
  963. s3c_fb_set_position_win(fbi, LeftTop_x, LeftTop_y, Width, Height);
  964. s3c_fb_set_size_win(fbi, Width, Height);
  965. s3c_fb_set_memory_size_win(fbi);
  966. s3c_fb_win_onoff(fbi, OnOff); // off
  967. return 0;
  968. }
  969. int s3c_fb_win_onoff(struct s3c_fb_info *fbi, int On)
  970. {
  971. int win_num = fbi->win_id;
  972. if(On)
  973. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_ENWIN_F_ENABLE,
  974. S3C_WINCON0+(0x04*win_num)); // ON
  975. else
  976. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))&~(S3C_WINCONx_ENWIN_F_ENABLE),
  977. S3C_WINCON0+(0x04*win_num)); // OFF
  978. return 0;
  979. }
  980. int s3c_fb_set_alpha_level(struct s3c_fb_info *fbi)
  981. {
  982. unsigned long alpha_val;
  983. int win_num = fbi->win_id;
  984. if(win_num==0){
  985. printk("WIN0 do not support alpha blending.\n");
  986. return -1;
  987. }
  988. alpha_val = S3C_VIDOSDxC_ALPHA1_B(osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_G(osd_alpha_level) |S3C_VIDOSDxC_ALPHA1_R(osd_alpha_level);
  989. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  990. __raw_writel(alpha_val, S3C_VIDOSD1C);
  991. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  992. __raw_writel(alpha_val, S3C_VIDOSD0C+(0x10*win_num));
  993. #endif
  994. return 0;
  995. }
  996. int s3c_fb_set_alpha_mode(struct s3c_fb_info *fbi, int Alpha_mode, int Alpha_level)
  997. {
  998. unsigned long alpha_val;
  999. int win_num = fbi->win_id;
  1000. if(win_num==0){
  1001. printk("WIN0 do not support alpha blending.\n");
  1002. return -1;
  1003. }
  1004. switch(Alpha_mode){
  1005. case 0: // Plane Blending
  1006. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BLD_PIX_PLANE,
  1007. S3C_WINCON0+(0x04*win_num));
  1008. break;
  1009. case 1: // Pixel Blending & chroma(color) key
  1010. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BLD_PIX_PIXEL|S3C_WINCONx_ALPHA_SEL_0,
  1011. S3C_WINCON0+(0x04*win_num));
  1012. break;
  1013. }
  1014. osd_alpha_level = Alpha_level;
  1015. alpha_val = S3C_VIDOSDxC_ALPHA1_B(osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_G(osd_alpha_level) |S3C_VIDOSDxC_ALPHA1_R(osd_alpha_level);
  1016. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1017. __raw_writel(alpha_val, S3C_VIDOSD1C);
  1018. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1019. __raw_writel(alpha_val, S3C_VIDOSD0C+(0x10*win_num));
  1020. #endif
  1021. return 0;
  1022. }
  1023. /*------------------------- Set up color key ------------------------------*/
  1024. int s3c_fb_color_key_alpha_onoff(struct s3c_fb_info *fbi, int On)
  1025. {
  1026. int win_num = fbi->win_id;
  1027. win_num--;
  1028. if(On)
  1029. __raw_writel(__raw_readl(S3C_W1KEYCON0+(0x08*win_num))|S3C_WxKEYCON0_KEYBLEN_ENABLE,
  1030. S3C_W1KEYCON0+(0x08*win_num)); // ON
  1031. else
  1032. __raw_writel(__raw_readl(S3C_W1KEYCON0+(0x08*win_num))&~(S3C_WxKEYCON0_KEYBLEN_ENABLE),
  1033. S3C_W1KEYCON0+(0x08*win_num)); // OFF
  1034. return 0;
  1035. }
  1036. int s3c_fb_color_key_onoff(struct s3c_fb_info *fbi, int On)
  1037. {
  1038. int win_num = fbi->win_id;
  1039. win_num--;
  1040. if(On)
  1041. __raw_writel(__raw_readl(S3C_W1KEYCON0+(0x08*win_num))|S3C_WxKEYCON0_KEYEN_F_ENABLE,
  1042. S3C_W1KEYCON0+(0x08*win_num)); // ON
  1043. else
  1044. __raw_writel(__raw_readl(S3C_W1KEYCON0+(0x08*win_num))&~(S3C_WxKEYCON0_KEYEN_F_ENABLE),
  1045. S3C_W1KEYCON0+(0x08*win_num)); // OFF
  1046. return 0;
  1047. }
  1048. int s3c_fb_setup_color_key_register(struct s3c_fb_info *fbi, s3c_color_key_info_t colkey_info)
  1049. {
  1050. unsigned int compkey = 0;
  1051. int win_num = fbi->win_id;
  1052. if(win_num==0){
  1053. printk("WIN0 do not support color-key.\n");
  1054. return -1;
  1055. }
  1056. win_num--;
  1057. if(fbi->fb.var.bits_per_pixel == PIXEL_BPP16) {
  1058. /* RGB 5-6-5 mode */
  1059. compkey = (((colkey_info.compkey_red & 0x1F) << 19) | 0x70000);
  1060. compkey |= (((colkey_info.compkey_green & 0x3F) << 10) | 0x300);
  1061. compkey |= (((colkey_info.compkey_blue & 0x1F) << 3 )| 0x7);
  1062. }
  1063. else if (fbi->fb.var.bits_per_pixel == PIXEL_BPP24) {
  1064. /* currently RGB 8-8-8 mode */
  1065. compkey = ((colkey_info.compkey_red & 0xFF) << 16);
  1066. compkey |= ((colkey_info.compkey_green & 0xFF) << 8);
  1067. compkey |= ((colkey_info.compkey_blue & 0xFF) << 0);
  1068. }
  1069. else
  1070. printk("Invalid BPP has been given !\n");
  1071. if(colkey_info.direction == COLOR_KEY_DIR_BG_DISPLAY)
  1072. __raw_writel(S3C_WxKEYCON0_COMPKEY(compkey) | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE, S3C_W1KEYCON0+(0x08*win_num));
  1073. else if (colkey_info.direction == COLOR_KEY_DIR_FG_DISPLAY)
  1074. __raw_writel(S3C_WxKEYCON0_COMPKEY(compkey) | S3C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE, S3C_W1KEYCON0+(0x08*win_num));
  1075. else
  1076. printk("Color key direction is not correct :: %d!!!\n", colkey_info.direction);
  1077. return 0;
  1078. }
  1079. int s3c_fb_set_color_value(struct s3c_fb_info *fbi, s3c_color_val_info_t colval_info)
  1080. {
  1081. unsigned int colval = 0;
  1082. int win_num = fbi->win_id;
  1083. if(win_num==0){
  1084. printk("WIN0 do not support color-key value.\n");
  1085. return -1;
  1086. }
  1087. win_num--;
  1088. if(fbi->fb.var.bits_per_pixel == PIXEL_BPP16) {
  1089. /* RGB 5-6-5 mode */
  1090. colval = (((colval_info.colval_red & 0x1F) << 19) | 0x70000);
  1091. colval |= (((colval_info.colval_green & 0x3F) << 10) | 0x300);
  1092. colval |= (((colval_info.colval_blue & 0x1F) << 3 )| 0x7);
  1093. }
  1094. else if (fbi->fb.var.bits_per_pixel == PIXEL_BPP24) {
  1095. /* currently RGB 8-8-8 mode */
  1096. colval = ((colval_info.colval_red & 0xFF) << 16);
  1097. colval |= ((colval_info.colval_green & 0xFF) << 8);
  1098. colval |= ((colval_info.colval_blue & 0xFF) << 0);
  1099. }
  1100. else
  1101. printk("Invalid BPP has been given !\n");
  1102. __raw_writel(S3C_WxKEYCON1_COLVAL(colval), S3C_W1KEYCON1+(0x08*win_num));
  1103. return 0;
  1104. }
  1105. /*--------------------------------------------------------------------------*/
  1106. int s3c_fb_set_position_win(struct s3c_fb_info *fbi, int LeftTop_x, int LeftTop_y, int Width, int Height)
  1107. {
  1108. struct fb_var_screeninfo *var= &fbi->fb.var;
  1109. int win_num = fbi->win_id;
  1110. #if 0
  1111. if(win_num==0){
  1112. printk("WIN0 do not support window position control.\n");
  1113. return -1;
  1114. }
  1115. #endif
  1116. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1117. __raw_writel(S3C_VIDOSDxA_OSD_LTX_F(LeftTop_x) | S3C_VIDOSDxA_OSD_LTY_F(LeftTop_y),
  1118. S3C_VIDOSD0A+(0x0c*win_num));
  1119. __raw_writel(S3C_VIDOSDxB_OSD_RBX_F(Width-1 + LeftTop_x) | S3C_VIDOSDxB_OSD_RBY_F(Height-1 + LeftTop_y),
  1120. S3C_VIDOSD0B+(0x0c*win_num));
  1121. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1122. __raw_writel(S3C_VIDOSDxA_OSD_LTX_F(LeftTop_x) | S3C_VIDOSDxA_OSD_LTY_F(LeftTop_y),
  1123. S3C_VIDOSD0A+(0x10*win_num));
  1124. __raw_writel(S3C_VIDOSDxB_OSD_RBX_F(Width-1 + LeftTop_x) | S3C_VIDOSDxB_OSD_RBY_F(Height-1 + LeftTop_y),
  1125. S3C_VIDOSD0B+(0x10*win_num));
  1126. #endif
  1127. var->xoffset=LeftTop_x;
  1128. var->yoffset=LeftTop_y;
  1129. return 0;
  1130. }
  1131. int s3c_fb_set_size_win(struct s3c_fb_info *fbi, int Width, int Height)
  1132. {
  1133. struct fb_var_screeninfo *var= &fbi->fb.var;
  1134. int win_num = fbi->win_id;
  1135. #if 0
  1136. if(win_num==0){
  1137. printk("WIN0 do not support window size control.\n");
  1138. return -1;
  1139. }
  1140. #endif
  1141. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1142. if(win_num==1)
  1143. __raw_writel(S3C_VIDOSD0C_OSDSIZE(Width*Height),S3C_VIDOSD1D);
  1144. else if(win_num==2)
  1145. __raw_writel(S3C_VIDOSD0C_OSDSIZE(Width*Height),S3C_VIDOSD2D);
  1146. #endif
  1147. var->xres = Width;
  1148. var->yres = Height;
  1149. var->xres_virtual = Width;
  1150. var->yres_virtual= Height;
  1151. return 0;
  1152. }
  1153. int s3c_fb_set_bpp(struct s3c_fb_info *fbi, int Bpp)
  1154. {
  1155. struct fb_var_screeninfo *var= &fbi->fb.var;
  1156. int win_num = fbi->win_id;
  1157. switch(Bpp){
  1158. case 1:
  1159. case 2:
  1160. case 4:
  1161. case 8:
  1162. // What should I do???
  1163. break;
  1164. case 16:
  1165. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BPPMODE_F_16BPP_565,
  1166. S3C_WINCON0+(0x04*win_num));
  1167. var->bits_per_pixel=16;
  1168. break;
  1169. case 24:
  1170. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BPPMODE_F_24BPP_888,
  1171. S3C_WINCON0+(0x04*win_num));
  1172. var->bits_per_pixel=24;
  1173. break;
  1174. case 32:
  1175. var->bits_per_pixel=32;
  1176. break;
  1177. }
  1178. return 0;
  1179. }
  1180. int s3c_fb_set_memory_size_win(struct s3c_fb_info *fbi)
  1181. {
  1182. struct fb_var_screeninfo *var= &fbi->fb.var;
  1183. int win_num = fbi->win_id;
  1184. unsigned long Offset = 0;
  1185. unsigned long PageWidth = 0;
  1186. unsigned long FrameBufferSize = 0;
  1187. PageWidth = var->xres * mach_info.bytes_per_pixel;
  1188. Offset = (var->xres_virtual - var->xres) * mach_info.bytes_per_pixel;
  1189. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  1190. if(win_num==0) Offset=0;
  1191. #endif
  1192. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long)__raw_readl(S3C_VIDW00ADD0B0+(0x08*win_num)) + (PageWidth + Offset) * (var->yres)),
  1193. S3C_VIDW00ADD1B0+(0x08*win_num));
  1194. if(win_num==1)
  1195. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long)__raw_readl(S3C_VIDW00ADD0B1+(0x08*win_num)) + (PageWidth + Offset) * (var->yres)),
  1196. S3C_VIDW00ADD1B1+(0x08*win_num));
  1197. /* size of frame buffer */
  1198. FrameBufferSize = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  1199. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1200. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2B0+(0x08*win_num));
  1201. if(win_num==0)
  1202. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2B1);
  1203. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1204. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2+(0x04*win_num));
  1205. #endif
  1206. return 0;
  1207. }
  1208. int s3c_fb_set_out_path(struct s3c_fb_info *fbi, int Path)
  1209. {
  1210. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1211. switch(Path){
  1212. case 0: // RGB I/F
  1213. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P, S3C_VIDCON0);
  1214. break;
  1215. case 1: // TV Encoder T/F
  1216. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TV, S3C_VIDCON0);
  1217. break;
  1218. case 2: // Indirect I80 I/F-0
  1219. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_I80IF0, S3C_VIDCON0);
  1220. break;
  1221. case 3: // Indirect I80 I/F-1
  1222. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_I80IF1, S3C_VIDCON0);
  1223. break;
  1224. case 4: // TV Encoder & RGB I/F
  1225. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNRGBIF, S3C_VIDCON0);
  1226. break;
  1227. case 6: // TV Encoder & Indirect I80 I/F-0
  1228. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNI80IF0, S3C_VIDCON0);
  1229. break;
  1230. case 7: // TV Encoder & Indirect I80 I/F-1
  1231. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNI80IF1, S3C_VIDCON0);
  1232. break;
  1233. default: // RGB I/F
  1234. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P, S3C_VIDCON0);
  1235. break;
  1236. }
  1237. #endif
  1238. return 0;
  1239. }
  1240. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1241. #define LCD_TV 1
  1242. // LCD display controller configuration functions
  1243. void s3c_fb_set_output_path(int out)
  1244. {
  1245. u32 tmp;
  1246. //printk("s3c_fb_set_output_path() called.\n");
  1247. tmp = __raw_readl(S3C_VIDCON0);
  1248. // if output mode is LCD mode, Scan mode always should be progressive mode
  1249. if(out == LCD_TV) {
  1250. tmp &=~(1<<29);
  1251. }
  1252. tmp &=~(0x7<<26);
  1253. tmp |= (out<<26);
  1254. __raw_writel(tmp, S3C_VIDCON0);
  1255. }
  1256. void s3c_fb_set_clkval(u32 clkval)
  1257. {
  1258. u32 tmp;
  1259. //printk("s3c_fb_set_clkval() called.\n");
  1260. tmp = __raw_readl(S3C_VIDCON0);
  1261. tmp &=~(0x1<<4);
  1262. tmp &=~(0xff<<6);
  1263. __raw_writel(tmp | (clkval<<6) | (1<<4), S3C_VIDCON0);
  1264. }
  1265. void s3c_fb_enable_rgbport(u32 on_off)
  1266. {
  1267. //printk("s3c_fb_enable_rgbport() called.\n");
  1268. if(on_off) //enable
  1269. __raw_writel(0x380, S3C_VIDCON2);
  1270. else //disable
  1271. __raw_writel(0x0, S3C_VIDCON2);
  1272. }
  1273. EXPORT_SYMBOL(s3c_fb_set_output_path);
  1274. EXPORT_SYMBOL(s3c_fb_set_clkval);
  1275. EXPORT_SYMBOL(s3c_fb_enable_rgbport);
  1276. #endif
  1277. void SetLcdPort(void)
  1278. {
  1279. unsigned long gpdat;
  1280. unsigned long gpcon;
  1281. unsigned long hclkcon; //, sclkcon;
  1282. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1283. //Enable clock to LCD
  1284. hclkcon = __raw_readl(S3C2443_HCLKCON);
  1285. hclkcon |= S3C2443_HCLKCON_LCDC;
  1286. __raw_writel(hclkcon, S3C2443_HCLKCON);
  1287. // To select TFT LCD type
  1288. gpdat = __raw_readl(S3C2410_MISCCR);
  1289. gpdat |= (1<<28);
  1290. __raw_writel(gpdat, S3C2410_MISCCR);
  1291. __raw_writel(0xaaaa02aa, S3C2410_GPCCON); // CTRL, VD[7:0]
  1292. __raw_writel(0xaaaaaaaa, S3C2410_GPDCON); // VD[23:8]
  1293. __raw_writel(0x0, S3C2410_GPCUP); // CTRL, VD[7:0]
  1294. __raw_writel(0x0, S3C2410_GPDUP); // CTRL, VD[7:0]
  1295. /* LCD Backlight Enable control */
  1296. gpcon = __raw_readl(S3C2410_GPBCON);
  1297. //gpcon = (gpcon & ~(3<<6)) | (1<<6); // Backlight(GPB3) Enable control : SMDK2443
  1298. gpcon = (gpcon & ~(3<<0)) | (1<<0); // Backlight(GPB0) Enable control : SMDK2450
  1299. __raw_writel(gpcon, S3C2410_GPBCON);
  1300. /* LCD Backlight ON */
  1301. gpdat = __raw_readl(S3C2410_GPBDAT);
  1302. gpdat |= (1<<0);
  1303. __raw_writel(gpdat, S3C2410_GPBDAT);
  1304. /* LCD Backlight dimming control */
  1305. gpcon = __raw_readl(S3C2410_GPBCON);
  1306. gpcon = (gpcon & ~(3<<6)) | (1<<6);
  1307. __raw_writel(gpcon, S3C2410_GPBCON);
  1308. /* LCD Backlight dimming ON */
  1309. gpdat = __raw_readl(S3C2410_GPBDAT);
  1310. gpdat |= (1<<3);
  1311. __raw_writel(gpdat, S3C2410_GPBDAT);
  1312. /* LCD Backlight dimming control pull-down disable*/
  1313. gpcon = __raw_readl(S3C2410_GPBUP);
  1314. gpcon = (gpcon & ~(3<<6));
  1315. __raw_writel(gpcon, S3C2410_GPBUP);
  1316. // LCD _nRESET control
  1317. gpcon = __raw_readl(S3C2410_GPBCON);
  1318. gpcon = (gpcon & ~(3<<2)) |(1<<2);
  1319. __raw_writel(gpcon, S3C2410_GPBCON);
  1320. // LCD module reset
  1321. gpdat = __raw_readl(S3C2410_GPBDAT);
  1322. gpdat &= ~(1<<1); // goes to LOW
  1323. __raw_writel(gpdat, S3C2410_GPBDAT);
  1324. mdelay(10);
  1325. /* LCD Reset high */
  1326. gpdat = __raw_readl(S3C2410_GPBDAT);
  1327. gpdat |= (1<<1); // goes to HIGH
  1328. __raw_writel(gpdat, S3C2410_GPBDAT);
  1329. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1330. //Must be '0' for Normal-path instead of By-pass
  1331. // (*(volatile unsigned *)0x7410800c)=0;
  1332. __raw_writel(0x0, S3C_HOSTIFB_MIFPCON);
  1333. //Enable clock to LCD
  1334. hclkcon = __raw_readl(S3C_HCLK_GATE);
  1335. hclkcon |= S3C_CLKCON_HCLK_LCD;
  1336. __raw_writel(hclkcon, S3C_HCLK_GATE);
  1337. // To select TFT LCD type (RGB I/F)
  1338. gpdat = __raw_readl(S3C_SPCON);
  1339. gpdat &= ~0x3;
  1340. gpdat |= (1<<0);
  1341. __raw_writel(gpdat, S3C_SPCON);
  1342. __raw_writel(0xaaaaaaaa, S3C_GPICON); // VD[15:0]
  1343. __raw_writel(0xaaaaaaaa, S3C_GPJCON); // VD[23:16], Ctrl
  1344. /* jsgood: for smdk6410 unified 0.1 ver. */
  1345. #if 1
  1346. /* Dummy code : remove to LCD pwm control (ryu)*/
  1347. /* LCD Backlight Enable control */
  1348. gpcon = __raw_readl(S3C_GPFCON);
  1349. gpcon = (gpcon & ~(3<<30)) | (1<<30); // Backlight(GPF15) Enable control
  1350. __raw_writel(gpcon, S3C_GPFCON);
  1351. /* LCD Backlight ON */
  1352. gpdat = __raw_readl(S3C_GPFDAT);
  1353. gpdat |= (1<<15);
  1354. __raw_writel(gpdat, S3C_GPFDAT);
  1355. #endif
  1356. // LCD _nRESET control
  1357. gpcon = __raw_readl(S3C_GPNCON);
  1358. gpcon = (gpcon & ~(3<<10)) |(1<<10);
  1359. __raw_writel(gpcon, S3C_GPNCON);
  1360. gpdat = __raw_readl(S3C_GPNDAT);
  1361. gpdat |= (0<<5);
  1362. __raw_writel(gpdat, S3C_GPNDAT);
  1363. mdelay(10);
  1364. gpdat = __raw_readl(S3C_GPNDAT);
  1365. gpdat |= (1<<5);
  1366. __raw_writel(gpdat, S3C_GPNDAT);
  1367. #endif
  1368. }
  1369. void Init_LDI(void)
  1370. {
  1371. printk(KERN_INFO "LCD TYPE :: S3C_LTE480WV LCD will be initialized\n");
  1372. SetLcdPort();
  1373. }