pvr2fb.c 31 KB

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  1. /* drivers/video/pvr2fb.c
  2. *
  3. * Frame buffer and fbcon support for the NEC PowerVR2 found within the Sega
  4. * Dreamcast.
  5. *
  6. * Copyright (c) 2001 M. R. Brown <mrbrown@0xd6.org>
  7. * Copyright (c) 2001, 2002, 2003, 2004, 2005 Paul Mundt <lethal@linux-sh.org>
  8. *
  9. * This file is part of the LinuxDC project (linuxdc.sourceforge.net).
  10. *
  11. */
  12. /*
  13. * This driver is mostly based on the excellent amifb and vfb sources. It uses
  14. * an odd scheme for converting hardware values to/from framebuffer values,
  15. * here are some hacked-up formulas:
  16. *
  17. * The Dreamcast has screen offsets from each side of its four borders and
  18. * the start offsets of the display window. I used these values to calculate
  19. * 'pseudo' values (think of them as placeholders) for the fb video mode, so
  20. * that when it came time to convert these values back into their hardware
  21. * values, I could just add mode- specific offsets to get the correct mode
  22. * settings:
  23. *
  24. * left_margin = diwstart_h - borderstart_h;
  25. * right_margin = borderstop_h - (diwstart_h + xres);
  26. * upper_margin = diwstart_v - borderstart_v;
  27. * lower_margin = borderstop_v - (diwstart_h + yres);
  28. *
  29. * hsync_len = borderstart_h + (hsync_total - borderstop_h);
  30. * vsync_len = borderstart_v + (vsync_total - borderstop_v);
  31. *
  32. * Then, when it's time to convert back to hardware settings, the only
  33. * constants are the borderstart_* offsets, all other values are derived from
  34. * the fb video mode:
  35. *
  36. * // PAL
  37. * borderstart_h = 116;
  38. * borderstart_v = 44;
  39. * ...
  40. * borderstop_h = borderstart_h + hsync_total - hsync_len;
  41. * ...
  42. * diwstart_v = borderstart_v - upper_margin;
  43. *
  44. * However, in the current implementation, the borderstart values haven't had
  45. * the benefit of being fully researched, so some modes may be broken.
  46. */
  47. #undef DEBUG
  48. #include <linux/module.h>
  49. #include <linux/kernel.h>
  50. #include <linux/errno.h>
  51. #include <linux/string.h>
  52. #include <linux/mm.h>
  53. #include <linux/slab.h>
  54. #include <linux/delay.h>
  55. #include <linux/interrupt.h>
  56. #include <linux/fb.h>
  57. #include <linux/init.h>
  58. #include <linux/pci.h>
  59. #ifdef CONFIG_SH_DREAMCAST
  60. #include <asm/machvec.h>
  61. #include <asm/mach/sysasic.h>
  62. #endif
  63. #ifdef CONFIG_SH_DMA
  64. #include <linux/pagemap.h>
  65. #include <asm/mach/dma.h>
  66. #include <asm/dma.h>
  67. #endif
  68. #ifdef CONFIG_SH_STORE_QUEUES
  69. #include <asm/uaccess.h>
  70. #include <asm/cpu/sq.h>
  71. #endif
  72. #ifndef PCI_DEVICE_ID_NEC_NEON250
  73. # define PCI_DEVICE_ID_NEC_NEON250 0x0067
  74. #endif
  75. /* 2D video registers */
  76. #define DISP_BASE par->mmio_base
  77. #define DISP_BRDRCOLR (DISP_BASE + 0x40)
  78. #define DISP_DIWMODE (DISP_BASE + 0x44)
  79. #define DISP_DIWADDRL (DISP_BASE + 0x50)
  80. #define DISP_DIWADDRS (DISP_BASE + 0x54)
  81. #define DISP_DIWSIZE (DISP_BASE + 0x5c)
  82. #define DISP_SYNCCONF (DISP_BASE + 0xd0)
  83. #define DISP_BRDRHORZ (DISP_BASE + 0xd4)
  84. #define DISP_SYNCSIZE (DISP_BASE + 0xd8)
  85. #define DISP_BRDRVERT (DISP_BASE + 0xdc)
  86. #define DISP_DIWCONF (DISP_BASE + 0xe8)
  87. #define DISP_DIWHSTRT (DISP_BASE + 0xec)
  88. #define DISP_DIWVSTRT (DISP_BASE + 0xf0)
  89. /* Pixel clocks, one for TV output, doubled for VGA output */
  90. #define TV_CLK 74239
  91. #define VGA_CLK 37119
  92. /* This is for 60Hz - the VTOTAL is doubled for interlaced modes */
  93. #define PAL_HTOTAL 863
  94. #define PAL_VTOTAL 312
  95. #define NTSC_HTOTAL 857
  96. #define NTSC_VTOTAL 262
  97. /* Supported cable types */
  98. enum { CT_VGA, CT_NONE, CT_RGB, CT_COMPOSITE };
  99. /* Supported video output types */
  100. enum { VO_PAL, VO_NTSC, VO_VGA };
  101. /* Supported palette types */
  102. enum { PAL_ARGB1555, PAL_RGB565, PAL_ARGB4444, PAL_ARGB8888 };
  103. struct pvr2_params { unsigned int val; char *name; };
  104. static struct pvr2_params cables[] __initdata = {
  105. { CT_VGA, "VGA" }, { CT_RGB, "RGB" }, { CT_COMPOSITE, "COMPOSITE" },
  106. };
  107. static struct pvr2_params outputs[] __initdata = {
  108. { VO_PAL, "PAL" }, { VO_NTSC, "NTSC" }, { VO_VGA, "VGA" },
  109. };
  110. /*
  111. * This describes the current video mode
  112. */
  113. static struct pvr2fb_par {
  114. unsigned int hsync_total; /* Clocks/line */
  115. unsigned int vsync_total; /* Lines/field */
  116. unsigned int borderstart_h;
  117. unsigned int borderstop_h;
  118. unsigned int borderstart_v;
  119. unsigned int borderstop_v;
  120. unsigned int diwstart_h; /* Horizontal offset of the display field */
  121. unsigned int diwstart_v; /* Vertical offset of the display field, for
  122. interlaced modes, this is the long field */
  123. unsigned long disp_start; /* Address of image within VRAM */
  124. unsigned char is_interlaced; /* Is the display interlaced? */
  125. unsigned char is_doublescan; /* Are scanlines output twice? (doublescan) */
  126. unsigned char is_lowres; /* Is horizontal pixel-doubling enabled? */
  127. unsigned long mmio_base; /* MMIO base */
  128. } *currentpar;
  129. static struct fb_info *fb_info;
  130. static struct fb_fix_screeninfo pvr2_fix __initdata = {
  131. .id = "NEC PowerVR2",
  132. .type = FB_TYPE_PACKED_PIXELS,
  133. .visual = FB_VISUAL_TRUECOLOR,
  134. .ypanstep = 1,
  135. .ywrapstep = 1,
  136. .accel = FB_ACCEL_NONE,
  137. };
  138. static struct fb_var_screeninfo pvr2_var __initdata = {
  139. .xres = 640,
  140. .yres = 480,
  141. .xres_virtual = 640,
  142. .yres_virtual = 480,
  143. .bits_per_pixel =16,
  144. .red = { 11, 5, 0 },
  145. .green = { 5, 6, 0 },
  146. .blue = { 0, 5, 0 },
  147. .activate = FB_ACTIVATE_NOW,
  148. .height = -1,
  149. .width = -1,
  150. .vmode = FB_VMODE_NONINTERLACED,
  151. };
  152. static int cable_type = CT_VGA;
  153. static int video_output = VO_VGA;
  154. static int nopan = 0;
  155. static int nowrap = 1;
  156. /*
  157. * We do all updating, blanking, etc. during the vertical retrace period
  158. */
  159. static unsigned int do_vmode_full = 0; /* Change the video mode */
  160. static unsigned int do_vmode_pan = 0; /* Update the video mode */
  161. static short do_blank = 0; /* (Un)Blank the screen */
  162. static unsigned int is_blanked = 0; /* Is the screen blanked? */
  163. #ifdef CONFIG_SH_STORE_QUEUES
  164. static unsigned long pvr2fb_map;
  165. #endif
  166. #ifdef CONFIG_SH_DMA
  167. static unsigned int shdma = PVR2_CASCADE_CHAN;
  168. static unsigned int pvr2dma = ONCHIP_NR_DMA_CHANNELS;
  169. #endif
  170. /* Interface used by the world */
  171. int pvr2fb_setup(char*);
  172. static int pvr2fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, unsigned int blue,
  173. unsigned int transp, struct fb_info *info);
  174. static int pvr2fb_blank(int blank, struct fb_info *info);
  175. static unsigned long get_line_length(int xres_virtual, int bpp);
  176. static void set_color_bitfields(struct fb_var_screeninfo *var);
  177. static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
  178. static int pvr2fb_set_par(struct fb_info *info);
  179. static void pvr2_update_display(struct fb_info *info);
  180. static void pvr2_init_display(struct fb_info *info);
  181. static void pvr2_do_blank(void);
  182. static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id);
  183. static int pvr2_init_cable(void);
  184. static int pvr2_get_param(const struct pvr2_params *p, const char *s,
  185. int val, int size);
  186. #ifdef CONFIG_SH_DMA
  187. static ssize_t pvr2fb_write(struct file *file, const char *buf,
  188. size_t count, loff_t *ppos);
  189. #endif
  190. static struct fb_ops pvr2fb_ops = {
  191. .owner = THIS_MODULE,
  192. .fb_setcolreg = pvr2fb_setcolreg,
  193. .fb_blank = pvr2fb_blank,
  194. .fb_check_var = pvr2fb_check_var,
  195. .fb_set_par = pvr2fb_set_par,
  196. #ifdef CONFIG_SH_DMA
  197. .fb_write = pvr2fb_write,
  198. #endif
  199. .fb_fillrect = cfb_fillrect,
  200. .fb_copyarea = cfb_copyarea,
  201. .fb_imageblit = cfb_imageblit,
  202. };
  203. static struct fb_videomode pvr2_modedb[] __initdata = {
  204. /*
  205. * Broadcast video modes (PAL and NTSC). I'm unfamiliar with
  206. * PAL-M and PAL-N, but from what I've read both modes parallel PAL and
  207. * NTSC, so it shouldn't be a problem (I hope).
  208. */
  209. {
  210. /* 640x480 @ 60Hz interlaced (NTSC) */
  211. "ntsc_640x480i", 60, 640, 480, TV_CLK, 38, 33, 0, 18, 146, 26,
  212. FB_SYNC_BROADCAST, FB_VMODE_INTERLACED | FB_VMODE_YWRAP
  213. }, {
  214. /* 640x240 @ 60Hz (NTSC) */
  215. /* XXX: Broken! Don't use... */
  216. "ntsc_640x240", 60, 640, 240, TV_CLK, 38, 33, 0, 0, 146, 22,
  217. FB_SYNC_BROADCAST, FB_VMODE_YWRAP
  218. }, {
  219. /* 640x480 @ 60hz (VGA) */
  220. "vga_640x480", 60, 640, 480, VGA_CLK, 38, 33, 0, 18, 146, 26,
  221. 0, FB_VMODE_YWRAP
  222. },
  223. };
  224. #define NUM_TOTAL_MODES ARRAY_SIZE(pvr2_modedb)
  225. #define DEFMODE_NTSC 0
  226. #define DEFMODE_PAL 0
  227. #define DEFMODE_VGA 2
  228. static int defmode = DEFMODE_NTSC;
  229. static char *mode_option __initdata = NULL;
  230. static inline void pvr2fb_set_pal_type(unsigned int type)
  231. {
  232. struct pvr2fb_par *par = (struct pvr2fb_par *)fb_info->par;
  233. fb_writel(type, par->mmio_base + 0x108);
  234. }
  235. static inline void pvr2fb_set_pal_entry(struct pvr2fb_par *par,
  236. unsigned int regno,
  237. unsigned int val)
  238. {
  239. fb_writel(val, par->mmio_base + 0x1000 + (4 * regno));
  240. }
  241. static int pvr2fb_blank(int blank, struct fb_info *info)
  242. {
  243. do_blank = blank ? blank : -1;
  244. return 0;
  245. }
  246. static inline unsigned long get_line_length(int xres_virtual, int bpp)
  247. {
  248. return (unsigned long)((((xres_virtual*bpp)+31)&~31) >> 3);
  249. }
  250. static void set_color_bitfields(struct fb_var_screeninfo *var)
  251. {
  252. switch (var->bits_per_pixel) {
  253. case 16: /* RGB 565 */
  254. pvr2fb_set_pal_type(PAL_RGB565);
  255. var->red.offset = 11; var->red.length = 5;
  256. var->green.offset = 5; var->green.length = 6;
  257. var->blue.offset = 0; var->blue.length = 5;
  258. var->transp.offset = 0; var->transp.length = 0;
  259. break;
  260. case 24: /* RGB 888 */
  261. var->red.offset = 16; var->red.length = 8;
  262. var->green.offset = 8; var->green.length = 8;
  263. var->blue.offset = 0; var->blue.length = 8;
  264. var->transp.offset = 0; var->transp.length = 0;
  265. break;
  266. case 32: /* ARGB 8888 */
  267. pvr2fb_set_pal_type(PAL_ARGB8888);
  268. var->red.offset = 16; var->red.length = 8;
  269. var->green.offset = 8; var->green.length = 8;
  270. var->blue.offset = 0; var->blue.length = 8;
  271. var->transp.offset = 24; var->transp.length = 8;
  272. break;
  273. }
  274. }
  275. static int pvr2fb_setcolreg(unsigned int regno, unsigned int red,
  276. unsigned int green, unsigned int blue,
  277. unsigned int transp, struct fb_info *info)
  278. {
  279. struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
  280. unsigned int tmp;
  281. if (regno > info->cmap.len)
  282. return 1;
  283. /*
  284. * We only support the hardware palette for 16 and 32bpp. It's also
  285. * expected that the palette format has been set by the time we get
  286. * here, so we don't waste time setting it again.
  287. */
  288. switch (info->var.bits_per_pixel) {
  289. case 16: /* RGB 565 */
  290. tmp = (red & 0xf800) |
  291. ((green & 0xfc00) >> 5) |
  292. ((blue & 0xf800) >> 11);
  293. pvr2fb_set_pal_entry(par, regno, tmp);
  294. ((u16*)(info->pseudo_palette))[regno] = tmp;
  295. break;
  296. case 24: /* RGB 888 */
  297. red >>= 8; green >>= 8; blue >>= 8;
  298. ((u32*)(info->pseudo_palette))[regno] = (red << 16) | (green << 8) | blue;
  299. break;
  300. case 32: /* ARGB 8888 */
  301. red >>= 8; green >>= 8; blue >>= 8;
  302. tmp = (transp << 24) | (red << 16) | (green << 8) | blue;
  303. pvr2fb_set_pal_entry(par, regno, tmp);
  304. ((u32*)(info->pseudo_palette))[regno] = tmp;
  305. break;
  306. default:
  307. pr_debug("Invalid bit depth %d?!?\n", info->var.bits_per_pixel);
  308. return 1;
  309. }
  310. return 0;
  311. }
  312. static int pvr2fb_set_par(struct fb_info *info)
  313. {
  314. struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
  315. struct fb_var_screeninfo *var = &info->var;
  316. unsigned long line_length;
  317. unsigned int vtotal;
  318. /*
  319. * XXX: It's possible that a user could use a VGA box, change the cable
  320. * type in hardware (i.e. switch from VGA<->composite), then change
  321. * modes (i.e. switching to another VT). If that happens we should
  322. * automagically change the output format to cope, but currently I
  323. * don't have a VGA box to make sure this works properly.
  324. */
  325. cable_type = pvr2_init_cable();
  326. if (cable_type == CT_VGA && video_output != VO_VGA)
  327. video_output = VO_VGA;
  328. var->vmode &= FB_VMODE_MASK;
  329. if (var->vmode & FB_VMODE_INTERLACED && video_output != VO_VGA)
  330. par->is_interlaced = 1;
  331. /*
  332. * XXX: Need to be more creative with this (i.e. allow doublecan for
  333. * PAL/NTSC output).
  334. */
  335. if (var->vmode & FB_VMODE_DOUBLE && video_output == VO_VGA)
  336. par->is_doublescan = 1;
  337. par->hsync_total = var->left_margin + var->xres + var->right_margin +
  338. var->hsync_len;
  339. par->vsync_total = var->upper_margin + var->yres + var->lower_margin +
  340. var->vsync_len;
  341. if (var->sync & FB_SYNC_BROADCAST) {
  342. vtotal = par->vsync_total;
  343. if (par->is_interlaced)
  344. vtotal /= 2;
  345. if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
  346. /* XXX: Check for start values here... */
  347. /* XXX: Check hardware for PAL-compatibility */
  348. par->borderstart_h = 116;
  349. par->borderstart_v = 44;
  350. } else {
  351. /* NTSC video output */
  352. par->borderstart_h = 126;
  353. par->borderstart_v = 18;
  354. }
  355. } else {
  356. /* VGA mode */
  357. /* XXX: What else needs to be checked? */
  358. /*
  359. * XXX: We have a little freedom in VGA modes, what ranges
  360. * should be here (i.e. hsync/vsync totals, etc.)?
  361. */
  362. par->borderstart_h = 126;
  363. par->borderstart_v = 40;
  364. }
  365. /* Calculate the remainding offsets */
  366. par->diwstart_h = par->borderstart_h + var->left_margin;
  367. par->diwstart_v = par->borderstart_v + var->upper_margin;
  368. par->borderstop_h = par->diwstart_h + var->xres +
  369. var->right_margin;
  370. par->borderstop_v = par->diwstart_v + var->yres +
  371. var->lower_margin;
  372. if (!par->is_interlaced)
  373. par->borderstop_v /= 2;
  374. if (info->var.xres < 640)
  375. par->is_lowres = 1;
  376. line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
  377. par->disp_start = info->fix.smem_start + (line_length * var->yoffset) * line_length;
  378. info->fix.line_length = line_length;
  379. return 0;
  380. }
  381. static int pvr2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  382. {
  383. struct pvr2fb_par *par = (struct pvr2fb_par *)info->par;
  384. unsigned int vtotal, hsync_total;
  385. unsigned long line_length;
  386. if (var->pixclock != TV_CLK && var->pixclock != VGA_CLK) {
  387. pr_debug("Invalid pixclock value %d\n", var->pixclock);
  388. return -EINVAL;
  389. }
  390. if (var->xres < 320)
  391. var->xres = 320;
  392. if (var->yres < 240)
  393. var->yres = 240;
  394. if (var->xres_virtual < var->xres)
  395. var->xres_virtual = var->xres;
  396. if (var->yres_virtual < var->yres)
  397. var->yres_virtual = var->yres;
  398. if (var->bits_per_pixel <= 16)
  399. var->bits_per_pixel = 16;
  400. else if (var->bits_per_pixel <= 24)
  401. var->bits_per_pixel = 24;
  402. else if (var->bits_per_pixel <= 32)
  403. var->bits_per_pixel = 32;
  404. set_color_bitfields(var);
  405. if (var->vmode & FB_VMODE_YWRAP) {
  406. if (var->xoffset || var->yoffset < 0 ||
  407. var->yoffset >= var->yres_virtual) {
  408. var->xoffset = var->yoffset = 0;
  409. } else {
  410. if (var->xoffset > var->xres_virtual - var->xres ||
  411. var->yoffset > var->yres_virtual - var->yres ||
  412. var->xoffset < 0 || var->yoffset < 0)
  413. var->xoffset = var->yoffset = 0;
  414. }
  415. } else {
  416. var->xoffset = var->yoffset = 0;
  417. }
  418. /*
  419. * XXX: Need to be more creative with this (i.e. allow doublecan for
  420. * PAL/NTSC output).
  421. */
  422. if (var->yres < 480 && video_output == VO_VGA)
  423. var->vmode |= FB_VMODE_DOUBLE;
  424. if (video_output != VO_VGA) {
  425. var->sync |= FB_SYNC_BROADCAST;
  426. var->vmode |= FB_VMODE_INTERLACED;
  427. } else {
  428. var->sync &= ~FB_SYNC_BROADCAST;
  429. var->vmode &= ~FB_VMODE_INTERLACED;
  430. var->vmode |= pvr2_var.vmode;
  431. }
  432. if ((var->activate & FB_ACTIVATE_MASK) != FB_ACTIVATE_TEST) {
  433. var->right_margin = par->borderstop_h -
  434. (par->diwstart_h + var->xres);
  435. var->left_margin = par->diwstart_h - par->borderstart_h;
  436. var->hsync_len = par->borderstart_h +
  437. (par->hsync_total - par->borderstop_h);
  438. var->upper_margin = par->diwstart_v - par->borderstart_v;
  439. var->lower_margin = par->borderstop_v -
  440. (par->diwstart_v + var->yres);
  441. var->vsync_len = par->borderstop_v +
  442. (par->vsync_total - par->borderstop_v);
  443. }
  444. hsync_total = var->left_margin + var->xres + var->right_margin +
  445. var->hsync_len;
  446. vtotal = var->upper_margin + var->yres + var->lower_margin +
  447. var->vsync_len;
  448. if (var->sync & FB_SYNC_BROADCAST) {
  449. if (var->vmode & FB_VMODE_INTERLACED)
  450. vtotal /= 2;
  451. if (vtotal > (PAL_VTOTAL + NTSC_VTOTAL)/2) {
  452. /* PAL video output */
  453. /* XXX: Should be using a range here ... ? */
  454. if (hsync_total != PAL_HTOTAL) {
  455. pr_debug("invalid hsync total for PAL\n");
  456. return -EINVAL;
  457. }
  458. } else {
  459. /* NTSC video output */
  460. if (hsync_total != NTSC_HTOTAL) {
  461. pr_debug("invalid hsync total for NTSC\n");
  462. return -EINVAL;
  463. }
  464. }
  465. }
  466. /* Check memory sizes */
  467. line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
  468. if (line_length * var->yres_virtual > info->fix.smem_len)
  469. return -ENOMEM;
  470. return 0;
  471. }
  472. static void pvr2_update_display(struct fb_info *info)
  473. {
  474. struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
  475. struct fb_var_screeninfo *var = &info->var;
  476. /* Update the start address of the display image */
  477. fb_writel(par->disp_start, DISP_DIWADDRL);
  478. fb_writel(par->disp_start +
  479. get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
  480. DISP_DIWADDRS);
  481. }
  482. /*
  483. * Initialize the video mode. Currently, the 16bpp and 24bpp modes aren't
  484. * very stable. It's probably due to the fact that a lot of the 2D video
  485. * registers are still undocumented.
  486. */
  487. static void pvr2_init_display(struct fb_info *info)
  488. {
  489. struct pvr2fb_par *par = (struct pvr2fb_par *) info->par;
  490. struct fb_var_screeninfo *var = &info->var;
  491. unsigned int diw_height, diw_width, diw_modulo = 1;
  492. unsigned int bytesperpixel = var->bits_per_pixel >> 3;
  493. /* hsync and vsync totals */
  494. fb_writel((par->vsync_total << 16) | par->hsync_total, DISP_SYNCSIZE);
  495. /* column height, modulo, row width */
  496. /* since we're "panning" within vram, we need to offset things based
  497. * on the offset from the virtual x start to our real gfx. */
  498. if (video_output != VO_VGA && par->is_interlaced)
  499. diw_modulo += info->fix.line_length / 4;
  500. diw_height = (par->is_interlaced ? var->yres / 2 : var->yres);
  501. diw_width = get_line_length(var->xres, var->bits_per_pixel) / 4;
  502. fb_writel((diw_modulo << 20) | (--diw_height << 10) | --diw_width,
  503. DISP_DIWSIZE);
  504. /* display address, long and short fields */
  505. fb_writel(par->disp_start, DISP_DIWADDRL);
  506. fb_writel(par->disp_start +
  507. get_line_length(var->xoffset+var->xres, var->bits_per_pixel),
  508. DISP_DIWADDRS);
  509. /* border horizontal, border vertical, border color */
  510. fb_writel((par->borderstart_h << 16) | par->borderstop_h, DISP_BRDRHORZ);
  511. fb_writel((par->borderstart_v << 16) | par->borderstop_v, DISP_BRDRVERT);
  512. fb_writel(0, DISP_BRDRCOLR);
  513. /* display window start position */
  514. fb_writel(par->diwstart_h, DISP_DIWHSTRT);
  515. fb_writel((par->diwstart_v << 16) | par->diwstart_v, DISP_DIWVSTRT);
  516. /* misc. settings */
  517. fb_writel((0x16 << 16) | par->is_lowres, DISP_DIWCONF);
  518. /* clock doubler (for VGA), scan doubler, display enable */
  519. fb_writel(((video_output == VO_VGA) << 23) |
  520. (par->is_doublescan << 1) | 1, DISP_DIWMODE);
  521. /* bits per pixel */
  522. fb_writel(fb_readl(DISP_DIWMODE) | (--bytesperpixel << 2), DISP_DIWMODE);
  523. /* video enable, color sync, interlace,
  524. * hsync and vsync polarity (currently unused) */
  525. fb_writel(0x100 | ((par->is_interlaced /*|4*/) << 4), DISP_SYNCCONF);
  526. }
  527. /* Simulate blanking by making the border cover the entire screen */
  528. #define BLANK_BIT (1<<3)
  529. static void pvr2_do_blank(void)
  530. {
  531. struct pvr2fb_par *par = currentpar;
  532. unsigned long diwconf;
  533. diwconf = fb_readl(DISP_DIWCONF);
  534. if (do_blank > 0)
  535. fb_writel(diwconf | BLANK_BIT, DISP_DIWCONF);
  536. else
  537. fb_writel(diwconf & ~BLANK_BIT, DISP_DIWCONF);
  538. is_blanked = do_blank > 0 ? do_blank : 0;
  539. }
  540. static irqreturn_t pvr2fb_interrupt(int irq, void *dev_id)
  541. {
  542. struct fb_info *info = dev_id;
  543. if (do_vmode_pan || do_vmode_full)
  544. pvr2_update_display(info);
  545. if (do_vmode_full)
  546. pvr2_init_display(info);
  547. if (do_vmode_pan)
  548. do_vmode_pan = 0;
  549. if (do_vmode_full)
  550. do_vmode_full = 0;
  551. if (do_blank) {
  552. pvr2_do_blank();
  553. do_blank = 0;
  554. }
  555. return IRQ_HANDLED;
  556. }
  557. /*
  558. * Determine the cable type and initialize the cable output format. Don't do
  559. * anything if the cable type has been overidden (via "cable:XX").
  560. */
  561. #define PCTRA 0xff80002c
  562. #define PDTRA 0xff800030
  563. #define VOUTC 0xa0702c00
  564. static int pvr2_init_cable(void)
  565. {
  566. if (cable_type < 0) {
  567. fb_writel((fb_readl(PCTRA) & 0xfff0ffff) | 0x000a0000,
  568. PCTRA);
  569. cable_type = (fb_readw(PDTRA) >> 8) & 3;
  570. }
  571. /* Now select the output format (either composite or other) */
  572. /* XXX: Save the previous val first, as this reg is also AICA
  573. related */
  574. if (cable_type == CT_COMPOSITE)
  575. fb_writel(3 << 8, VOUTC);
  576. else
  577. fb_writel(0, VOUTC);
  578. return cable_type;
  579. }
  580. #ifdef CONFIG_SH_DMA
  581. static ssize_t pvr2fb_write(struct file *file, const char *buf,
  582. size_t count, loff_t *ppos)
  583. {
  584. unsigned long dst, start, end, len;
  585. unsigned int nr_pages;
  586. struct page **pages;
  587. int ret, i;
  588. nr_pages = (count + PAGE_SIZE - 1) >> PAGE_SHIFT;
  589. pages = kmalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
  590. if (!pages)
  591. return -ENOMEM;
  592. down_read(&current->mm->mmap_sem);
  593. ret = get_user_pages(current, current->mm, (unsigned long)buf,
  594. nr_pages, WRITE, 0, pages, NULL);
  595. up_read(&current->mm->mmap_sem);
  596. if (ret < nr_pages) {
  597. nr_pages = ret;
  598. ret = -EINVAL;
  599. goto out_unmap;
  600. }
  601. dma_configure_channel(shdma, 0x12c1);
  602. dst = (unsigned long)fb_info->screen_base + *ppos;
  603. start = (unsigned long)page_address(pages[0]);
  604. end = (unsigned long)page_address(pages[nr_pages]);
  605. len = nr_pages << PAGE_SHIFT;
  606. /* Half-assed contig check */
  607. if (start + len == end) {
  608. /* As we do this in one shot, it's either all or nothing.. */
  609. if ((*ppos + len) > fb_info->fix.smem_len) {
  610. ret = -ENOSPC;
  611. goto out_unmap;
  612. }
  613. dma_write(shdma, start, 0, len);
  614. dma_write(pvr2dma, 0, dst, len);
  615. dma_wait_for_completion(pvr2dma);
  616. goto out;
  617. }
  618. /* Not contiguous, writeout per-page instead.. */
  619. for (i = 0; i < nr_pages; i++, dst += PAGE_SIZE) {
  620. if ((*ppos + (i << PAGE_SHIFT)) > fb_info->fix.smem_len) {
  621. ret = -ENOSPC;
  622. goto out_unmap;
  623. }
  624. dma_write_page(shdma, (unsigned long)page_address(pages[i]), 0);
  625. dma_write_page(pvr2dma, 0, dst);
  626. dma_wait_for_completion(pvr2dma);
  627. }
  628. out:
  629. *ppos += count;
  630. ret = count;
  631. out_unmap:
  632. for (i = 0; i < nr_pages; i++)
  633. page_cache_release(pages[i]);
  634. kfree(pages);
  635. return ret;
  636. }
  637. #endif /* CONFIG_SH_DMA */
  638. /**
  639. * pvr2fb_common_init
  640. *
  641. * Common init code for the PVR2 chips.
  642. *
  643. * This mostly takes care of the common aspects of the fb setup and
  644. * registration. It's expected that the board-specific init code has
  645. * already setup pvr2_fix with something meaningful at this point.
  646. *
  647. * Device info reporting is also done here, as well as picking a sane
  648. * default from the modedb. For board-specific modelines, simply define
  649. * a per-board modedb.
  650. *
  651. * Also worth noting is that the cable and video output types are likely
  652. * always going to be VGA for the PCI-based PVR2 boards, but we leave this
  653. * in for flexibility anyways. Who knows, maybe someone has tv-out on a
  654. * PCI-based version of these things ;-)
  655. */
  656. static int __init pvr2fb_common_init(void)
  657. {
  658. struct pvr2fb_par *par = currentpar;
  659. unsigned long modememused, rev;
  660. fb_info->screen_base = ioremap_nocache(pvr2_fix.smem_start,
  661. pvr2_fix.smem_len);
  662. if (!fb_info->screen_base) {
  663. printk(KERN_ERR "pvr2fb: Failed to remap smem space\n");
  664. goto out_err;
  665. }
  666. par->mmio_base = (unsigned long)ioremap_nocache(pvr2_fix.mmio_start,
  667. pvr2_fix.mmio_len);
  668. if (!par->mmio_base) {
  669. printk(KERN_ERR "pvr2fb: Failed to remap mmio space\n");
  670. goto out_err;
  671. }
  672. fb_memset(fb_info->screen_base, 0, pvr2_fix.smem_len);
  673. pvr2_fix.ypanstep = nopan ? 0 : 1;
  674. pvr2_fix.ywrapstep = nowrap ? 0 : 1;
  675. fb_info->fbops = &pvr2fb_ops;
  676. fb_info->fix = pvr2_fix;
  677. fb_info->par = currentpar;
  678. fb_info->pseudo_palette = (void *)(fb_info->par + 1);
  679. fb_info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  680. if (video_output == VO_VGA)
  681. defmode = DEFMODE_VGA;
  682. if (!mode_option)
  683. mode_option = "640x480@60";
  684. if (!fb_find_mode(&fb_info->var, fb_info, mode_option, pvr2_modedb,
  685. NUM_TOTAL_MODES, &pvr2_modedb[defmode], 16))
  686. fb_info->var = pvr2_var;
  687. fb_alloc_cmap(&fb_info->cmap, 256, 0);
  688. if (register_framebuffer(fb_info) < 0)
  689. goto out_err;
  690. modememused = get_line_length(fb_info->var.xres_virtual,
  691. fb_info->var.bits_per_pixel);
  692. modememused *= fb_info->var.yres_virtual;
  693. rev = fb_readl(par->mmio_base + 0x04);
  694. printk("fb%d: %s (rev %ld.%ld) frame buffer device, using %ldk/%ldk of video memory\n",
  695. fb_info->node, fb_info->fix.id, (rev >> 4) & 0x0f, rev & 0x0f,
  696. modememused >> 10, (unsigned long)(fb_info->fix.smem_len >> 10));
  697. printk("fb%d: Mode %dx%d-%d pitch = %ld cable: %s video output: %s\n",
  698. fb_info->node, fb_info->var.xres, fb_info->var.yres,
  699. fb_info->var.bits_per_pixel,
  700. get_line_length(fb_info->var.xres, fb_info->var.bits_per_pixel),
  701. (char *)pvr2_get_param(cables, NULL, cable_type, 3),
  702. (char *)pvr2_get_param(outputs, NULL, video_output, 3));
  703. #ifdef CONFIG_SH_STORE_QUEUES
  704. printk(KERN_NOTICE "fb%d: registering with SQ API\n", fb_info->node);
  705. pvr2fb_map = sq_remap(fb_info->fix.smem_start, fb_info->fix.smem_len,
  706. fb_info->fix.id, pgprot_val(PAGE_SHARED));
  707. printk(KERN_NOTICE "fb%d: Mapped video memory to SQ addr 0x%lx\n",
  708. fb_info->node, pvr2fb_map);
  709. #endif
  710. return 0;
  711. out_err:
  712. if (fb_info->screen_base)
  713. iounmap(fb_info->screen_base);
  714. if (par->mmio_base)
  715. iounmap((void *)par->mmio_base);
  716. return -ENXIO;
  717. }
  718. #ifdef CONFIG_SH_DREAMCAST
  719. static int __init pvr2fb_dc_init(void)
  720. {
  721. if (!mach_is_dreamcast())
  722. return -ENXIO;
  723. /* Make a guess at the monitor based on the attached cable */
  724. if (pvr2_init_cable() == CT_VGA) {
  725. fb_info->monspecs.hfmin = 30000;
  726. fb_info->monspecs.hfmax = 70000;
  727. fb_info->monspecs.vfmin = 60;
  728. fb_info->monspecs.vfmax = 60;
  729. } else {
  730. /* Not VGA, using a TV (taken from acornfb) */
  731. fb_info->monspecs.hfmin = 15469;
  732. fb_info->monspecs.hfmax = 15781;
  733. fb_info->monspecs.vfmin = 49;
  734. fb_info->monspecs.vfmax = 51;
  735. }
  736. /*
  737. * XXX: This needs to pull default video output via BIOS or other means
  738. */
  739. if (video_output < 0) {
  740. if (cable_type == CT_VGA) {
  741. video_output = VO_VGA;
  742. } else {
  743. video_output = VO_NTSC;
  744. }
  745. }
  746. /*
  747. * Nothing exciting about the DC PVR2 .. only a measly 8MiB.
  748. */
  749. pvr2_fix.smem_start = 0xa5000000; /* RAM starts here */
  750. pvr2_fix.smem_len = 8 << 20;
  751. pvr2_fix.mmio_start = 0xa05f8000; /* registers start here */
  752. pvr2_fix.mmio_len = 0x2000;
  753. if (request_irq(HW_EVENT_VSYNC, pvr2fb_interrupt, 0,
  754. "pvr2 VBL handler", fb_info)) {
  755. return -EBUSY;
  756. }
  757. #ifdef CONFIG_SH_DMA
  758. if (request_dma(pvr2dma, "pvr2") != 0) {
  759. free_irq(HW_EVENT_VSYNC, 0);
  760. return -EBUSY;
  761. }
  762. #endif
  763. return pvr2fb_common_init();
  764. }
  765. static void pvr2fb_dc_exit(void)
  766. {
  767. if (fb_info->screen_base) {
  768. iounmap(fb_info->screen_base);
  769. fb_info->screen_base = NULL;
  770. }
  771. if (currentpar->mmio_base) {
  772. iounmap((void *)currentpar->mmio_base);
  773. currentpar->mmio_base = 0;
  774. }
  775. free_irq(HW_EVENT_VSYNC, 0);
  776. #ifdef CONFIG_SH_DMA
  777. free_dma(pvr2dma);
  778. #endif
  779. }
  780. #endif /* CONFIG_SH_DREAMCAST */
  781. #ifdef CONFIG_PCI
  782. static int __devinit pvr2fb_pci_probe(struct pci_dev *pdev,
  783. const struct pci_device_id *ent)
  784. {
  785. int ret;
  786. ret = pci_enable_device(pdev);
  787. if (ret) {
  788. printk(KERN_ERR "pvr2fb: PCI enable failed\n");
  789. return ret;
  790. }
  791. ret = pci_request_regions(pdev, "pvr2fb");
  792. if (ret) {
  793. printk(KERN_ERR "pvr2fb: PCI request regions failed\n");
  794. return ret;
  795. }
  796. /*
  797. * Slightly more exciting than the DC PVR2 .. 16MiB!
  798. */
  799. pvr2_fix.smem_start = pci_resource_start(pdev, 0);
  800. pvr2_fix.smem_len = pci_resource_len(pdev, 0);
  801. pvr2_fix.mmio_start = pci_resource_start(pdev, 1);
  802. pvr2_fix.mmio_len = pci_resource_len(pdev, 1);
  803. fb_info->device = &pdev->dev;
  804. return pvr2fb_common_init();
  805. }
  806. static void __devexit pvr2fb_pci_remove(struct pci_dev *pdev)
  807. {
  808. if (fb_info->screen_base) {
  809. iounmap(fb_info->screen_base);
  810. fb_info->screen_base = NULL;
  811. }
  812. if (currentpar->mmio_base) {
  813. iounmap((void *)currentpar->mmio_base);
  814. currentpar->mmio_base = 0;
  815. }
  816. pci_release_regions(pdev);
  817. }
  818. static struct pci_device_id pvr2fb_pci_tbl[] __devinitdata = {
  819. { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NEON250,
  820. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  821. { 0, },
  822. };
  823. MODULE_DEVICE_TABLE(pci, pvr2fb_pci_tbl);
  824. static struct pci_driver pvr2fb_pci_driver = {
  825. .name = "pvr2fb",
  826. .id_table = pvr2fb_pci_tbl,
  827. .probe = pvr2fb_pci_probe,
  828. .remove = __devexit_p(pvr2fb_pci_remove),
  829. };
  830. static int __init pvr2fb_pci_init(void)
  831. {
  832. return pci_register_driver(&pvr2fb_pci_driver);
  833. }
  834. static void pvr2fb_pci_exit(void)
  835. {
  836. pci_unregister_driver(&pvr2fb_pci_driver);
  837. }
  838. #endif /* CONFIG_PCI */
  839. static int __init pvr2_get_param(const struct pvr2_params *p, const char *s,
  840. int val, int size)
  841. {
  842. int i;
  843. for (i = 0 ; i < size ; i++ ) {
  844. if (s != NULL) {
  845. if (!strnicmp(p[i].name, s, strlen(s)))
  846. return p[i].val;
  847. } else {
  848. if (p[i].val == val)
  849. return (int)p[i].name;
  850. }
  851. }
  852. return -1;
  853. }
  854. /*
  855. * Parse command arguments. Supported arguments are:
  856. * inverse Use inverse color maps
  857. * cable:composite|rgb|vga Override the video cable type
  858. * output:NTSC|PAL|VGA Override the video output format
  859. *
  860. * <xres>x<yres>[-<bpp>][@<refresh>] or,
  861. * <name>[-<bpp>][@<refresh>] Startup using this video mode
  862. */
  863. #ifndef MODULE
  864. int __init pvr2fb_setup(char *options)
  865. {
  866. char *this_opt;
  867. char cable_arg[80];
  868. char output_arg[80];
  869. if (!options || !*options)
  870. return 0;
  871. while ((this_opt = strsep(&options, ","))) {
  872. if (!*this_opt)
  873. continue;
  874. if (!strcmp(this_opt, "inverse")) {
  875. fb_invert_cmaps();
  876. } else if (!strncmp(this_opt, "cable:", 6)) {
  877. strcpy(cable_arg, this_opt + 6);
  878. } else if (!strncmp(this_opt, "output:", 7)) {
  879. strcpy(output_arg, this_opt + 7);
  880. } else if (!strncmp(this_opt, "nopan", 5)) {
  881. nopan = 1;
  882. } else if (!strncmp(this_opt, "nowrap", 6)) {
  883. nowrap = 1;
  884. } else {
  885. mode_option = this_opt;
  886. }
  887. }
  888. if (*cable_arg)
  889. cable_type = pvr2_get_param(cables, cable_arg, 0, 3);
  890. if (*output_arg)
  891. video_output = pvr2_get_param(outputs, output_arg, 0, 3);
  892. return 0;
  893. }
  894. #endif
  895. static struct pvr2_board {
  896. int (*init)(void);
  897. void (*exit)(void);
  898. char name[16];
  899. } board_list[] = {
  900. #ifdef CONFIG_SH_DREAMCAST
  901. { pvr2fb_dc_init, pvr2fb_dc_exit, "Sega DC PVR2" },
  902. #endif
  903. #ifdef CONFIG_PCI
  904. { pvr2fb_pci_init, pvr2fb_pci_exit, "PCI PVR2" },
  905. #endif
  906. { 0, },
  907. };
  908. int __init pvr2fb_init(void)
  909. {
  910. int i, ret = -ENODEV;
  911. int size;
  912. #ifndef MODULE
  913. char *option = NULL;
  914. if (fb_get_options("pvr2fb", &option))
  915. return -ENODEV;
  916. pvr2fb_setup(option);
  917. #endif
  918. size = sizeof(struct fb_info) + sizeof(struct pvr2fb_par) + 16 * sizeof(u32);
  919. fb_info = kmalloc(size, GFP_KERNEL);
  920. if (!fb_info) {
  921. printk(KERN_ERR "Failed to allocate memory for fb_info\n");
  922. return -ENOMEM;
  923. }
  924. memset(fb_info, 0, size);
  925. currentpar = (struct pvr2fb_par *)(fb_info + 1);
  926. for (i = 0; i < ARRAY_SIZE(board_list); i++) {
  927. struct pvr2_board *pvr_board = board_list + i;
  928. if (!pvr_board->init)
  929. continue;
  930. ret = pvr_board->init();
  931. if (ret != 0) {
  932. printk(KERN_ERR "pvr2fb: Failed init of %s device\n",
  933. pvr_board->name);
  934. kfree(fb_info);
  935. break;
  936. }
  937. }
  938. return ret;
  939. }
  940. static void __exit pvr2fb_exit(void)
  941. {
  942. int i;
  943. for (i = 0; i < ARRAY_SIZE(board_list); i++) {
  944. struct pvr2_board *pvr_board = board_list + i;
  945. if (pvr_board->exit)
  946. pvr_board->exit();
  947. }
  948. #ifdef CONFIG_SH_STORE_QUEUES
  949. sq_unmap(pvr2fb_map);
  950. #endif
  951. unregister_framebuffer(fb_info);
  952. kfree(fb_info);
  953. }
  954. module_init(pvr2fb_init);
  955. module_exit(pvr2fb_exit);
  956. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, M. R. Brown <mrbrown@0xd6.org>");
  957. MODULE_DESCRIPTION("Framebuffer driver for NEC PowerVR 2 based graphics boards");
  958. MODULE_LICENSE("GPL");