neofb.c 58 KB

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  1. /*
  2. * linux/drivers/video/neofb.c -- NeoMagic Framebuffer Driver
  3. *
  4. * Copyright (c) 2001-2002 Denis Oliver Kropp <dok@directfb.org>
  5. *
  6. *
  7. * Card specific code is based on XFree86's neomagic driver.
  8. * Framebuffer framework code is based on code of cyber2000fb.
  9. *
  10. * This file is subject to the terms and conditions of the GNU General
  11. * Public License. See the file COPYING in the main directory of this
  12. * archive for more details.
  13. *
  14. *
  15. * 0.4.1
  16. * - Cosmetic changes (dok)
  17. *
  18. * 0.4
  19. * - Toshiba Libretto support, allow modes larger than LCD size if
  20. * LCD is disabled, keep BIOS settings if internal/external display
  21. * haven't been enabled explicitly
  22. * (Thomas J. Moore <dark@mama.indstate.edu>)
  23. *
  24. * 0.3.3
  25. * - Porting over to new fbdev api. (jsimmons)
  26. *
  27. * 0.3.2
  28. * - got rid of all floating point (dok)
  29. *
  30. * 0.3.1
  31. * - added module license (dok)
  32. *
  33. * 0.3
  34. * - hardware accelerated clear and move for 2200 and above (dok)
  35. * - maximum allowed dotclock is handled now (dok)
  36. *
  37. * 0.2.1
  38. * - correct panning after X usage (dok)
  39. * - added module and kernel parameters (dok)
  40. * - no stretching if external display is enabled (dok)
  41. *
  42. * 0.2
  43. * - initial version (dok)
  44. *
  45. *
  46. * TODO
  47. * - ioctl for internal/external switching
  48. * - blanking
  49. * - 32bit depth support, maybe impossible
  50. * - disable pan-on-sync, need specs
  51. *
  52. * BUGS
  53. * - white margin on bootup like with tdfxfb (colormap problem?)
  54. *
  55. */
  56. #include <linux/module.h>
  57. #include <linux/kernel.h>
  58. #include <linux/errno.h>
  59. #include <linux/string.h>
  60. #include <linux/mm.h>
  61. #include <linux/slab.h>
  62. #include <linux/delay.h>
  63. #include <linux/fb.h>
  64. #include <linux/pci.h>
  65. #include <linux/init.h>
  66. #ifdef CONFIG_TOSHIBA
  67. #include <linux/toshiba.h>
  68. #endif
  69. #include <asm/io.h>
  70. #include <asm/irq.h>
  71. #include <asm/pgtable.h>
  72. #include <asm/system.h>
  73. #include <asm/uaccess.h>
  74. #ifdef CONFIG_MTRR
  75. #include <asm/mtrr.h>
  76. #endif
  77. #include <video/vga.h>
  78. #include <video/neomagic.h>
  79. #define NEOFB_VERSION "0.4.2"
  80. /* --------------------------------------------------------------------- */
  81. static int internal;
  82. static int external;
  83. static int libretto;
  84. static int nostretch;
  85. static int nopciburst;
  86. static char *mode_option __devinitdata = NULL;
  87. #ifdef MODULE
  88. MODULE_AUTHOR("(c) 2001-2002 Denis Oliver Kropp <dok@convergence.de>");
  89. MODULE_LICENSE("GPL");
  90. MODULE_DESCRIPTION("FBDev driver for NeoMagic PCI Chips");
  91. module_param(internal, bool, 0);
  92. MODULE_PARM_DESC(internal, "Enable output on internal LCD Display.");
  93. module_param(external, bool, 0);
  94. MODULE_PARM_DESC(external, "Enable output on external CRT.");
  95. module_param(libretto, bool, 0);
  96. MODULE_PARM_DESC(libretto, "Force Libretto 100/110 800x480 LCD.");
  97. module_param(nostretch, bool, 0);
  98. MODULE_PARM_DESC(nostretch,
  99. "Disable stretching of modes smaller than LCD.");
  100. module_param(nopciburst, bool, 0);
  101. MODULE_PARM_DESC(nopciburst, "Disable PCI burst mode.");
  102. module_param(mode_option, charp, 0);
  103. MODULE_PARM_DESC(mode_option, "Preferred video mode ('640x480-8@60', etc)");
  104. #endif
  105. /* --------------------------------------------------------------------- */
  106. static biosMode bios8[] = {
  107. {320, 240, 0x40},
  108. {300, 400, 0x42},
  109. {640, 400, 0x20},
  110. {640, 480, 0x21},
  111. {800, 600, 0x23},
  112. {1024, 768, 0x25},
  113. };
  114. static biosMode bios16[] = {
  115. {320, 200, 0x2e},
  116. {320, 240, 0x41},
  117. {300, 400, 0x43},
  118. {640, 480, 0x31},
  119. {800, 600, 0x34},
  120. {1024, 768, 0x37},
  121. };
  122. static biosMode bios24[] = {
  123. {640, 480, 0x32},
  124. {800, 600, 0x35},
  125. {1024, 768, 0x38}
  126. };
  127. #ifdef NO_32BIT_SUPPORT_YET
  128. /* FIXME: guessed values, wrong */
  129. static biosMode bios32[] = {
  130. {640, 480, 0x33},
  131. {800, 600, 0x36},
  132. {1024, 768, 0x39}
  133. };
  134. #endif
  135. static inline void write_le32(int regindex, u32 val, const struct neofb_par *par)
  136. {
  137. writel(val, par->neo2200 + par->cursorOff + regindex);
  138. }
  139. static int neoFindMode(int xres, int yres, int depth)
  140. {
  141. int xres_s;
  142. int i, size;
  143. biosMode *mode;
  144. switch (depth) {
  145. case 8:
  146. size = ARRAY_SIZE(bios8);
  147. mode = bios8;
  148. break;
  149. case 16:
  150. size = ARRAY_SIZE(bios16);
  151. mode = bios16;
  152. break;
  153. case 24:
  154. size = ARRAY_SIZE(bios24);
  155. mode = bios24;
  156. break;
  157. #ifdef NO_32BIT_SUPPORT_YET
  158. case 32:
  159. size = ARRAY_SIZE(bios32);
  160. mode = bios32;
  161. break;
  162. #endif
  163. default:
  164. return 0;
  165. }
  166. for (i = 0; i < size; i++) {
  167. if (xres <= mode[i].x_res) {
  168. xres_s = mode[i].x_res;
  169. for (; i < size; i++) {
  170. if (mode[i].x_res != xres_s)
  171. return mode[i - 1].mode;
  172. if (yres <= mode[i].y_res)
  173. return mode[i].mode;
  174. }
  175. }
  176. }
  177. return mode[size - 1].mode;
  178. }
  179. /*
  180. * neoCalcVCLK --
  181. *
  182. * Determine the closest clock frequency to the one requested.
  183. */
  184. #define REF_FREQ 0xe517 /* 14.31818 in 20.12 fixed point */
  185. #define MAX_N 127
  186. #define MAX_D 31
  187. #define MAX_F 1
  188. static void neoCalcVCLK(const struct fb_info *info,
  189. struct neofb_par *par, long freq)
  190. {
  191. int n, d, f;
  192. int n_best = 0, d_best = 0, f_best = 0;
  193. long f_best_diff = (0x7ffff << 12); /* 20.12 */
  194. long f_target = (freq << 12) / 1000; /* 20.12 */
  195. for (f = 0; f <= MAX_F; f++)
  196. for (n = 0; n <= MAX_N; n++)
  197. for (d = 0; d <= MAX_D; d++) {
  198. long f_out; /* 20.12 */
  199. long f_diff; /* 20.12 */
  200. f_out =
  201. ((((n + 1) << 12) / ((d +
  202. 1) *
  203. (1 << f))) >> 12)
  204. * REF_FREQ;
  205. f_diff = abs(f_out - f_target);
  206. if (f_diff < f_best_diff) {
  207. f_best_diff = f_diff;
  208. n_best = n;
  209. d_best = d;
  210. f_best = f;
  211. }
  212. }
  213. if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
  214. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
  215. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
  216. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
  217. /* NOT_DONE: We are trying the full range of the 2200 clock.
  218. We should be able to try n up to 2047 */
  219. par->VCLK3NumeratorLow = n_best;
  220. par->VCLK3NumeratorHigh = (f_best << 7);
  221. } else
  222. par->VCLK3NumeratorLow = n_best | (f_best << 7);
  223. par->VCLK3Denominator = d_best;
  224. #ifdef NEOFB_DEBUG
  225. printk("neoVCLK: f:%d NumLow=%d NumHi=%d Den=%d Df=%d\n",
  226. f_target >> 12,
  227. par->VCLK3NumeratorLow,
  228. par->VCLK3NumeratorHigh,
  229. par->VCLK3Denominator, f_best_diff >> 12);
  230. #endif
  231. }
  232. /*
  233. * vgaHWInit --
  234. * Handle the initialization, etc. of a screen.
  235. * Return FALSE on failure.
  236. */
  237. static int vgaHWInit(const struct fb_var_screeninfo *var,
  238. const struct fb_info *info,
  239. struct neofb_par *par, struct xtimings *timings)
  240. {
  241. par->MiscOutReg = 0x23;
  242. if (!(timings->sync & FB_SYNC_HOR_HIGH_ACT))
  243. par->MiscOutReg |= 0x40;
  244. if (!(timings->sync & FB_SYNC_VERT_HIGH_ACT))
  245. par->MiscOutReg |= 0x80;
  246. /*
  247. * Time Sequencer
  248. */
  249. par->Sequencer[0] = 0x00;
  250. par->Sequencer[1] = 0x01;
  251. par->Sequencer[2] = 0x0F;
  252. par->Sequencer[3] = 0x00; /* Font select */
  253. par->Sequencer[4] = 0x0E; /* Misc */
  254. /*
  255. * CRTC Controller
  256. */
  257. par->CRTC[0] = (timings->HTotal >> 3) - 5;
  258. par->CRTC[1] = (timings->HDisplay >> 3) - 1;
  259. par->CRTC[2] = (timings->HDisplay >> 3) - 1;
  260. par->CRTC[3] = (((timings->HTotal >> 3) - 1) & 0x1F) | 0x80;
  261. par->CRTC[4] = (timings->HSyncStart >> 3);
  262. par->CRTC[5] = ((((timings->HTotal >> 3) - 1) & 0x20) << 2)
  263. | (((timings->HSyncEnd >> 3)) & 0x1F);
  264. par->CRTC[6] = (timings->VTotal - 2) & 0xFF;
  265. par->CRTC[7] = (((timings->VTotal - 2) & 0x100) >> 8)
  266. | (((timings->VDisplay - 1) & 0x100) >> 7)
  267. | ((timings->VSyncStart & 0x100) >> 6)
  268. | (((timings->VDisplay - 1) & 0x100) >> 5)
  269. | 0x10 | (((timings->VTotal - 2) & 0x200) >> 4)
  270. | (((timings->VDisplay - 1) & 0x200) >> 3)
  271. | ((timings->VSyncStart & 0x200) >> 2);
  272. par->CRTC[8] = 0x00;
  273. par->CRTC[9] = (((timings->VDisplay - 1) & 0x200) >> 4) | 0x40;
  274. if (timings->dblscan)
  275. par->CRTC[9] |= 0x80;
  276. par->CRTC[10] = 0x00;
  277. par->CRTC[11] = 0x00;
  278. par->CRTC[12] = 0x00;
  279. par->CRTC[13] = 0x00;
  280. par->CRTC[14] = 0x00;
  281. par->CRTC[15] = 0x00;
  282. par->CRTC[16] = timings->VSyncStart & 0xFF;
  283. par->CRTC[17] = (timings->VSyncEnd & 0x0F) | 0x20;
  284. par->CRTC[18] = (timings->VDisplay - 1) & 0xFF;
  285. par->CRTC[19] = var->xres_virtual >> 4;
  286. par->CRTC[20] = 0x00;
  287. par->CRTC[21] = (timings->VDisplay - 1) & 0xFF;
  288. par->CRTC[22] = (timings->VTotal - 1) & 0xFF;
  289. par->CRTC[23] = 0xC3;
  290. par->CRTC[24] = 0xFF;
  291. /*
  292. * are these unnecessary?
  293. * vgaHWHBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
  294. * vgaHWVBlankKGA(mode, regp, 0, KGA_FIX_OVERSCAN | KGA_ENABLE_ON_ZERO);
  295. */
  296. /*
  297. * Graphics Display Controller
  298. */
  299. par->Graphics[0] = 0x00;
  300. par->Graphics[1] = 0x00;
  301. par->Graphics[2] = 0x00;
  302. par->Graphics[3] = 0x00;
  303. par->Graphics[4] = 0x00;
  304. par->Graphics[5] = 0x40;
  305. par->Graphics[6] = 0x05; /* only map 64k VGA memory !!!! */
  306. par->Graphics[7] = 0x0F;
  307. par->Graphics[8] = 0xFF;
  308. par->Attribute[0] = 0x00; /* standard colormap translation */
  309. par->Attribute[1] = 0x01;
  310. par->Attribute[2] = 0x02;
  311. par->Attribute[3] = 0x03;
  312. par->Attribute[4] = 0x04;
  313. par->Attribute[5] = 0x05;
  314. par->Attribute[6] = 0x06;
  315. par->Attribute[7] = 0x07;
  316. par->Attribute[8] = 0x08;
  317. par->Attribute[9] = 0x09;
  318. par->Attribute[10] = 0x0A;
  319. par->Attribute[11] = 0x0B;
  320. par->Attribute[12] = 0x0C;
  321. par->Attribute[13] = 0x0D;
  322. par->Attribute[14] = 0x0E;
  323. par->Attribute[15] = 0x0F;
  324. par->Attribute[16] = 0x41;
  325. par->Attribute[17] = 0xFF;
  326. par->Attribute[18] = 0x0F;
  327. par->Attribute[19] = 0x00;
  328. par->Attribute[20] = 0x00;
  329. return 0;
  330. }
  331. static void vgaHWLock(struct vgastate *state)
  332. {
  333. /* Protect CRTC[0-7] */
  334. vga_wcrt(state->vgabase, 0x11, vga_rcrt(state->vgabase, 0x11) | 0x80);
  335. }
  336. static void vgaHWUnlock(void)
  337. {
  338. /* Unprotect CRTC[0-7] */
  339. vga_wcrt(NULL, 0x11, vga_rcrt(NULL, 0x11) & ~0x80);
  340. }
  341. static void neoLock(struct vgastate *state)
  342. {
  343. vga_wgfx(state->vgabase, 0x09, 0x00);
  344. vgaHWLock(state);
  345. }
  346. static void neoUnlock(void)
  347. {
  348. vgaHWUnlock();
  349. vga_wgfx(NULL, 0x09, 0x26);
  350. }
  351. /*
  352. * VGA Palette management
  353. */
  354. static int paletteEnabled = 0;
  355. static inline void VGAenablePalette(void)
  356. {
  357. vga_r(NULL, VGA_IS1_RC);
  358. vga_w(NULL, VGA_ATT_W, 0x00);
  359. paletteEnabled = 1;
  360. }
  361. static inline void VGAdisablePalette(void)
  362. {
  363. vga_r(NULL, VGA_IS1_RC);
  364. vga_w(NULL, VGA_ATT_W, 0x20);
  365. paletteEnabled = 0;
  366. }
  367. static inline void VGAwATTR(u8 index, u8 value)
  368. {
  369. if (paletteEnabled)
  370. index &= ~0x20;
  371. else
  372. index |= 0x20;
  373. vga_r(NULL, VGA_IS1_RC);
  374. vga_wattr(NULL, index, value);
  375. }
  376. static void vgaHWProtect(int on)
  377. {
  378. unsigned char tmp;
  379. if (on) {
  380. /*
  381. * Turn off screen and disable sequencer.
  382. */
  383. tmp = vga_rseq(NULL, 0x01);
  384. vga_wseq(NULL, 0x00, 0x01); /* Synchronous Reset */
  385. vga_wseq(NULL, 0x01, tmp | 0x20); /* disable the display */
  386. VGAenablePalette();
  387. } else {
  388. /*
  389. * Reenable sequencer, then turn on screen.
  390. */
  391. tmp = vga_rseq(NULL, 0x01);
  392. vga_wseq(NULL, 0x01, tmp & ~0x20); /* reenable display */
  393. vga_wseq(NULL, 0x00, 0x03); /* clear synchronousreset */
  394. VGAdisablePalette();
  395. }
  396. }
  397. static void vgaHWRestore(const struct fb_info *info,
  398. const struct neofb_par *par)
  399. {
  400. int i;
  401. vga_w(NULL, VGA_MIS_W, par->MiscOutReg);
  402. for (i = 1; i < 5; i++)
  403. vga_wseq(NULL, i, par->Sequencer[i]);
  404. /* Ensure CRTC registers 0-7 are unlocked by clearing bit 7 or CRTC[17] */
  405. vga_wcrt(NULL, 17, par->CRTC[17] & ~0x80);
  406. for (i = 0; i < 25; i++)
  407. vga_wcrt(NULL, i, par->CRTC[i]);
  408. for (i = 0; i < 9; i++)
  409. vga_wgfx(NULL, i, par->Graphics[i]);
  410. VGAenablePalette();
  411. for (i = 0; i < 21; i++)
  412. VGAwATTR(i, par->Attribute[i]);
  413. VGAdisablePalette();
  414. }
  415. /* -------------------- Hardware specific routines ------------------------- */
  416. /*
  417. * Hardware Acceleration for Neo2200+
  418. */
  419. static inline int neo2200_sync(struct fb_info *info)
  420. {
  421. struct neofb_par *par = info->par;
  422. while (readl(&par->neo2200->bltStat) & 1);
  423. return 0;
  424. }
  425. static inline void neo2200_wait_fifo(struct fb_info *info,
  426. int requested_fifo_space)
  427. {
  428. // ndev->neo.waitfifo_calls++;
  429. // ndev->neo.waitfifo_sum += requested_fifo_space;
  430. /* FIXME: does not work
  431. if (neo_fifo_space < requested_fifo_space)
  432. {
  433. neo_fifo_waitcycles++;
  434. while (1)
  435. {
  436. neo_fifo_space = (neo2200->bltStat >> 8);
  437. if (neo_fifo_space >= requested_fifo_space)
  438. break;
  439. }
  440. }
  441. else
  442. {
  443. neo_fifo_cache_hits++;
  444. }
  445. neo_fifo_space -= requested_fifo_space;
  446. */
  447. neo2200_sync(info);
  448. }
  449. static inline void neo2200_accel_init(struct fb_info *info,
  450. struct fb_var_screeninfo *var)
  451. {
  452. struct neofb_par *par = info->par;
  453. Neo2200 __iomem *neo2200 = par->neo2200;
  454. u32 bltMod, pitch;
  455. neo2200_sync(info);
  456. switch (var->bits_per_pixel) {
  457. case 8:
  458. bltMod = NEO_MODE1_DEPTH8;
  459. pitch = var->xres_virtual;
  460. break;
  461. case 15:
  462. case 16:
  463. bltMod = NEO_MODE1_DEPTH16;
  464. pitch = var->xres_virtual * 2;
  465. break;
  466. case 24:
  467. bltMod = NEO_MODE1_DEPTH24;
  468. pitch = var->xres_virtual * 3;
  469. break;
  470. default:
  471. printk(KERN_ERR
  472. "neofb: neo2200_accel_init: unexpected bits per pixel!\n");
  473. return;
  474. }
  475. writel(bltMod << 16, &neo2200->bltStat);
  476. writel((pitch << 16) | pitch, &neo2200->pitch);
  477. }
  478. /* --------------------------------------------------------------------- */
  479. static int
  480. neofb_open(struct fb_info *info, int user)
  481. {
  482. struct neofb_par *par = info->par;
  483. mutex_lock(&par->open_lock);
  484. if (!par->ref_count) {
  485. memset(&par->state, 0, sizeof(struct vgastate));
  486. par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
  487. save_vga(&par->state);
  488. }
  489. par->ref_count++;
  490. mutex_unlock(&par->open_lock);
  491. return 0;
  492. }
  493. static int
  494. neofb_release(struct fb_info *info, int user)
  495. {
  496. struct neofb_par *par = info->par;
  497. mutex_lock(&par->open_lock);
  498. if (!par->ref_count) {
  499. mutex_unlock(&par->open_lock);
  500. return -EINVAL;
  501. }
  502. if (par->ref_count == 1) {
  503. restore_vga(&par->state);
  504. }
  505. par->ref_count--;
  506. mutex_unlock(&par->open_lock);
  507. return 0;
  508. }
  509. static int
  510. neofb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  511. {
  512. struct neofb_par *par = info->par;
  513. unsigned int pixclock = var->pixclock;
  514. struct xtimings timings;
  515. int memlen, vramlen;
  516. int mode_ok = 0;
  517. DBG("neofb_check_var");
  518. if (!pixclock)
  519. pixclock = 10000; /* 10ns = 100MHz */
  520. timings.pixclock = 1000000000 / pixclock;
  521. if (timings.pixclock < 1)
  522. timings.pixclock = 1;
  523. if (timings.pixclock > par->maxClock)
  524. return -EINVAL;
  525. timings.dblscan = var->vmode & FB_VMODE_DOUBLE;
  526. timings.interlaced = var->vmode & FB_VMODE_INTERLACED;
  527. timings.HDisplay = var->xres;
  528. timings.HSyncStart = timings.HDisplay + var->right_margin;
  529. timings.HSyncEnd = timings.HSyncStart + var->hsync_len;
  530. timings.HTotal = timings.HSyncEnd + var->left_margin;
  531. timings.VDisplay = var->yres;
  532. timings.VSyncStart = timings.VDisplay + var->lower_margin;
  533. timings.VSyncEnd = timings.VSyncStart + var->vsync_len;
  534. timings.VTotal = timings.VSyncEnd + var->upper_margin;
  535. timings.sync = var->sync;
  536. /* Is the mode larger than the LCD panel? */
  537. if (par->internal_display &&
  538. ((var->xres > par->NeoPanelWidth) ||
  539. (var->yres > par->NeoPanelHeight))) {
  540. printk(KERN_INFO
  541. "Mode (%dx%d) larger than the LCD panel (%dx%d)\n",
  542. var->xres, var->yres, par->NeoPanelWidth,
  543. par->NeoPanelHeight);
  544. return -EINVAL;
  545. }
  546. /* Is the mode one of the acceptable sizes? */
  547. if (!par->internal_display)
  548. mode_ok = 1;
  549. else {
  550. switch (var->xres) {
  551. case 1280:
  552. if (var->yres == 1024)
  553. mode_ok = 1;
  554. break;
  555. case 1024:
  556. if (var->yres == 768)
  557. mode_ok = 1;
  558. break;
  559. case 800:
  560. if (var->yres == (par->libretto ? 480 : 600))
  561. mode_ok = 1;
  562. break;
  563. case 640:
  564. if (var->yres == 480)
  565. mode_ok = 1;
  566. break;
  567. }
  568. }
  569. if (!mode_ok) {
  570. printk(KERN_INFO
  571. "Mode (%dx%d) won't display properly on LCD\n",
  572. var->xres, var->yres);
  573. return -EINVAL;
  574. }
  575. var->red.msb_right = 0;
  576. var->green.msb_right = 0;
  577. var->blue.msb_right = 0;
  578. switch (var->bits_per_pixel) {
  579. case 8: /* PSEUDOCOLOUR, 256 */
  580. var->transp.offset = 0;
  581. var->transp.length = 0;
  582. var->red.offset = 0;
  583. var->red.length = 8;
  584. var->green.offset = 0;
  585. var->green.length = 8;
  586. var->blue.offset = 0;
  587. var->blue.length = 8;
  588. break;
  589. case 16: /* DIRECTCOLOUR, 64k */
  590. var->transp.offset = 0;
  591. var->transp.length = 0;
  592. var->red.offset = 11;
  593. var->red.length = 5;
  594. var->green.offset = 5;
  595. var->green.length = 6;
  596. var->blue.offset = 0;
  597. var->blue.length = 5;
  598. break;
  599. case 24: /* TRUECOLOUR, 16m */
  600. var->transp.offset = 0;
  601. var->transp.length = 0;
  602. var->red.offset = 16;
  603. var->red.length = 8;
  604. var->green.offset = 8;
  605. var->green.length = 8;
  606. var->blue.offset = 0;
  607. var->blue.length = 8;
  608. break;
  609. #ifdef NO_32BIT_SUPPORT_YET
  610. case 32: /* TRUECOLOUR, 16m */
  611. var->transp.offset = 24;
  612. var->transp.length = 8;
  613. var->red.offset = 16;
  614. var->red.length = 8;
  615. var->green.offset = 8;
  616. var->green.length = 8;
  617. var->blue.offset = 0;
  618. var->blue.length = 8;
  619. break;
  620. #endif
  621. default:
  622. printk(KERN_WARNING "neofb: no support for %dbpp\n",
  623. var->bits_per_pixel);
  624. return -EINVAL;
  625. }
  626. vramlen = info->fix.smem_len;
  627. if (vramlen > 4 * 1024 * 1024)
  628. vramlen = 4 * 1024 * 1024;
  629. if (var->yres_virtual < var->yres)
  630. var->yres_virtual = var->yres;
  631. if (var->xres_virtual < var->xres)
  632. var->xres_virtual = var->xres;
  633. memlen = var->xres_virtual * var->bits_per_pixel * var->yres_virtual >> 3;
  634. if (memlen > vramlen) {
  635. var->yres_virtual = vramlen * 8 / (var->xres_virtual *
  636. var->bits_per_pixel);
  637. memlen = var->xres_virtual * var->bits_per_pixel *
  638. var->yres_virtual / 8;
  639. }
  640. /* we must round yres/xres down, we already rounded y/xres_virtual up
  641. if it was possible. We should return -EINVAL, but I disagree */
  642. if (var->yres_virtual < var->yres)
  643. var->yres = var->yres_virtual;
  644. if (var->xres_virtual < var->xres)
  645. var->xres = var->xres_virtual;
  646. if (var->xoffset + var->xres > var->xres_virtual)
  647. var->xoffset = var->xres_virtual - var->xres;
  648. if (var->yoffset + var->yres > var->yres_virtual)
  649. var->yoffset = var->yres_virtual - var->yres;
  650. var->nonstd = 0;
  651. var->height = -1;
  652. var->width = -1;
  653. if (var->bits_per_pixel >= 24 || !par->neo2200)
  654. var->accel_flags &= ~FB_ACCELF_TEXT;
  655. return 0;
  656. }
  657. static int neofb_set_par(struct fb_info *info)
  658. {
  659. struct neofb_par *par = info->par;
  660. struct xtimings timings;
  661. unsigned char temp;
  662. int i, clock_hi = 0;
  663. int lcd_stretch;
  664. int hoffset, voffset;
  665. DBG("neofb_set_par");
  666. neoUnlock();
  667. vgaHWProtect(1); /* Blank the screen */
  668. timings.dblscan = info->var.vmode & FB_VMODE_DOUBLE;
  669. timings.interlaced = info->var.vmode & FB_VMODE_INTERLACED;
  670. timings.HDisplay = info->var.xres;
  671. timings.HSyncStart = timings.HDisplay + info->var.right_margin;
  672. timings.HSyncEnd = timings.HSyncStart + info->var.hsync_len;
  673. timings.HTotal = timings.HSyncEnd + info->var.left_margin;
  674. timings.VDisplay = info->var.yres;
  675. timings.VSyncStart = timings.VDisplay + info->var.lower_margin;
  676. timings.VSyncEnd = timings.VSyncStart + info->var.vsync_len;
  677. timings.VTotal = timings.VSyncEnd + info->var.upper_margin;
  678. timings.sync = info->var.sync;
  679. timings.pixclock = PICOS2KHZ(info->var.pixclock);
  680. if (timings.pixclock < 1)
  681. timings.pixclock = 1;
  682. /*
  683. * This will allocate the datastructure and initialize all of the
  684. * generic VGA registers.
  685. */
  686. if (vgaHWInit(&info->var, info, par, &timings))
  687. return -EINVAL;
  688. /*
  689. * The default value assigned by vgaHW.c is 0x41, but this does
  690. * not work for NeoMagic.
  691. */
  692. par->Attribute[16] = 0x01;
  693. switch (info->var.bits_per_pixel) {
  694. case 8:
  695. par->CRTC[0x13] = info->var.xres_virtual >> 3;
  696. par->ExtCRTOffset = info->var.xres_virtual >> 11;
  697. par->ExtColorModeSelect = 0x11;
  698. break;
  699. case 16:
  700. par->CRTC[0x13] = info->var.xres_virtual >> 2;
  701. par->ExtCRTOffset = info->var.xres_virtual >> 10;
  702. par->ExtColorModeSelect = 0x13;
  703. break;
  704. case 24:
  705. par->CRTC[0x13] = (info->var.xres_virtual * 3) >> 3;
  706. par->ExtCRTOffset = (info->var.xres_virtual * 3) >> 11;
  707. par->ExtColorModeSelect = 0x14;
  708. break;
  709. #ifdef NO_32BIT_SUPPORT_YET
  710. case 32: /* FIXME: guessed values */
  711. par->CRTC[0x13] = info->var.xres_virtual >> 1;
  712. par->ExtCRTOffset = info->var.xres_virtual >> 9;
  713. par->ExtColorModeSelect = 0x15;
  714. break;
  715. #endif
  716. default:
  717. break;
  718. }
  719. par->ExtCRTDispAddr = 0x10;
  720. /* Vertical Extension */
  721. par->VerticalExt = (((timings.VTotal - 2) & 0x400) >> 10)
  722. | (((timings.VDisplay - 1) & 0x400) >> 9)
  723. | (((timings.VSyncStart) & 0x400) >> 8)
  724. | (((timings.VSyncStart) & 0x400) >> 7);
  725. /* Fast write bursts on unless disabled. */
  726. if (par->pci_burst)
  727. par->SysIfaceCntl1 = 0x30;
  728. else
  729. par->SysIfaceCntl1 = 0x00;
  730. par->SysIfaceCntl2 = 0xc0; /* VESA Bios sets this to 0x80! */
  731. /* Initialize: by default, we want display config register to be read */
  732. par->PanelDispCntlRegRead = 1;
  733. /* Enable any user specified display devices. */
  734. par->PanelDispCntlReg1 = 0x00;
  735. if (par->internal_display)
  736. par->PanelDispCntlReg1 |= 0x02;
  737. if (par->external_display)
  738. par->PanelDispCntlReg1 |= 0x01;
  739. /* If the user did not specify any display devices, then... */
  740. if (par->PanelDispCntlReg1 == 0x00) {
  741. /* Default to internal (i.e., LCD) only. */
  742. par->PanelDispCntlReg1 = vga_rgfx(NULL, 0x20) & 0x03;
  743. }
  744. /* If we are using a fixed mode, then tell the chip we are. */
  745. switch (info->var.xres) {
  746. case 1280:
  747. par->PanelDispCntlReg1 |= 0x60;
  748. break;
  749. case 1024:
  750. par->PanelDispCntlReg1 |= 0x40;
  751. break;
  752. case 800:
  753. par->PanelDispCntlReg1 |= 0x20;
  754. break;
  755. case 640:
  756. default:
  757. break;
  758. }
  759. /* Setup shadow register locking. */
  760. switch (par->PanelDispCntlReg1 & 0x03) {
  761. case 0x01: /* External CRT only mode: */
  762. par->GeneralLockReg = 0x00;
  763. /* We need to program the VCLK for external display only mode. */
  764. par->ProgramVCLK = 1;
  765. break;
  766. case 0x02: /* Internal LCD only mode: */
  767. case 0x03: /* Simultaneous internal/external (LCD/CRT) mode: */
  768. par->GeneralLockReg = 0x01;
  769. /* Don't program the VCLK when using the LCD. */
  770. par->ProgramVCLK = 0;
  771. break;
  772. }
  773. /*
  774. * If the screen is to be stretched, turn on stretching for the
  775. * various modes.
  776. *
  777. * OPTION_LCD_STRETCH means stretching should be turned off!
  778. */
  779. par->PanelDispCntlReg2 = 0x00;
  780. par->PanelDispCntlReg3 = 0x00;
  781. if (par->lcd_stretch && (par->PanelDispCntlReg1 == 0x02) && /* LCD only */
  782. (info->var.xres != par->NeoPanelWidth)) {
  783. switch (info->var.xres) {
  784. case 320: /* Needs testing. KEM -- 24 May 98 */
  785. case 400: /* Needs testing. KEM -- 24 May 98 */
  786. case 640:
  787. case 800:
  788. case 1024:
  789. lcd_stretch = 1;
  790. par->PanelDispCntlReg2 |= 0xC6;
  791. break;
  792. default:
  793. lcd_stretch = 0;
  794. /* No stretching in these modes. */
  795. }
  796. } else
  797. lcd_stretch = 0;
  798. /*
  799. * If the screen is to be centerd, turn on the centering for the
  800. * various modes.
  801. */
  802. par->PanelVertCenterReg1 = 0x00;
  803. par->PanelVertCenterReg2 = 0x00;
  804. par->PanelVertCenterReg3 = 0x00;
  805. par->PanelVertCenterReg4 = 0x00;
  806. par->PanelVertCenterReg5 = 0x00;
  807. par->PanelHorizCenterReg1 = 0x00;
  808. par->PanelHorizCenterReg2 = 0x00;
  809. par->PanelHorizCenterReg3 = 0x00;
  810. par->PanelHorizCenterReg4 = 0x00;
  811. par->PanelHorizCenterReg5 = 0x00;
  812. if (par->PanelDispCntlReg1 & 0x02) {
  813. if (info->var.xres == par->NeoPanelWidth) {
  814. /*
  815. * No centering required when the requested display width
  816. * equals the panel width.
  817. */
  818. } else {
  819. par->PanelDispCntlReg2 |= 0x01;
  820. par->PanelDispCntlReg3 |= 0x10;
  821. /* Calculate the horizontal and vertical offsets. */
  822. if (!lcd_stretch) {
  823. hoffset =
  824. ((par->NeoPanelWidth -
  825. info->var.xres) >> 4) - 1;
  826. voffset =
  827. ((par->NeoPanelHeight -
  828. info->var.yres) >> 1) - 2;
  829. } else {
  830. /* Stretched modes cannot be centered. */
  831. hoffset = 0;
  832. voffset = 0;
  833. }
  834. switch (info->var.xres) {
  835. case 320: /* Needs testing. KEM -- 24 May 98 */
  836. par->PanelHorizCenterReg3 = hoffset;
  837. par->PanelVertCenterReg2 = voffset;
  838. break;
  839. case 400: /* Needs testing. KEM -- 24 May 98 */
  840. par->PanelHorizCenterReg4 = hoffset;
  841. par->PanelVertCenterReg1 = voffset;
  842. break;
  843. case 640:
  844. par->PanelHorizCenterReg1 = hoffset;
  845. par->PanelVertCenterReg3 = voffset;
  846. break;
  847. case 800:
  848. par->PanelHorizCenterReg2 = hoffset;
  849. par->PanelVertCenterReg4 = voffset;
  850. break;
  851. case 1024:
  852. par->PanelHorizCenterReg5 = hoffset;
  853. par->PanelVertCenterReg5 = voffset;
  854. break;
  855. case 1280:
  856. default:
  857. /* No centering in these modes. */
  858. break;
  859. }
  860. }
  861. }
  862. par->biosMode =
  863. neoFindMode(info->var.xres, info->var.yres,
  864. info->var.bits_per_pixel);
  865. /*
  866. * Calculate the VCLK that most closely matches the requested dot
  867. * clock.
  868. */
  869. neoCalcVCLK(info, par, timings.pixclock);
  870. /* Since we program the clocks ourselves, always use VCLK3. */
  871. par->MiscOutReg |= 0x0C;
  872. /* alread unlocked above */
  873. /* BOGUS vga_wgfx(NULL, 0x09, 0x26); */
  874. /* don't know what this is, but it's 0 from bootup anyway */
  875. vga_wgfx(NULL, 0x15, 0x00);
  876. /* was set to 0x01 by my bios in text and vesa modes */
  877. vga_wgfx(NULL, 0x0A, par->GeneralLockReg);
  878. /*
  879. * The color mode needs to be set before calling vgaHWRestore
  880. * to ensure the DAC is initialized properly.
  881. *
  882. * NOTE: Make sure we don't change bits make sure we don't change
  883. * any reserved bits.
  884. */
  885. temp = vga_rgfx(NULL, 0x90);
  886. switch (info->fix.accel) {
  887. case FB_ACCEL_NEOMAGIC_NM2070:
  888. temp &= 0xF0; /* Save bits 7:4 */
  889. temp |= (par->ExtColorModeSelect & ~0xF0);
  890. break;
  891. case FB_ACCEL_NEOMAGIC_NM2090:
  892. case FB_ACCEL_NEOMAGIC_NM2093:
  893. case FB_ACCEL_NEOMAGIC_NM2097:
  894. case FB_ACCEL_NEOMAGIC_NM2160:
  895. case FB_ACCEL_NEOMAGIC_NM2200:
  896. case FB_ACCEL_NEOMAGIC_NM2230:
  897. case FB_ACCEL_NEOMAGIC_NM2360:
  898. case FB_ACCEL_NEOMAGIC_NM2380:
  899. temp &= 0x70; /* Save bits 6:4 */
  900. temp |= (par->ExtColorModeSelect & ~0x70);
  901. break;
  902. }
  903. vga_wgfx(NULL, 0x90, temp);
  904. /*
  905. * In some rare cases a lockup might occur if we don't delay
  906. * here. (Reported by Miles Lane)
  907. */
  908. //mdelay(200);
  909. /*
  910. * Disable horizontal and vertical graphics and text expansions so
  911. * that vgaHWRestore works properly.
  912. */
  913. temp = vga_rgfx(NULL, 0x25);
  914. temp &= 0x39;
  915. vga_wgfx(NULL, 0x25, temp);
  916. /*
  917. * Sleep for 200ms to make sure that the two operations above have
  918. * had time to take effect.
  919. */
  920. mdelay(200);
  921. /*
  922. * This function handles restoring the generic VGA registers. */
  923. vgaHWRestore(info, par);
  924. /* linear colormap for non palettized modes */
  925. switch (info->var.bits_per_pixel) {
  926. case 8:
  927. /* PseudoColor, 256 */
  928. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  929. break;
  930. case 16:
  931. /* TrueColor, 64k */
  932. info->fix.visual = FB_VISUAL_TRUECOLOR;
  933. for (i = 0; i < 64; i++) {
  934. outb(i, 0x3c8);
  935. outb(i << 1, 0x3c9);
  936. outb(i, 0x3c9);
  937. outb(i << 1, 0x3c9);
  938. }
  939. break;
  940. case 24:
  941. #ifdef NO_32BIT_SUPPORT_YET
  942. case 32:
  943. #endif
  944. /* TrueColor, 16m */
  945. info->fix.visual = FB_VISUAL_TRUECOLOR;
  946. for (i = 0; i < 256; i++) {
  947. outb(i, 0x3c8);
  948. outb(i, 0x3c9);
  949. outb(i, 0x3c9);
  950. outb(i, 0x3c9);
  951. }
  952. break;
  953. }
  954. vga_wgfx(NULL, 0x0E, par->ExtCRTDispAddr);
  955. vga_wgfx(NULL, 0x0F, par->ExtCRTOffset);
  956. temp = vga_rgfx(NULL, 0x10);
  957. temp &= 0x0F; /* Save bits 3:0 */
  958. temp |= (par->SysIfaceCntl1 & ~0x0F); /* VESA Bios sets bit 1! */
  959. vga_wgfx(NULL, 0x10, temp);
  960. vga_wgfx(NULL, 0x11, par->SysIfaceCntl2);
  961. vga_wgfx(NULL, 0x15, 0 /*par->SingleAddrPage */ );
  962. vga_wgfx(NULL, 0x16, 0 /*par->DualAddrPage */ );
  963. temp = vga_rgfx(NULL, 0x20);
  964. switch (info->fix.accel) {
  965. case FB_ACCEL_NEOMAGIC_NM2070:
  966. temp &= 0xFC; /* Save bits 7:2 */
  967. temp |= (par->PanelDispCntlReg1 & ~0xFC);
  968. break;
  969. case FB_ACCEL_NEOMAGIC_NM2090:
  970. case FB_ACCEL_NEOMAGIC_NM2093:
  971. case FB_ACCEL_NEOMAGIC_NM2097:
  972. case FB_ACCEL_NEOMAGIC_NM2160:
  973. temp &= 0xDC; /* Save bits 7:6,4:2 */
  974. temp |= (par->PanelDispCntlReg1 & ~0xDC);
  975. break;
  976. case FB_ACCEL_NEOMAGIC_NM2200:
  977. case FB_ACCEL_NEOMAGIC_NM2230:
  978. case FB_ACCEL_NEOMAGIC_NM2360:
  979. case FB_ACCEL_NEOMAGIC_NM2380:
  980. temp &= 0x98; /* Save bits 7,4:3 */
  981. temp |= (par->PanelDispCntlReg1 & ~0x98);
  982. break;
  983. }
  984. vga_wgfx(NULL, 0x20, temp);
  985. temp = vga_rgfx(NULL, 0x25);
  986. temp &= 0x38; /* Save bits 5:3 */
  987. temp |= (par->PanelDispCntlReg2 & ~0x38);
  988. vga_wgfx(NULL, 0x25, temp);
  989. if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
  990. temp = vga_rgfx(NULL, 0x30);
  991. temp &= 0xEF; /* Save bits 7:5 and bits 3:0 */
  992. temp |= (par->PanelDispCntlReg3 & ~0xEF);
  993. vga_wgfx(NULL, 0x30, temp);
  994. }
  995. vga_wgfx(NULL, 0x28, par->PanelVertCenterReg1);
  996. vga_wgfx(NULL, 0x29, par->PanelVertCenterReg2);
  997. vga_wgfx(NULL, 0x2a, par->PanelVertCenterReg3);
  998. if (info->fix.accel != FB_ACCEL_NEOMAGIC_NM2070) {
  999. vga_wgfx(NULL, 0x32, par->PanelVertCenterReg4);
  1000. vga_wgfx(NULL, 0x33, par->PanelHorizCenterReg1);
  1001. vga_wgfx(NULL, 0x34, par->PanelHorizCenterReg2);
  1002. vga_wgfx(NULL, 0x35, par->PanelHorizCenterReg3);
  1003. }
  1004. if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2160)
  1005. vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
  1006. if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
  1007. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
  1008. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
  1009. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
  1010. vga_wgfx(NULL, 0x36, par->PanelHorizCenterReg4);
  1011. vga_wgfx(NULL, 0x37, par->PanelVertCenterReg5);
  1012. vga_wgfx(NULL, 0x38, par->PanelHorizCenterReg5);
  1013. clock_hi = 1;
  1014. }
  1015. /* Program VCLK3 if needed. */
  1016. if (par->ProgramVCLK && ((vga_rgfx(NULL, 0x9B) != par->VCLK3NumeratorLow)
  1017. || (vga_rgfx(NULL, 0x9F) != par->VCLK3Denominator)
  1018. || (clock_hi && ((vga_rgfx(NULL, 0x8F) & ~0x0f)
  1019. != (par->VCLK3NumeratorHigh &
  1020. ~0x0F))))) {
  1021. vga_wgfx(NULL, 0x9B, par->VCLK3NumeratorLow);
  1022. if (clock_hi) {
  1023. temp = vga_rgfx(NULL, 0x8F);
  1024. temp &= 0x0F; /* Save bits 3:0 */
  1025. temp |= (par->VCLK3NumeratorHigh & ~0x0F);
  1026. vga_wgfx(NULL, 0x8F, temp);
  1027. }
  1028. vga_wgfx(NULL, 0x9F, par->VCLK3Denominator);
  1029. }
  1030. if (par->biosMode)
  1031. vga_wcrt(NULL, 0x23, par->biosMode);
  1032. vga_wgfx(NULL, 0x93, 0xc0); /* Gives 5x faster framebuffer writes !!! */
  1033. /* Program vertical extension register */
  1034. if (info->fix.accel == FB_ACCEL_NEOMAGIC_NM2200 ||
  1035. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2230 ||
  1036. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2360 ||
  1037. info->fix.accel == FB_ACCEL_NEOMAGIC_NM2380) {
  1038. vga_wcrt(NULL, 0x70, par->VerticalExt);
  1039. }
  1040. vgaHWProtect(0); /* Turn on screen */
  1041. /* Calling this also locks offset registers required in update_start */
  1042. neoLock(&par->state);
  1043. info->fix.line_length =
  1044. info->var.xres_virtual * (info->var.bits_per_pixel >> 3);
  1045. switch (info->fix.accel) {
  1046. case FB_ACCEL_NEOMAGIC_NM2200:
  1047. case FB_ACCEL_NEOMAGIC_NM2230:
  1048. case FB_ACCEL_NEOMAGIC_NM2360:
  1049. case FB_ACCEL_NEOMAGIC_NM2380:
  1050. neo2200_accel_init(info, &info->var);
  1051. break;
  1052. default:
  1053. break;
  1054. }
  1055. return 0;
  1056. }
  1057. static void neofb_update_start(struct fb_info *info,
  1058. struct fb_var_screeninfo *var)
  1059. {
  1060. struct neofb_par *par = info->par;
  1061. struct vgastate *state = &par->state;
  1062. int oldExtCRTDispAddr;
  1063. int Base;
  1064. DBG("neofb_update_start");
  1065. Base = (var->yoffset * var->xres_virtual + var->xoffset) >> 2;
  1066. Base *= (var->bits_per_pixel + 7) / 8;
  1067. neoUnlock();
  1068. /*
  1069. * These are the generic starting address registers.
  1070. */
  1071. vga_wcrt(state->vgabase, 0x0C, (Base & 0x00FF00) >> 8);
  1072. vga_wcrt(state->vgabase, 0x0D, (Base & 0x00FF));
  1073. /*
  1074. * Make sure we don't clobber some other bits that might already
  1075. * have been set. NOTE: NM2200 has a writable bit 3, but it shouldn't
  1076. * be needed.
  1077. */
  1078. oldExtCRTDispAddr = vga_rgfx(NULL, 0x0E);
  1079. vga_wgfx(state->vgabase, 0x0E, (((Base >> 16) & 0x0f) | (oldExtCRTDispAddr & 0xf0)));
  1080. neoLock(state);
  1081. }
  1082. /*
  1083. * Pan or Wrap the Display
  1084. */
  1085. static int neofb_pan_display(struct fb_var_screeninfo *var,
  1086. struct fb_info *info)
  1087. {
  1088. u_int y_bottom;
  1089. y_bottom = var->yoffset;
  1090. if (!(var->vmode & FB_VMODE_YWRAP))
  1091. y_bottom += var->yres;
  1092. if (var->xoffset > (var->xres_virtual - var->xres))
  1093. return -EINVAL;
  1094. if (y_bottom > info->var.yres_virtual)
  1095. return -EINVAL;
  1096. neofb_update_start(info, var);
  1097. info->var.xoffset = var->xoffset;
  1098. info->var.yoffset = var->yoffset;
  1099. if (var->vmode & FB_VMODE_YWRAP)
  1100. info->var.vmode |= FB_VMODE_YWRAP;
  1101. else
  1102. info->var.vmode &= ~FB_VMODE_YWRAP;
  1103. return 0;
  1104. }
  1105. static int neofb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  1106. u_int transp, struct fb_info *fb)
  1107. {
  1108. if (regno >= fb->cmap.len || regno > 255)
  1109. return -EINVAL;
  1110. if (fb->var.bits_per_pixel <= 8) {
  1111. outb(regno, 0x3c8);
  1112. outb(red >> 10, 0x3c9);
  1113. outb(green >> 10, 0x3c9);
  1114. outb(blue >> 10, 0x3c9);
  1115. } else if (regno < 16) {
  1116. switch (fb->var.bits_per_pixel) {
  1117. case 16:
  1118. ((u32 *) fb->pseudo_palette)[regno] =
  1119. ((red & 0xf800)) | ((green & 0xfc00) >> 5) |
  1120. ((blue & 0xf800) >> 11);
  1121. break;
  1122. case 24:
  1123. ((u32 *) fb->pseudo_palette)[regno] =
  1124. ((red & 0xff00) << 8) | ((green & 0xff00)) |
  1125. ((blue & 0xff00) >> 8);
  1126. break;
  1127. #ifdef NO_32BIT_SUPPORT_YET
  1128. case 32:
  1129. ((u32 *) fb->pseudo_palette)[regno] =
  1130. ((transp & 0xff00) << 16) | ((red & 0xff00) << 8) |
  1131. ((green & 0xff00)) | ((blue & 0xff00) >> 8);
  1132. break;
  1133. #endif
  1134. default:
  1135. return 1;
  1136. }
  1137. }
  1138. return 0;
  1139. }
  1140. /*
  1141. * (Un)Blank the display.
  1142. */
  1143. static int neofb_blank(int blank_mode, struct fb_info *info)
  1144. {
  1145. /*
  1146. * Blank the screen if blank_mode != 0, else unblank.
  1147. * Return 0 if blanking succeeded, != 0 if un-/blanking failed due to
  1148. * e.g. a video mode which doesn't support it. Implements VESA suspend
  1149. * and powerdown modes for monitors, and backlight control on LCDs.
  1150. * blank_mode == 0: unblanked (backlight on)
  1151. * blank_mode == 1: blank (backlight on)
  1152. * blank_mode == 2: suspend vsync (backlight off)
  1153. * blank_mode == 3: suspend hsync (backlight off)
  1154. * blank_mode == 4: powerdown (backlight off)
  1155. *
  1156. * wms...Enable VESA DPMS compatible powerdown mode
  1157. * run "setterm -powersave powerdown" to take advantage
  1158. */
  1159. struct neofb_par *par = info->par;
  1160. int seqflags, lcdflags, dpmsflags, reg, tmpdisp;
  1161. /*
  1162. * Read back the register bits related to display configuration. They might
  1163. * have been changed underneath the driver via Fn key stroke.
  1164. */
  1165. neoUnlock();
  1166. tmpdisp = vga_rgfx(NULL, 0x20) & 0x03;
  1167. neoLock(&par->state);
  1168. /* In case we blank the screen, we want to store the possibly new
  1169. * configuration in the driver. During un-blank, we re-apply this setting,
  1170. * since the LCD bit will be cleared in order to switch off the backlight.
  1171. */
  1172. if (par->PanelDispCntlRegRead) {
  1173. par->PanelDispCntlReg1 = tmpdisp;
  1174. }
  1175. par->PanelDispCntlRegRead = !blank_mode;
  1176. switch (blank_mode) {
  1177. case FB_BLANK_POWERDOWN: /* powerdown - both sync lines down */
  1178. seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
  1179. lcdflags = 0; /* LCD off */
  1180. dpmsflags = NEO_GR01_SUPPRESS_HSYNC |
  1181. NEO_GR01_SUPPRESS_VSYNC;
  1182. #ifdef CONFIG_TOSHIBA
  1183. /* Do we still need this ? */
  1184. /* attempt to turn off backlight on toshiba; also turns off external */
  1185. {
  1186. SMMRegisters regs;
  1187. regs.eax = 0xff00; /* HCI_SET */
  1188. regs.ebx = 0x0002; /* HCI_BACKLIGHT */
  1189. regs.ecx = 0x0000; /* HCI_DISABLE */
  1190. tosh_smm(&regs);
  1191. }
  1192. #endif
  1193. break;
  1194. case FB_BLANK_HSYNC_SUSPEND: /* hsync off */
  1195. seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
  1196. lcdflags = 0; /* LCD off */
  1197. dpmsflags = NEO_GR01_SUPPRESS_HSYNC;
  1198. break;
  1199. case FB_BLANK_VSYNC_SUSPEND: /* vsync off */
  1200. seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
  1201. lcdflags = 0; /* LCD off */
  1202. dpmsflags = NEO_GR01_SUPPRESS_VSYNC;
  1203. break;
  1204. case FB_BLANK_NORMAL: /* just blank screen (backlight stays on) */
  1205. seqflags = VGA_SR01_SCREEN_OFF; /* Disable sequencer */
  1206. /*
  1207. * During a blank operation with the LID shut, we might store "LCD off"
  1208. * by mistake. Due to timing issues, the BIOS may switch the lights
  1209. * back on, and we turn it back off once we "unblank".
  1210. *
  1211. * So here is an attempt to implement ">=" - if we are in the process
  1212. * of unblanking, and the LCD bit is unset in the driver but set in the
  1213. * register, we must keep it.
  1214. */
  1215. lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
  1216. dpmsflags = 0x00; /* no hsync/vsync suppression */
  1217. break;
  1218. case FB_BLANK_UNBLANK: /* unblank */
  1219. seqflags = 0; /* Enable sequencer */
  1220. lcdflags = ((par->PanelDispCntlReg1 | tmpdisp) & 0x02); /* LCD normal */
  1221. dpmsflags = 0x00; /* no hsync/vsync suppression */
  1222. #ifdef CONFIG_TOSHIBA
  1223. /* Do we still need this ? */
  1224. /* attempt to re-enable backlight/external on toshiba */
  1225. {
  1226. SMMRegisters regs;
  1227. regs.eax = 0xff00; /* HCI_SET */
  1228. regs.ebx = 0x0002; /* HCI_BACKLIGHT */
  1229. regs.ecx = 0x0001; /* HCI_ENABLE */
  1230. tosh_smm(&regs);
  1231. }
  1232. #endif
  1233. break;
  1234. default: /* Anything else we don't understand; return 1 to tell
  1235. * fb_blank we didn't aactually do anything */
  1236. return 1;
  1237. }
  1238. neoUnlock();
  1239. reg = (vga_rseq(NULL, 0x01) & ~0x20) | seqflags;
  1240. vga_wseq(NULL, 0x01, reg);
  1241. reg = (vga_rgfx(NULL, 0x20) & ~0x02) | lcdflags;
  1242. vga_wgfx(NULL, 0x20, reg);
  1243. reg = (vga_rgfx(NULL, 0x01) & ~0xF0) | 0x80 | dpmsflags;
  1244. vga_wgfx(NULL, 0x01, reg);
  1245. neoLock(&par->state);
  1246. return 0;
  1247. }
  1248. static void
  1249. neo2200_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  1250. {
  1251. struct neofb_par *par = info->par;
  1252. u_long dst, rop;
  1253. dst = rect->dx + rect->dy * info->var.xres_virtual;
  1254. rop = rect->rop ? 0x060000 : 0x0c0000;
  1255. neo2200_wait_fifo(info, 4);
  1256. /* set blt control */
  1257. writel(NEO_BC3_FIFO_EN |
  1258. NEO_BC0_SRC_IS_FG | NEO_BC3_SKIP_MAPPING |
  1259. // NEO_BC3_DST_XY_ADDR |
  1260. // NEO_BC3_SRC_XY_ADDR |
  1261. rop, &par->neo2200->bltCntl);
  1262. switch (info->var.bits_per_pixel) {
  1263. case 8:
  1264. writel(rect->color, &par->neo2200->fgColor);
  1265. break;
  1266. case 16:
  1267. case 24:
  1268. writel(((u32 *) (info->pseudo_palette))[rect->color],
  1269. &par->neo2200->fgColor);
  1270. break;
  1271. }
  1272. writel(dst * ((info->var.bits_per_pixel + 7) >> 3),
  1273. &par->neo2200->dstStart);
  1274. writel((rect->height << 16) | (rect->width & 0xffff),
  1275. &par->neo2200->xyExt);
  1276. }
  1277. static void
  1278. neo2200_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  1279. {
  1280. u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
  1281. struct neofb_par *par = info->par;
  1282. u_long src, dst, bltCntl;
  1283. bltCntl = NEO_BC3_FIFO_EN | NEO_BC3_SKIP_MAPPING | 0x0C0000;
  1284. if ((dy > sy) || ((dy == sy) && (dx > sx))) {
  1285. /* Start with the lower right corner */
  1286. sy += (area->height - 1);
  1287. dy += (area->height - 1);
  1288. sx += (area->width - 1);
  1289. dx += (area->width - 1);
  1290. bltCntl |= NEO_BC0_X_DEC | NEO_BC0_DST_Y_DEC | NEO_BC0_SRC_Y_DEC;
  1291. }
  1292. src = sx * (info->var.bits_per_pixel >> 3) + sy*info->fix.line_length;
  1293. dst = dx * (info->var.bits_per_pixel >> 3) + dy*info->fix.line_length;
  1294. neo2200_wait_fifo(info, 4);
  1295. /* set blt control */
  1296. writel(bltCntl, &par->neo2200->bltCntl);
  1297. writel(src, &par->neo2200->srcStart);
  1298. writel(dst, &par->neo2200->dstStart);
  1299. writel((area->height << 16) | (area->width & 0xffff),
  1300. &par->neo2200->xyExt);
  1301. }
  1302. static void
  1303. neo2200_imageblit(struct fb_info *info, const struct fb_image *image)
  1304. {
  1305. struct neofb_par *par = info->par;
  1306. int s_pitch = (image->width * image->depth + 7) >> 3;
  1307. int scan_align = info->pixmap.scan_align - 1;
  1308. int buf_align = info->pixmap.buf_align - 1;
  1309. int bltCntl_flags, d_pitch, data_len;
  1310. // The data is padded for the hardware
  1311. d_pitch = (s_pitch + scan_align) & ~scan_align;
  1312. data_len = ((d_pitch * image->height) + buf_align) & ~buf_align;
  1313. neo2200_sync(info);
  1314. if (image->depth == 1) {
  1315. if (info->var.bits_per_pixel == 24 && image->width < 16) {
  1316. /* FIXME. There is a bug with accelerated color-expanded
  1317. * transfers in 24 bit mode if the image being transferred
  1318. * is less than 16 bits wide. This is due to insufficient
  1319. * padding when writing the image. We need to adjust
  1320. * struct fb_pixmap. Not yet done. */
  1321. return cfb_imageblit(info, image);
  1322. }
  1323. bltCntl_flags = NEO_BC0_SRC_MONO;
  1324. } else if (image->depth == info->var.bits_per_pixel) {
  1325. bltCntl_flags = 0;
  1326. } else {
  1327. /* We don't currently support hardware acceleration if image
  1328. * depth is different from display */
  1329. return cfb_imageblit(info, image);
  1330. }
  1331. switch (info->var.bits_per_pixel) {
  1332. case 8:
  1333. writel(image->fg_color, &par->neo2200->fgColor);
  1334. writel(image->bg_color, &par->neo2200->bgColor);
  1335. break;
  1336. case 16:
  1337. case 24:
  1338. writel(((u32 *) (info->pseudo_palette))[image->fg_color],
  1339. &par->neo2200->fgColor);
  1340. writel(((u32 *) (info->pseudo_palette))[image->bg_color],
  1341. &par->neo2200->bgColor);
  1342. break;
  1343. }
  1344. writel(NEO_BC0_SYS_TO_VID |
  1345. NEO_BC3_SKIP_MAPPING | bltCntl_flags |
  1346. // NEO_BC3_DST_XY_ADDR |
  1347. 0x0c0000, &par->neo2200->bltCntl);
  1348. writel(0, &par->neo2200->srcStart);
  1349. // par->neo2200->dstStart = (image->dy << 16) | (image->dx & 0xffff);
  1350. writel(((image->dx & 0xffff) * (info->var.bits_per_pixel >> 3) +
  1351. image->dy * info->fix.line_length), &par->neo2200->dstStart);
  1352. writel((image->height << 16) | (image->width & 0xffff),
  1353. &par->neo2200->xyExt);
  1354. memcpy_toio(par->mmio_vbase + 0x100000, image->data, data_len);
  1355. }
  1356. static void
  1357. neofb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  1358. {
  1359. switch (info->fix.accel) {
  1360. case FB_ACCEL_NEOMAGIC_NM2200:
  1361. case FB_ACCEL_NEOMAGIC_NM2230:
  1362. case FB_ACCEL_NEOMAGIC_NM2360:
  1363. case FB_ACCEL_NEOMAGIC_NM2380:
  1364. neo2200_fillrect(info, rect);
  1365. break;
  1366. default:
  1367. cfb_fillrect(info, rect);
  1368. break;
  1369. }
  1370. }
  1371. static void
  1372. neofb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  1373. {
  1374. switch (info->fix.accel) {
  1375. case FB_ACCEL_NEOMAGIC_NM2200:
  1376. case FB_ACCEL_NEOMAGIC_NM2230:
  1377. case FB_ACCEL_NEOMAGIC_NM2360:
  1378. case FB_ACCEL_NEOMAGIC_NM2380:
  1379. neo2200_copyarea(info, area);
  1380. break;
  1381. default:
  1382. cfb_copyarea(info, area);
  1383. break;
  1384. }
  1385. }
  1386. static void
  1387. neofb_imageblit(struct fb_info *info, const struct fb_image *image)
  1388. {
  1389. switch (info->fix.accel) {
  1390. case FB_ACCEL_NEOMAGIC_NM2200:
  1391. case FB_ACCEL_NEOMAGIC_NM2230:
  1392. case FB_ACCEL_NEOMAGIC_NM2360:
  1393. case FB_ACCEL_NEOMAGIC_NM2380:
  1394. neo2200_imageblit(info, image);
  1395. break;
  1396. default:
  1397. cfb_imageblit(info, image);
  1398. break;
  1399. }
  1400. }
  1401. static int
  1402. neofb_sync(struct fb_info *info)
  1403. {
  1404. switch (info->fix.accel) {
  1405. case FB_ACCEL_NEOMAGIC_NM2200:
  1406. case FB_ACCEL_NEOMAGIC_NM2230:
  1407. case FB_ACCEL_NEOMAGIC_NM2360:
  1408. case FB_ACCEL_NEOMAGIC_NM2380:
  1409. neo2200_sync(info);
  1410. break;
  1411. default:
  1412. break;
  1413. }
  1414. return 0;
  1415. }
  1416. /*
  1417. static void
  1418. neofb_draw_cursor(struct fb_info *info, u8 *dst, u8 *src, unsigned int width)
  1419. {
  1420. //memset_io(info->sprite.addr, 0xff, 1);
  1421. }
  1422. static int
  1423. neofb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  1424. {
  1425. struct neofb_par *par = (struct neofb_par *) info->par;
  1426. * Disable cursor *
  1427. write_le32(NEOREG_CURSCNTL, ~NEO_CURS_ENABLE, par);
  1428. if (cursor->set & FB_CUR_SETPOS) {
  1429. u32 x = cursor->image.dx;
  1430. u32 y = cursor->image.dy;
  1431. info->cursor.image.dx = x;
  1432. info->cursor.image.dy = y;
  1433. write_le32(NEOREG_CURSX, x, par);
  1434. write_le32(NEOREG_CURSY, y, par);
  1435. }
  1436. if (cursor->set & FB_CUR_SETSIZE) {
  1437. info->cursor.image.height = cursor->image.height;
  1438. info->cursor.image.width = cursor->image.width;
  1439. }
  1440. if (cursor->set & FB_CUR_SETHOT)
  1441. info->cursor.hot = cursor->hot;
  1442. if (cursor->set & FB_CUR_SETCMAP) {
  1443. if (cursor->image.depth == 1) {
  1444. u32 fg = cursor->image.fg_color;
  1445. u32 bg = cursor->image.bg_color;
  1446. info->cursor.image.fg_color = fg;
  1447. info->cursor.image.bg_color = bg;
  1448. fg = ((fg & 0xff0000) >> 16) | ((fg & 0xff) << 16) | (fg & 0xff00);
  1449. bg = ((bg & 0xff0000) >> 16) | ((bg & 0xff) << 16) | (bg & 0xff00);
  1450. write_le32(NEOREG_CURSFGCOLOR, fg, par);
  1451. write_le32(NEOREG_CURSBGCOLOR, bg, par);
  1452. }
  1453. }
  1454. if (cursor->set & FB_CUR_SETSHAPE)
  1455. fb_load_cursor_image(info);
  1456. if (info->cursor.enable)
  1457. write_le32(NEOREG_CURSCNTL, NEO_CURS_ENABLE, par);
  1458. return 0;
  1459. }
  1460. */
  1461. static struct fb_ops neofb_ops = {
  1462. .owner = THIS_MODULE,
  1463. .fb_open = neofb_open,
  1464. .fb_release = neofb_release,
  1465. .fb_check_var = neofb_check_var,
  1466. .fb_set_par = neofb_set_par,
  1467. .fb_setcolreg = neofb_setcolreg,
  1468. .fb_pan_display = neofb_pan_display,
  1469. .fb_blank = neofb_blank,
  1470. .fb_sync = neofb_sync,
  1471. .fb_fillrect = neofb_fillrect,
  1472. .fb_copyarea = neofb_copyarea,
  1473. .fb_imageblit = neofb_imageblit,
  1474. };
  1475. /* --------------------------------------------------------------------- */
  1476. static struct fb_videomode __devinitdata mode800x480 = {
  1477. .xres = 800,
  1478. .yres = 480,
  1479. .pixclock = 25000,
  1480. .left_margin = 88,
  1481. .right_margin = 40,
  1482. .upper_margin = 23,
  1483. .lower_margin = 1,
  1484. .hsync_len = 128,
  1485. .vsync_len = 4,
  1486. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  1487. .vmode = FB_VMODE_NONINTERLACED
  1488. };
  1489. static int __devinit neo_map_mmio(struct fb_info *info,
  1490. struct pci_dev *dev)
  1491. {
  1492. struct neofb_par *par = info->par;
  1493. DBG("neo_map_mmio");
  1494. switch (info->fix.accel) {
  1495. case FB_ACCEL_NEOMAGIC_NM2070:
  1496. info->fix.mmio_start = pci_resource_start(dev, 0)+
  1497. 0x100000;
  1498. break;
  1499. case FB_ACCEL_NEOMAGIC_NM2090:
  1500. case FB_ACCEL_NEOMAGIC_NM2093:
  1501. info->fix.mmio_start = pci_resource_start(dev, 0)+
  1502. 0x200000;
  1503. break;
  1504. case FB_ACCEL_NEOMAGIC_NM2160:
  1505. case FB_ACCEL_NEOMAGIC_NM2097:
  1506. case FB_ACCEL_NEOMAGIC_NM2200:
  1507. case FB_ACCEL_NEOMAGIC_NM2230:
  1508. case FB_ACCEL_NEOMAGIC_NM2360:
  1509. case FB_ACCEL_NEOMAGIC_NM2380:
  1510. info->fix.mmio_start = pci_resource_start(dev, 1);
  1511. break;
  1512. default:
  1513. info->fix.mmio_start = pci_resource_start(dev, 0);
  1514. }
  1515. info->fix.mmio_len = MMIO_SIZE;
  1516. if (!request_mem_region
  1517. (info->fix.mmio_start, MMIO_SIZE, "memory mapped I/O")) {
  1518. printk("neofb: memory mapped IO in use\n");
  1519. return -EBUSY;
  1520. }
  1521. par->mmio_vbase = ioremap(info->fix.mmio_start, MMIO_SIZE);
  1522. if (!par->mmio_vbase) {
  1523. printk("neofb: unable to map memory mapped IO\n");
  1524. release_mem_region(info->fix.mmio_start,
  1525. info->fix.mmio_len);
  1526. return -ENOMEM;
  1527. } else
  1528. printk(KERN_INFO "neofb: mapped io at %p\n",
  1529. par->mmio_vbase);
  1530. return 0;
  1531. }
  1532. static void neo_unmap_mmio(struct fb_info *info)
  1533. {
  1534. struct neofb_par *par = info->par;
  1535. DBG("neo_unmap_mmio");
  1536. iounmap(par->mmio_vbase);
  1537. par->mmio_vbase = NULL;
  1538. release_mem_region(info->fix.mmio_start,
  1539. info->fix.mmio_len);
  1540. }
  1541. static int __devinit neo_map_video(struct fb_info *info,
  1542. struct pci_dev *dev, int video_len)
  1543. {
  1544. //unsigned long addr;
  1545. DBG("neo_map_video");
  1546. info->fix.smem_start = pci_resource_start(dev, 0);
  1547. info->fix.smem_len = video_len;
  1548. if (!request_mem_region(info->fix.smem_start, info->fix.smem_len,
  1549. "frame buffer")) {
  1550. printk("neofb: frame buffer in use\n");
  1551. return -EBUSY;
  1552. }
  1553. info->screen_base =
  1554. ioremap(info->fix.smem_start, info->fix.smem_len);
  1555. if (!info->screen_base) {
  1556. printk("neofb: unable to map screen memory\n");
  1557. release_mem_region(info->fix.smem_start,
  1558. info->fix.smem_len);
  1559. return -ENOMEM;
  1560. } else
  1561. printk(KERN_INFO "neofb: mapped framebuffer at %p\n",
  1562. info->screen_base);
  1563. #ifdef CONFIG_MTRR
  1564. ((struct neofb_par *)(info->par))->mtrr =
  1565. mtrr_add(info->fix.smem_start, pci_resource_len(dev, 0),
  1566. MTRR_TYPE_WRCOMB, 1);
  1567. #endif
  1568. /* Clear framebuffer, it's all white in memory after boot */
  1569. memset_io(info->screen_base, 0, info->fix.smem_len);
  1570. /* Allocate Cursor drawing pad.
  1571. info->fix.smem_len -= PAGE_SIZE;
  1572. addr = info->fix.smem_start + info->fix.smem_len;
  1573. write_le32(NEOREG_CURSMEMPOS, ((0x000f & (addr >> 10)) << 8) |
  1574. ((0x0ff0 & (addr >> 10)) >> 4), par);
  1575. addr = (unsigned long) info->screen_base + info->fix.smem_len;
  1576. info->sprite.addr = (u8 *) addr; */
  1577. return 0;
  1578. }
  1579. static void neo_unmap_video(struct fb_info *info)
  1580. {
  1581. DBG("neo_unmap_video");
  1582. #ifdef CONFIG_MTRR
  1583. {
  1584. struct neofb_par *par = info->par;
  1585. mtrr_del(par->mtrr, info->fix.smem_start,
  1586. info->fix.smem_len);
  1587. }
  1588. #endif
  1589. iounmap(info->screen_base);
  1590. info->screen_base = NULL;
  1591. release_mem_region(info->fix.smem_start,
  1592. info->fix.smem_len);
  1593. }
  1594. static int __devinit neo_scan_monitor(struct fb_info *info)
  1595. {
  1596. struct neofb_par *par = info->par;
  1597. unsigned char type, display;
  1598. int w;
  1599. // Eventually we will have i2c support.
  1600. info->monspecs.modedb = kmalloc(sizeof(struct fb_videomode), GFP_KERNEL);
  1601. if (!info->monspecs.modedb)
  1602. return -ENOMEM;
  1603. info->monspecs.modedb_len = 1;
  1604. /* Determine the panel type */
  1605. vga_wgfx(NULL, 0x09, 0x26);
  1606. type = vga_rgfx(NULL, 0x21);
  1607. display = vga_rgfx(NULL, 0x20);
  1608. if (!par->internal_display && !par->external_display) {
  1609. par->internal_display = display & 2 || !(display & 3) ? 1 : 0;
  1610. par->external_display = display & 1;
  1611. printk (KERN_INFO "Autodetected %s display\n",
  1612. par->internal_display && par->external_display ? "simultaneous" :
  1613. par->internal_display ? "internal" : "external");
  1614. }
  1615. /* Determine panel width -- used in NeoValidMode. */
  1616. w = vga_rgfx(NULL, 0x20);
  1617. vga_wgfx(NULL, 0x09, 0x00);
  1618. switch ((w & 0x18) >> 3) {
  1619. case 0x00:
  1620. // 640x480@60
  1621. par->NeoPanelWidth = 640;
  1622. par->NeoPanelHeight = 480;
  1623. memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
  1624. break;
  1625. case 0x01:
  1626. par->NeoPanelWidth = 800;
  1627. if (par->libretto) {
  1628. par->NeoPanelHeight = 480;
  1629. memcpy(info->monspecs.modedb, &mode800x480, sizeof(struct fb_videomode));
  1630. } else {
  1631. // 800x600@60
  1632. par->NeoPanelHeight = 600;
  1633. memcpy(info->monspecs.modedb, &vesa_modes[8], sizeof(struct fb_videomode));
  1634. }
  1635. break;
  1636. case 0x02:
  1637. // 1024x768@60
  1638. par->NeoPanelWidth = 1024;
  1639. par->NeoPanelHeight = 768;
  1640. memcpy(info->monspecs.modedb, &vesa_modes[13], sizeof(struct fb_videomode));
  1641. break;
  1642. case 0x03:
  1643. /* 1280x1024@60 panel support needs to be added */
  1644. #ifdef NOT_DONE
  1645. par->NeoPanelWidth = 1280;
  1646. par->NeoPanelHeight = 1024;
  1647. memcpy(info->monspecs.modedb, &vesa_modes[20], sizeof(struct fb_videomode));
  1648. break;
  1649. #else
  1650. printk(KERN_ERR
  1651. "neofb: Only 640x480, 800x600/480 and 1024x768 panels are currently supported\n");
  1652. return -1;
  1653. #endif
  1654. default:
  1655. // 640x480@60
  1656. par->NeoPanelWidth = 640;
  1657. par->NeoPanelHeight = 480;
  1658. memcpy(info->monspecs.modedb, &vesa_modes[3], sizeof(struct fb_videomode));
  1659. break;
  1660. }
  1661. printk(KERN_INFO "Panel is a %dx%d %s %s display\n",
  1662. par->NeoPanelWidth,
  1663. par->NeoPanelHeight,
  1664. (type & 0x02) ? "color" : "monochrome",
  1665. (type & 0x10) ? "TFT" : "dual scan");
  1666. return 0;
  1667. }
  1668. static int __devinit neo_init_hw(struct fb_info *info)
  1669. {
  1670. struct neofb_par *par = info->par;
  1671. int videoRam = 896;
  1672. int maxClock = 65000;
  1673. int CursorMem = 1024;
  1674. int CursorOff = 0x100;
  1675. int linearSize = 1024;
  1676. int maxWidth = 1024;
  1677. int maxHeight = 1024;
  1678. DBG("neo_init_hw");
  1679. neoUnlock();
  1680. #if 0
  1681. printk(KERN_DEBUG "--- Neo extended register dump ---\n");
  1682. for (int w = 0; w < 0x85; w++)
  1683. printk(KERN_DEBUG "CR %p: %p\n", (void *) w,
  1684. (void *) vga_rcrt(NULL, w));
  1685. for (int w = 0; w < 0xC7; w++)
  1686. printk(KERN_DEBUG "GR %p: %p\n", (void *) w,
  1687. (void *) vga_rgfx(NULL, w));
  1688. #endif
  1689. switch (info->fix.accel) {
  1690. case FB_ACCEL_NEOMAGIC_NM2070:
  1691. videoRam = 896;
  1692. maxClock = 65000;
  1693. CursorMem = 2048;
  1694. CursorOff = 0x100;
  1695. linearSize = 1024;
  1696. maxWidth = 1024;
  1697. maxHeight = 1024;
  1698. break;
  1699. case FB_ACCEL_NEOMAGIC_NM2090:
  1700. case FB_ACCEL_NEOMAGIC_NM2093:
  1701. videoRam = 1152;
  1702. maxClock = 80000;
  1703. CursorMem = 2048;
  1704. CursorOff = 0x100;
  1705. linearSize = 2048;
  1706. maxWidth = 1024;
  1707. maxHeight = 1024;
  1708. break;
  1709. case FB_ACCEL_NEOMAGIC_NM2097:
  1710. videoRam = 1152;
  1711. maxClock = 80000;
  1712. CursorMem = 1024;
  1713. CursorOff = 0x100;
  1714. linearSize = 2048;
  1715. maxWidth = 1024;
  1716. maxHeight = 1024;
  1717. break;
  1718. case FB_ACCEL_NEOMAGIC_NM2160:
  1719. videoRam = 2048;
  1720. maxClock = 90000;
  1721. CursorMem = 1024;
  1722. CursorOff = 0x100;
  1723. linearSize = 2048;
  1724. maxWidth = 1024;
  1725. maxHeight = 1024;
  1726. break;
  1727. case FB_ACCEL_NEOMAGIC_NM2200:
  1728. videoRam = 2560;
  1729. maxClock = 110000;
  1730. CursorMem = 1024;
  1731. CursorOff = 0x1000;
  1732. linearSize = 4096;
  1733. maxWidth = 1280;
  1734. maxHeight = 1024; /* ???? */
  1735. par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
  1736. break;
  1737. case FB_ACCEL_NEOMAGIC_NM2230:
  1738. videoRam = 3008;
  1739. maxClock = 110000;
  1740. CursorMem = 1024;
  1741. CursorOff = 0x1000;
  1742. linearSize = 4096;
  1743. maxWidth = 1280;
  1744. maxHeight = 1024; /* ???? */
  1745. par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
  1746. break;
  1747. case FB_ACCEL_NEOMAGIC_NM2360:
  1748. videoRam = 4096;
  1749. maxClock = 110000;
  1750. CursorMem = 1024;
  1751. CursorOff = 0x1000;
  1752. linearSize = 4096;
  1753. maxWidth = 1280;
  1754. maxHeight = 1024; /* ???? */
  1755. par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
  1756. break;
  1757. case FB_ACCEL_NEOMAGIC_NM2380:
  1758. videoRam = 6144;
  1759. maxClock = 110000;
  1760. CursorMem = 1024;
  1761. CursorOff = 0x1000;
  1762. linearSize = 8192;
  1763. maxWidth = 1280;
  1764. maxHeight = 1024; /* ???? */
  1765. par->neo2200 = (Neo2200 __iomem *) par->mmio_vbase;
  1766. break;
  1767. }
  1768. /*
  1769. info->sprite.size = CursorMem;
  1770. info->sprite.scan_align = 1;
  1771. info->sprite.buf_align = 1;
  1772. info->sprite.flags = FB_PIXMAP_IO;
  1773. info->sprite.outbuf = neofb_draw_cursor;
  1774. */
  1775. par->maxClock = maxClock;
  1776. par->cursorOff = CursorOff;
  1777. return ((videoRam * 1024));
  1778. }
  1779. static struct fb_info *__devinit neo_alloc_fb_info(struct pci_dev *dev, const struct
  1780. pci_device_id *id)
  1781. {
  1782. struct fb_info *info;
  1783. struct neofb_par *par;
  1784. info = framebuffer_alloc(sizeof(struct neofb_par), &dev->dev);
  1785. if (!info)
  1786. return NULL;
  1787. par = info->par;
  1788. info->fix.accel = id->driver_data;
  1789. mutex_init(&par->open_lock);
  1790. par->pci_burst = !nopciburst;
  1791. par->lcd_stretch = !nostretch;
  1792. par->libretto = libretto;
  1793. par->internal_display = internal;
  1794. par->external_display = external;
  1795. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  1796. switch (info->fix.accel) {
  1797. case FB_ACCEL_NEOMAGIC_NM2070:
  1798. sprintf(info->fix.id, "MagicGraph 128");
  1799. break;
  1800. case FB_ACCEL_NEOMAGIC_NM2090:
  1801. sprintf(info->fix.id, "MagicGraph 128V");
  1802. break;
  1803. case FB_ACCEL_NEOMAGIC_NM2093:
  1804. sprintf(info->fix.id, "MagicGraph 128ZV");
  1805. break;
  1806. case FB_ACCEL_NEOMAGIC_NM2097:
  1807. sprintf(info->fix.id, "MagicGraph 128ZV+");
  1808. break;
  1809. case FB_ACCEL_NEOMAGIC_NM2160:
  1810. sprintf(info->fix.id, "MagicGraph 128XD");
  1811. break;
  1812. case FB_ACCEL_NEOMAGIC_NM2200:
  1813. sprintf(info->fix.id, "MagicGraph 256AV");
  1814. info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
  1815. FBINFO_HWACCEL_COPYAREA |
  1816. FBINFO_HWACCEL_FILLRECT;
  1817. break;
  1818. case FB_ACCEL_NEOMAGIC_NM2230:
  1819. sprintf(info->fix.id, "MagicGraph 256AV+");
  1820. info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
  1821. FBINFO_HWACCEL_COPYAREA |
  1822. FBINFO_HWACCEL_FILLRECT;
  1823. break;
  1824. case FB_ACCEL_NEOMAGIC_NM2360:
  1825. sprintf(info->fix.id, "MagicGraph 256ZX");
  1826. info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
  1827. FBINFO_HWACCEL_COPYAREA |
  1828. FBINFO_HWACCEL_FILLRECT;
  1829. break;
  1830. case FB_ACCEL_NEOMAGIC_NM2380:
  1831. sprintf(info->fix.id, "MagicGraph 256XL+");
  1832. info->flags |= FBINFO_HWACCEL_IMAGEBLIT |
  1833. FBINFO_HWACCEL_COPYAREA |
  1834. FBINFO_HWACCEL_FILLRECT;
  1835. break;
  1836. }
  1837. info->fix.type = FB_TYPE_PACKED_PIXELS;
  1838. info->fix.type_aux = 0;
  1839. info->fix.xpanstep = 0;
  1840. info->fix.ypanstep = 4;
  1841. info->fix.ywrapstep = 0;
  1842. info->fix.accel = id->driver_data;
  1843. info->fbops = &neofb_ops;
  1844. info->pseudo_palette = par->palette;
  1845. return info;
  1846. }
  1847. static void neo_free_fb_info(struct fb_info *info)
  1848. {
  1849. if (info) {
  1850. /*
  1851. * Free the colourmap
  1852. */
  1853. fb_dealloc_cmap(&info->cmap);
  1854. framebuffer_release(info);
  1855. }
  1856. }
  1857. /* --------------------------------------------------------------------- */
  1858. static int __devinit neofb_probe(struct pci_dev *dev,
  1859. const struct pci_device_id *id)
  1860. {
  1861. struct fb_info *info;
  1862. u_int h_sync, v_sync;
  1863. int video_len, err;
  1864. DBG("neofb_probe");
  1865. err = pci_enable_device(dev);
  1866. if (err)
  1867. return err;
  1868. err = -ENOMEM;
  1869. info = neo_alloc_fb_info(dev, id);
  1870. if (!info)
  1871. return err;
  1872. err = neo_map_mmio(info, dev);
  1873. if (err)
  1874. goto err_map_mmio;
  1875. err = neo_scan_monitor(info);
  1876. if (err)
  1877. goto err_scan_monitor;
  1878. video_len = neo_init_hw(info);
  1879. if (video_len < 0) {
  1880. err = video_len;
  1881. goto err_init_hw;
  1882. }
  1883. err = neo_map_video(info, dev, video_len);
  1884. if (err)
  1885. goto err_init_hw;
  1886. if (!fb_find_mode(&info->var, info, mode_option, NULL, 0,
  1887. info->monspecs.modedb, 16)) {
  1888. printk(KERN_ERR "neofb: Unable to find usable video mode.\n");
  1889. goto err_map_video;
  1890. }
  1891. /*
  1892. * Calculate the hsync and vsync frequencies. Note that
  1893. * we split the 1e12 constant up so that we can preserve
  1894. * the precision and fit the results into 32-bit registers.
  1895. * (1953125000 * 512 = 1e12)
  1896. */
  1897. h_sync = 1953125000 / info->var.pixclock;
  1898. h_sync =
  1899. h_sync * 512 / (info->var.xres + info->var.left_margin +
  1900. info->var.right_margin + info->var.hsync_len);
  1901. v_sync =
  1902. h_sync / (info->var.yres + info->var.upper_margin +
  1903. info->var.lower_margin + info->var.vsync_len);
  1904. printk(KERN_INFO "neofb v" NEOFB_VERSION
  1905. ": %dkB VRAM, using %dx%d, %d.%03dkHz, %dHz\n",
  1906. info->fix.smem_len >> 10, info->var.xres,
  1907. info->var.yres, h_sync / 1000, h_sync % 1000, v_sync);
  1908. if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
  1909. goto err_map_video;
  1910. err = register_framebuffer(info);
  1911. if (err < 0)
  1912. goto err_reg_fb;
  1913. printk(KERN_INFO "fb%d: %s frame buffer device\n",
  1914. info->node, info->fix.id);
  1915. /*
  1916. * Our driver data
  1917. */
  1918. pci_set_drvdata(dev, info);
  1919. return 0;
  1920. err_reg_fb:
  1921. fb_dealloc_cmap(&info->cmap);
  1922. err_map_video:
  1923. neo_unmap_video(info);
  1924. err_init_hw:
  1925. fb_destroy_modedb(info->monspecs.modedb);
  1926. err_scan_monitor:
  1927. neo_unmap_mmio(info);
  1928. err_map_mmio:
  1929. neo_free_fb_info(info);
  1930. return err;
  1931. }
  1932. static void __devexit neofb_remove(struct pci_dev *dev)
  1933. {
  1934. struct fb_info *info = pci_get_drvdata(dev);
  1935. DBG("neofb_remove");
  1936. if (info) {
  1937. /*
  1938. * If unregister_framebuffer fails, then
  1939. * we will be leaving hooks that could cause
  1940. * oopsen laying around.
  1941. */
  1942. if (unregister_framebuffer(info))
  1943. printk(KERN_WARNING
  1944. "neofb: danger danger! Oopsen imminent!\n");
  1945. neo_unmap_video(info);
  1946. fb_destroy_modedb(info->monspecs.modedb);
  1947. neo_unmap_mmio(info);
  1948. neo_free_fb_info(info);
  1949. /*
  1950. * Ensure that the driver data is no longer
  1951. * valid.
  1952. */
  1953. pci_set_drvdata(dev, NULL);
  1954. }
  1955. }
  1956. static struct pci_device_id neofb_devices[] = {
  1957. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2070,
  1958. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2070},
  1959. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2090,
  1960. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2090},
  1961. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2093,
  1962. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2093},
  1963. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2097,
  1964. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2097},
  1965. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2160,
  1966. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2160},
  1967. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2200,
  1968. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2200},
  1969. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2230,
  1970. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2230},
  1971. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2360,
  1972. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2360},
  1973. {PCI_VENDOR_ID_NEOMAGIC, PCI_CHIP_NM2380,
  1974. PCI_ANY_ID, PCI_ANY_ID, 0, 0, FB_ACCEL_NEOMAGIC_NM2380},
  1975. {0, 0, 0, 0, 0, 0, 0}
  1976. };
  1977. MODULE_DEVICE_TABLE(pci, neofb_devices);
  1978. static struct pci_driver neofb_driver = {
  1979. .name = "neofb",
  1980. .id_table = neofb_devices,
  1981. .probe = neofb_probe,
  1982. .remove = __devexit_p(neofb_remove)
  1983. };
  1984. /* ************************* init in-kernel code ************************** */
  1985. #ifndef MODULE
  1986. static int __init neofb_setup(char *options)
  1987. {
  1988. char *this_opt;
  1989. DBG("neofb_setup");
  1990. if (!options || !*options)
  1991. return 0;
  1992. while ((this_opt = strsep(&options, ",")) != NULL) {
  1993. if (!*this_opt)
  1994. continue;
  1995. if (!strncmp(this_opt, "internal", 8))
  1996. internal = 1;
  1997. else if (!strncmp(this_opt, "external", 8))
  1998. external = 1;
  1999. else if (!strncmp(this_opt, "nostretch", 9))
  2000. nostretch = 1;
  2001. else if (!strncmp(this_opt, "nopciburst", 10))
  2002. nopciburst = 1;
  2003. else if (!strncmp(this_opt, "libretto", 8))
  2004. libretto = 1;
  2005. else
  2006. mode_option = this_opt;
  2007. }
  2008. return 0;
  2009. }
  2010. #endif /* MODULE */
  2011. static int __init neofb_init(void)
  2012. {
  2013. #ifndef MODULE
  2014. char *option = NULL;
  2015. if (fb_get_options("neofb", &option))
  2016. return -ENODEV;
  2017. neofb_setup(option);
  2018. #endif
  2019. return pci_register_driver(&neofb_driver);
  2020. }
  2021. module_init(neofb_init);
  2022. #ifdef MODULE
  2023. static void __exit neofb_exit(void)
  2024. {
  2025. pci_unregister_driver(&neofb_driver);
  2026. }
  2027. module_exit(neofb_exit);
  2028. #endif /* MODULE */