controlfb.c 27 KB

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  1. /*
  2. * controlfb.c -- frame buffer device for the PowerMac 'control' display
  3. *
  4. * Created 12 July 1998 by Dan Jacobowitz <dan@debian.org>
  5. * Copyright (C) 1998 Dan Jacobowitz
  6. * Copyright (C) 2001 Takashi Oe
  7. *
  8. * Mmap code by Michel Lanners <mlan@cpu.lu>
  9. *
  10. * Frame buffer structure from:
  11. * drivers/video/chipsfb.c -- frame buffer device for
  12. * Chips & Technologies 65550 chip.
  13. *
  14. * Copyright (C) 1998 Paul Mackerras
  15. *
  16. * This file is derived from the Powermac "chips" driver:
  17. * Copyright (C) 1997 Fabio Riccardi.
  18. * And from the frame buffer device for Open Firmware-initialized devices:
  19. * Copyright (C) 1997 Geert Uytterhoeven.
  20. *
  21. * Hardware information from:
  22. * control.c: Console support for PowerMac "control" display adaptor.
  23. * Copyright (C) 1996 Paul Mackerras
  24. *
  25. * Updated to 2.5 framebuffer API by Ben Herrenschmidt
  26. * <benh@kernel.crashing.org>, Paul Mackerras <paulus@samba.org>,
  27. * and James Simmons <jsimmons@infradead.org>.
  28. *
  29. * This file is subject to the terms and conditions of the GNU General Public
  30. * License. See the file COPYING in the main directory of this archive for
  31. * more details.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/kernel.h>
  35. #include <linux/errno.h>
  36. #include <linux/string.h>
  37. #include <linux/mm.h>
  38. #include <linux/slab.h>
  39. #include <linux/vmalloc.h>
  40. #include <linux/delay.h>
  41. #include <linux/interrupt.h>
  42. #include <linux/fb.h>
  43. #include <linux/init.h>
  44. #include <linux/pci.h>
  45. #include <linux/nvram.h>
  46. #include <linux/adb.h>
  47. #include <linux/cuda.h>
  48. #include <asm/io.h>
  49. #include <asm/prom.h>
  50. #include <asm/pgtable.h>
  51. #include <asm/btext.h>
  52. #include "macmodes.h"
  53. #include "controlfb.h"
  54. struct fb_par_control {
  55. int vmode, cmode;
  56. int xres, yres;
  57. int vxres, vyres;
  58. int xoffset, yoffset;
  59. int pitch;
  60. struct control_regvals regvals;
  61. unsigned long sync;
  62. unsigned char ctrl;
  63. };
  64. #define DIRTY(z) ((x)->z != (y)->z)
  65. #define DIRTY_CMAP(z) (memcmp(&((x)->z), &((y)->z), sizeof((y)->z)))
  66. static inline int PAR_EQUAL(struct fb_par_control *x, struct fb_par_control *y)
  67. {
  68. int i, results;
  69. results = 1;
  70. for (i = 0; i < 3; i++)
  71. results &= !DIRTY(regvals.clock_params[i]);
  72. if (!results)
  73. return 0;
  74. for (i = 0; i < 16; i++)
  75. results &= !DIRTY(regvals.regs[i]);
  76. if (!results)
  77. return 0;
  78. return (!DIRTY(cmode) && !DIRTY(xres) && !DIRTY(yres)
  79. && !DIRTY(vxres) && !DIRTY(vyres));
  80. }
  81. static inline int VAR_MATCH(struct fb_var_screeninfo *x, struct fb_var_screeninfo *y)
  82. {
  83. return (!DIRTY(bits_per_pixel) && !DIRTY(xres)
  84. && !DIRTY(yres) && !DIRTY(xres_virtual)
  85. && !DIRTY(yres_virtual)
  86. && !DIRTY_CMAP(red) && !DIRTY_CMAP(green) && !DIRTY_CMAP(blue));
  87. }
  88. struct fb_info_control {
  89. struct fb_info info;
  90. struct fb_par_control par;
  91. u32 pseudo_palette[17];
  92. struct cmap_regs __iomem *cmap_regs;
  93. unsigned long cmap_regs_phys;
  94. struct control_regs __iomem *control_regs;
  95. unsigned long control_regs_phys;
  96. unsigned long control_regs_size;
  97. __u8 __iomem *frame_buffer;
  98. unsigned long frame_buffer_phys;
  99. unsigned long fb_orig_base;
  100. unsigned long fb_orig_size;
  101. int control_use_bank2;
  102. unsigned long total_vram;
  103. unsigned char vram_attr;
  104. };
  105. /* control register access macro */
  106. #define CNTRL_REG(INFO,REG) (&(((INFO)->control_regs->REG).r))
  107. /******************** Prototypes for exported functions ********************/
  108. /*
  109. * struct fb_ops
  110. */
  111. static int controlfb_pan_display(struct fb_var_screeninfo *var,
  112. struct fb_info *info);
  113. static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  114. u_int transp, struct fb_info *info);
  115. static int controlfb_blank(int blank_mode, struct fb_info *info);
  116. static int controlfb_mmap(struct fb_info *info,
  117. struct vm_area_struct *vma);
  118. static int controlfb_set_par (struct fb_info *info);
  119. static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info);
  120. /******************** Prototypes for internal functions **********************/
  121. static void set_control_clock(unsigned char *params);
  122. static int init_control(struct fb_info_control *p);
  123. static void control_set_hardware(struct fb_info_control *p,
  124. struct fb_par_control *par);
  125. static int control_of_init(struct device_node *dp);
  126. static void find_vram_size(struct fb_info_control *p);
  127. static int read_control_sense(struct fb_info_control *p);
  128. static int calc_clock_params(unsigned long clk, unsigned char *param);
  129. static int control_var_to_par(struct fb_var_screeninfo *var,
  130. struct fb_par_control *par, const struct fb_info *fb_info);
  131. static inline void control_par_to_var(struct fb_par_control *par,
  132. struct fb_var_screeninfo *var);
  133. static void control_init_info(struct fb_info *info, struct fb_info_control *p);
  134. static void control_cleanup(void);
  135. /************************** Internal variables *******************************/
  136. static struct fb_info_control *control_fb;
  137. static int default_vmode __initdata = VMODE_NVRAM;
  138. static int default_cmode __initdata = CMODE_NVRAM;
  139. static struct fb_ops controlfb_ops = {
  140. .owner = THIS_MODULE,
  141. .fb_check_var = controlfb_check_var,
  142. .fb_set_par = controlfb_set_par,
  143. .fb_setcolreg = controlfb_setcolreg,
  144. .fb_pan_display = controlfb_pan_display,
  145. .fb_blank = controlfb_blank,
  146. .fb_mmap = controlfb_mmap,
  147. .fb_fillrect = cfb_fillrect,
  148. .fb_copyarea = cfb_copyarea,
  149. .fb_imageblit = cfb_imageblit,
  150. };
  151. /******************** The functions for controlfb_ops ********************/
  152. #ifdef MODULE
  153. MODULE_LICENSE("GPL");
  154. int init_module(void)
  155. {
  156. struct device_node *dp;
  157. dp = find_devices("control");
  158. if (dp != 0 && !control_of_init(dp))
  159. return 0;
  160. return -ENXIO;
  161. }
  162. void cleanup_module(void)
  163. {
  164. control_cleanup();
  165. }
  166. #endif
  167. /*
  168. * Checks a var structure
  169. */
  170. static int controlfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
  171. {
  172. struct fb_par_control par;
  173. int err;
  174. err = control_var_to_par(var, &par, info);
  175. if (err)
  176. return err;
  177. control_par_to_var(&par, var);
  178. return 0;
  179. }
  180. /*
  181. * Applies current var to display
  182. */
  183. static int controlfb_set_par (struct fb_info *info)
  184. {
  185. struct fb_info_control *p = (struct fb_info_control *) info;
  186. struct fb_par_control par;
  187. int err;
  188. if((err = control_var_to_par(&info->var, &par, info))) {
  189. printk (KERN_ERR "controlfb_set_par: error calling"
  190. " control_var_to_par: %d.\n", err);
  191. return err;
  192. }
  193. control_set_hardware(p, &par);
  194. info->fix.visual = (p->par.cmode == CMODE_8) ?
  195. FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
  196. info->fix.line_length = p->par.pitch;
  197. info->fix.xpanstep = 32 >> p->par.cmode;
  198. info->fix.ypanstep = 1;
  199. return 0;
  200. }
  201. /*
  202. * Set screen start address according to var offset values
  203. */
  204. static inline void set_screen_start(int xoffset, int yoffset,
  205. struct fb_info_control *p)
  206. {
  207. struct fb_par_control *par = &p->par;
  208. par->xoffset = xoffset;
  209. par->yoffset = yoffset;
  210. out_le32(CNTRL_REG(p,start_addr),
  211. par->yoffset * par->pitch + (par->xoffset << par->cmode));
  212. }
  213. static int controlfb_pan_display(struct fb_var_screeninfo *var,
  214. struct fb_info *info)
  215. {
  216. unsigned int xoffset, hstep;
  217. struct fb_info_control *p = (struct fb_info_control *)info;
  218. struct fb_par_control *par = &p->par;
  219. /*
  220. * make sure start addr will be 32-byte aligned
  221. */
  222. hstep = 0x1f >> par->cmode;
  223. xoffset = (var->xoffset + hstep) & ~hstep;
  224. if (xoffset+par->xres > par->vxres ||
  225. var->yoffset+par->yres > par->vyres)
  226. return -EINVAL;
  227. set_screen_start(xoffset, var->yoffset, p);
  228. return 0;
  229. }
  230. /*
  231. * Private mmap since we want to have a different caching on the framebuffer
  232. * for controlfb.
  233. * Note there's no locking in here; it's done in fb_mmap() in fbmem.c.
  234. */
  235. static int controlfb_mmap(struct fb_info *info,
  236. struct vm_area_struct *vma)
  237. {
  238. unsigned long off, start;
  239. u32 len;
  240. off = vma->vm_pgoff << PAGE_SHIFT;
  241. /* frame buffer memory */
  242. start = info->fix.smem_start;
  243. len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.smem_len);
  244. if (off >= len) {
  245. /* memory mapped io */
  246. off -= len;
  247. if (info->var.accel_flags)
  248. return -EINVAL;
  249. start = info->fix.mmio_start;
  250. len = PAGE_ALIGN((start & ~PAGE_MASK)+info->fix.mmio_len);
  251. pgprot_val(vma->vm_page_prot) |= _PAGE_NO_CACHE|_PAGE_GUARDED;
  252. } else {
  253. /* framebuffer */
  254. pgprot_val(vma->vm_page_prot) |= _PAGE_WRITETHRU;
  255. }
  256. start &= PAGE_MASK;
  257. if ((vma->vm_end - vma->vm_start + off) > len)
  258. return -EINVAL;
  259. off += start;
  260. vma->vm_pgoff = off >> PAGE_SHIFT;
  261. if (io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
  262. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  263. return -EAGAIN;
  264. return 0;
  265. }
  266. static int controlfb_blank(int blank_mode, struct fb_info *info)
  267. {
  268. struct fb_info_control *p = (struct fb_info_control *) info;
  269. unsigned ctrl;
  270. ctrl = ld_le32(CNTRL_REG(p,ctrl));
  271. if (blank_mode > 0)
  272. switch (blank_mode) {
  273. case FB_BLANK_VSYNC_SUSPEND:
  274. ctrl &= ~3;
  275. break;
  276. case FB_BLANK_HSYNC_SUSPEND:
  277. ctrl &= ~0x30;
  278. break;
  279. case FB_BLANK_POWERDOWN:
  280. ctrl &= ~0x33;
  281. /* fall through */
  282. case FB_BLANK_NORMAL:
  283. ctrl |= 0x400;
  284. break;
  285. default:
  286. break;
  287. }
  288. else {
  289. ctrl &= ~0x400;
  290. ctrl |= 0x33;
  291. }
  292. out_le32(CNTRL_REG(p,ctrl), ctrl);
  293. return 0;
  294. }
  295. static int controlfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  296. u_int transp, struct fb_info *info)
  297. {
  298. struct fb_info_control *p = (struct fb_info_control *) info;
  299. __u8 r, g, b;
  300. if (regno > 255)
  301. return 1;
  302. r = red >> 8;
  303. g = green >> 8;
  304. b = blue >> 8;
  305. out_8(&p->cmap_regs->addr, regno); /* tell clut what addr to fill */
  306. out_8(&p->cmap_regs->lut, r); /* send one color channel at */
  307. out_8(&p->cmap_regs->lut, g); /* a time... */
  308. out_8(&p->cmap_regs->lut, b);
  309. if (regno < 16) {
  310. int i;
  311. switch (p->par.cmode) {
  312. case CMODE_16:
  313. p->pseudo_palette[regno] =
  314. (regno << 10) | (regno << 5) | regno;
  315. break;
  316. case CMODE_32:
  317. i = (regno << 8) | regno;
  318. p->pseudo_palette[regno] = (i << 16) | i;
  319. break;
  320. }
  321. }
  322. return 0;
  323. }
  324. /******************** End of controlfb_ops implementation ******************/
  325. static void set_control_clock(unsigned char *params)
  326. {
  327. #ifdef CONFIG_ADB_CUDA
  328. struct adb_request req;
  329. int i;
  330. for (i = 0; i < 3; ++i) {
  331. cuda_request(&req, NULL, 5, CUDA_PACKET, CUDA_GET_SET_IIC,
  332. 0x50, i + 1, params[i]);
  333. while (!req.complete)
  334. cuda_poll();
  335. }
  336. #endif
  337. }
  338. /*
  339. * finish off the driver initialization and register
  340. */
  341. static int __init init_control(struct fb_info_control *p)
  342. {
  343. int full, sense, vmode, cmode, vyres;
  344. struct fb_var_screeninfo var;
  345. int rc;
  346. printk(KERN_INFO "controlfb: ");
  347. full = p->total_vram == 0x400000;
  348. /* Try to pick a video mode out of NVRAM if we have one. */
  349. #ifdef CONFIG_NVRAM
  350. if (default_cmode == CMODE_NVRAM){
  351. cmode = nvram_read_byte(NV_CMODE);
  352. if(cmode < CMODE_8 || cmode > CMODE_32)
  353. cmode = CMODE_8;
  354. } else
  355. #endif
  356. cmode=default_cmode;
  357. #ifdef CONFIG_NVRAM
  358. if (default_vmode == VMODE_NVRAM) {
  359. vmode = nvram_read_byte(NV_VMODE);
  360. if (vmode < 1 || vmode > VMODE_MAX ||
  361. control_mac_modes[vmode - 1].m[full] < cmode) {
  362. sense = read_control_sense(p);
  363. printk("Monitor sense value = 0x%x, ", sense);
  364. vmode = mac_map_monitor_sense(sense);
  365. if (control_mac_modes[vmode - 1].m[full] < cmode)
  366. vmode = VMODE_640_480_60;
  367. }
  368. } else
  369. #endif
  370. {
  371. vmode=default_vmode;
  372. if (control_mac_modes[vmode - 1].m[full] < cmode) {
  373. if (cmode > CMODE_8)
  374. cmode--;
  375. else
  376. vmode = VMODE_640_480_60;
  377. }
  378. }
  379. /* Initialize info structure */
  380. control_init_info(&p->info, p);
  381. /* Setup default var */
  382. if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
  383. /* This shouldn't happen! */
  384. printk("mac_vmode_to_var(%d, %d,) failed\n", vmode, cmode);
  385. try_again:
  386. vmode = VMODE_640_480_60;
  387. cmode = CMODE_8;
  388. if (mac_vmode_to_var(vmode, cmode, &var) < 0) {
  389. printk(KERN_ERR "controlfb: mac_vmode_to_var() failed\n");
  390. return -ENXIO;
  391. }
  392. printk(KERN_INFO "controlfb: ");
  393. }
  394. printk("using video mode %d and color mode %d.\n", vmode, cmode);
  395. vyres = (p->total_vram - CTRLFB_OFF) / (var.xres << cmode);
  396. if (vyres > var.yres)
  397. var.yres_virtual = vyres;
  398. /* Apply default var */
  399. var.activate = FB_ACTIVATE_NOW;
  400. rc = fb_set_var(&p->info, &var);
  401. if (rc && (vmode != VMODE_640_480_60 || cmode != CMODE_8))
  402. goto try_again;
  403. /* Register with fbdev layer */
  404. if (register_framebuffer(&p->info) < 0)
  405. return -ENXIO;
  406. printk(KERN_INFO "fb%d: control display adapter\n", p->info.node);
  407. return 0;
  408. }
  409. #define RADACAL_WRITE(a,d) \
  410. out_8(&p->cmap_regs->addr, (a)); \
  411. out_8(&p->cmap_regs->dat, (d))
  412. /* Now how about actually saying, Make it so! */
  413. /* Some things in here probably don't need to be done each time. */
  414. static void control_set_hardware(struct fb_info_control *p, struct fb_par_control *par)
  415. {
  416. struct control_regvals *r;
  417. volatile struct preg __iomem *rp;
  418. int i, cmode;
  419. if (PAR_EQUAL(&p->par, par)) {
  420. /*
  421. * check if only xoffset or yoffset differs.
  422. * this prevents flickers in typical VT switch case.
  423. */
  424. if (p->par.xoffset != par->xoffset ||
  425. p->par.yoffset != par->yoffset)
  426. set_screen_start(par->xoffset, par->yoffset, p);
  427. return;
  428. }
  429. p->par = *par;
  430. cmode = p->par.cmode;
  431. r = &par->regvals;
  432. /* Turn off display */
  433. out_le32(CNTRL_REG(p,ctrl), 0x400 | par->ctrl);
  434. set_control_clock(r->clock_params);
  435. RADACAL_WRITE(0x20, r->radacal_ctrl);
  436. RADACAL_WRITE(0x21, p->control_use_bank2 ? 0 : 1);
  437. RADACAL_WRITE(0x10, 0);
  438. RADACAL_WRITE(0x11, 0);
  439. rp = &p->control_regs->vswin;
  440. for (i = 0; i < 16; ++i, ++rp)
  441. out_le32(&rp->r, r->regs[i]);
  442. out_le32(CNTRL_REG(p,pitch), par->pitch);
  443. out_le32(CNTRL_REG(p,mode), r->mode);
  444. out_le32(CNTRL_REG(p,vram_attr), p->vram_attr);
  445. out_le32(CNTRL_REG(p,start_addr), par->yoffset * par->pitch
  446. + (par->xoffset << cmode));
  447. out_le32(CNTRL_REG(p,rfrcnt), 0x1e5);
  448. out_le32(CNTRL_REG(p,intr_ena), 0);
  449. /* Turn on display */
  450. out_le32(CNTRL_REG(p,ctrl), par->ctrl);
  451. #ifdef CONFIG_BOOTX_TEXT
  452. btext_update_display(p->frame_buffer_phys + CTRLFB_OFF,
  453. p->par.xres, p->par.yres,
  454. (cmode == CMODE_32? 32: cmode == CMODE_16? 16: 8),
  455. p->par.pitch);
  456. #endif /* CONFIG_BOOTX_TEXT */
  457. }
  458. /*
  459. * Parse user speficied options (`video=controlfb:')
  460. */
  461. static void __init control_setup(char *options)
  462. {
  463. char *this_opt;
  464. if (!options || !*options)
  465. return;
  466. while ((this_opt = strsep(&options, ",")) != NULL) {
  467. if (!strncmp(this_opt, "vmode:", 6)) {
  468. int vmode = simple_strtoul(this_opt+6, NULL, 0);
  469. if (vmode > 0 && vmode <= VMODE_MAX &&
  470. control_mac_modes[vmode - 1].m[1] >= 0)
  471. default_vmode = vmode;
  472. } else if (!strncmp(this_opt, "cmode:", 6)) {
  473. int depth = simple_strtoul(this_opt+6, NULL, 0);
  474. switch (depth) {
  475. case CMODE_8:
  476. case CMODE_16:
  477. case CMODE_32:
  478. default_cmode = depth;
  479. break;
  480. case 8:
  481. default_cmode = CMODE_8;
  482. break;
  483. case 15:
  484. case 16:
  485. default_cmode = CMODE_16;
  486. break;
  487. case 24:
  488. case 32:
  489. default_cmode = CMODE_32;
  490. break;
  491. }
  492. }
  493. }
  494. }
  495. static int __init control_init(void)
  496. {
  497. struct device_node *dp;
  498. char *option = NULL;
  499. if (fb_get_options("controlfb", &option))
  500. return -ENODEV;
  501. control_setup(option);
  502. dp = find_devices("control");
  503. if (dp != 0 && !control_of_init(dp))
  504. return 0;
  505. return -ENXIO;
  506. }
  507. module_init(control_init);
  508. /* Work out which banks of VRAM we have installed. */
  509. /* danj: I guess the card just ignores writes to nonexistant VRAM... */
  510. static void __init find_vram_size(struct fb_info_control *p)
  511. {
  512. int bank1, bank2;
  513. /*
  514. * Set VRAM in 2MB (bank 1) mode
  515. * VRAM Bank 2 will be accessible through offset 0x600000 if present
  516. * and VRAM Bank 1 will not respond at that offset even if present
  517. */
  518. out_le32(CNTRL_REG(p,vram_attr), 0x31);
  519. out_8(&p->frame_buffer[0x600000], 0xb3);
  520. out_8(&p->frame_buffer[0x600001], 0x71);
  521. asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0x600000])
  522. : "memory" );
  523. mb();
  524. asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0x600000])
  525. : "memory" );
  526. mb();
  527. bank2 = (in_8(&p->frame_buffer[0x600000]) == 0xb3)
  528. && (in_8(&p->frame_buffer[0x600001]) == 0x71);
  529. /*
  530. * Set VRAM in 2MB (bank 2) mode
  531. * VRAM Bank 1 will be accessible through offset 0x000000 if present
  532. * and VRAM Bank 2 will not respond at that offset even if present
  533. */
  534. out_le32(CNTRL_REG(p,vram_attr), 0x39);
  535. out_8(&p->frame_buffer[0], 0x5a);
  536. out_8(&p->frame_buffer[1], 0xc7);
  537. asm volatile("eieio; dcbf 0,%0" : : "r" (&p->frame_buffer[0])
  538. : "memory" );
  539. mb();
  540. asm volatile("eieio; dcbi 0,%0" : : "r" (&p->frame_buffer[0])
  541. : "memory" );
  542. mb();
  543. bank1 = (in_8(&p->frame_buffer[0]) == 0x5a)
  544. && (in_8(&p->frame_buffer[1]) == 0xc7);
  545. if (bank2) {
  546. if (!bank1) {
  547. /*
  548. * vram bank 2 only
  549. */
  550. p->control_use_bank2 = 1;
  551. p->vram_attr = 0x39;
  552. p->frame_buffer += 0x600000;
  553. p->frame_buffer_phys += 0x600000;
  554. } else {
  555. /*
  556. * 4 MB vram
  557. */
  558. p->vram_attr = 0x51;
  559. }
  560. } else {
  561. /*
  562. * vram bank 1 only
  563. */
  564. p->vram_attr = 0x31;
  565. }
  566. p->total_vram = (bank1 + bank2) * 0x200000;
  567. printk(KERN_INFO "controlfb: VRAM Total = %dMB "
  568. "(%dMB @ bank 1, %dMB @ bank 2)\n",
  569. (bank1 + bank2) << 1, bank1 << 1, bank2 << 1);
  570. }
  571. /*
  572. * find "control" and initialize
  573. */
  574. static int __init control_of_init(struct device_node *dp)
  575. {
  576. struct fb_info_control *p;
  577. struct resource fb_res, reg_res;
  578. if (control_fb) {
  579. printk(KERN_ERR "controlfb: only one control is supported\n");
  580. return -ENXIO;
  581. }
  582. if (of_pci_address_to_resource(dp, 2, &fb_res) ||
  583. of_pci_address_to_resource(dp, 1, &reg_res)) {
  584. printk(KERN_ERR "can't get 2 addresses for control\n");
  585. return -ENXIO;
  586. }
  587. p = kzalloc(sizeof(*p), GFP_KERNEL);
  588. if (p == 0)
  589. return -ENXIO;
  590. control_fb = p; /* save it for cleanups */
  591. /* Map in frame buffer and registers */
  592. p->fb_orig_base = fb_res.start;
  593. p->fb_orig_size = fb_res.end - fb_res.start + 1;
  594. /* use the big-endian aperture (??) */
  595. p->frame_buffer_phys = fb_res.start + 0x800000;
  596. p->control_regs_phys = reg_res.start;
  597. p->control_regs_size = reg_res.end - reg_res.start + 1;
  598. if (!p->fb_orig_base ||
  599. !request_mem_region(p->fb_orig_base,p->fb_orig_size,"controlfb")) {
  600. p->fb_orig_base = 0;
  601. goto error_out;
  602. }
  603. /* map at most 8MB for the frame buffer */
  604. p->frame_buffer = __ioremap(p->frame_buffer_phys, 0x800000,
  605. _PAGE_WRITETHRU);
  606. if (!p->control_regs_phys ||
  607. !request_mem_region(p->control_regs_phys, p->control_regs_size,
  608. "controlfb regs")) {
  609. p->control_regs_phys = 0;
  610. goto error_out;
  611. }
  612. p->control_regs = ioremap(p->control_regs_phys, p->control_regs_size);
  613. p->cmap_regs_phys = 0xf301b000; /* XXX not in prom? */
  614. if (!request_mem_region(p->cmap_regs_phys, 0x1000, "controlfb cmap")) {
  615. p->cmap_regs_phys = 0;
  616. goto error_out;
  617. }
  618. p->cmap_regs = ioremap(p->cmap_regs_phys, 0x1000);
  619. if (!p->cmap_regs || !p->control_regs || !p->frame_buffer)
  620. goto error_out;
  621. find_vram_size(p);
  622. if (!p->total_vram)
  623. goto error_out;
  624. if (init_control(p) < 0)
  625. goto error_out;
  626. return 0;
  627. error_out:
  628. control_cleanup();
  629. return -ENXIO;
  630. }
  631. /*
  632. * Get the monitor sense value.
  633. * Note that this can be called before calibrate_delay,
  634. * so we can't use udelay.
  635. */
  636. static int read_control_sense(struct fb_info_control *p)
  637. {
  638. int sense;
  639. out_le32(CNTRL_REG(p,mon_sense), 7); /* drive all lines high */
  640. __delay(200);
  641. out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
  642. __delay(2000);
  643. sense = (in_le32(CNTRL_REG(p,mon_sense)) & 0x1c0) << 2;
  644. /* drive each sense line low in turn and collect the other 2 */
  645. out_le32(CNTRL_REG(p,mon_sense), 033); /* drive A low */
  646. __delay(2000);
  647. sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0xc0) >> 2;
  648. out_le32(CNTRL_REG(p,mon_sense), 055); /* drive B low */
  649. __delay(2000);
  650. sense |= ((in_le32(CNTRL_REG(p,mon_sense)) & 0x100) >> 5)
  651. | ((in_le32(CNTRL_REG(p,mon_sense)) & 0x40) >> 4);
  652. out_le32(CNTRL_REG(p,mon_sense), 066); /* drive C low */
  653. __delay(2000);
  654. sense |= (in_le32(CNTRL_REG(p,mon_sense)) & 0x180) >> 7;
  655. out_le32(CNTRL_REG(p,mon_sense), 077); /* turn off drivers */
  656. return sense;
  657. }
  658. /********************** Various translation functions **********************/
  659. #define CONTROL_PIXCLOCK_BASE 256016
  660. #define CONTROL_PIXCLOCK_MIN 5000 /* ~ 200 MHz dot clock */
  661. /*
  662. * calculate the clock paramaters to be sent to CUDA according to given
  663. * pixclock in pico second.
  664. */
  665. static int calc_clock_params(unsigned long clk, unsigned char *param)
  666. {
  667. unsigned long p0, p1, p2, k, l, m, n, min;
  668. if (clk > (CONTROL_PIXCLOCK_BASE << 3))
  669. return 1;
  670. p2 = ((clk << 4) < CONTROL_PIXCLOCK_BASE)? 3: 2;
  671. l = clk << p2;
  672. p0 = 0;
  673. p1 = 0;
  674. for (k = 1, min = l; k < 32; k++) {
  675. unsigned long rem;
  676. m = CONTROL_PIXCLOCK_BASE * k;
  677. n = m / l;
  678. rem = m % l;
  679. if (n && (n < 128) && rem < min) {
  680. p0 = k;
  681. p1 = n;
  682. min = rem;
  683. }
  684. }
  685. if (!p0 || !p1)
  686. return 1;
  687. param[0] = p0;
  688. param[1] = p1;
  689. param[2] = p2;
  690. return 0;
  691. }
  692. /*
  693. * This routine takes a user-supplied var, and picks the best vmode/cmode
  694. * from it.
  695. */
  696. static int control_var_to_par(struct fb_var_screeninfo *var,
  697. struct fb_par_control *par, const struct fb_info *fb_info)
  698. {
  699. int cmode, piped_diff, hstep;
  700. unsigned hperiod, hssync, hsblank, hesync, heblank, piped, heq, hlfln,
  701. hserr, vperiod, vssync, vesync, veblank, vsblank, vswin, vewin;
  702. unsigned long pixclock;
  703. struct fb_info_control *p = (struct fb_info_control *) fb_info;
  704. struct control_regvals *r = &par->regvals;
  705. switch (var->bits_per_pixel) {
  706. case 8:
  707. par->cmode = CMODE_8;
  708. if (p->total_vram > 0x200000) {
  709. r->mode = 3;
  710. r->radacal_ctrl = 0x20;
  711. piped_diff = 13;
  712. } else {
  713. r->mode = 2;
  714. r->radacal_ctrl = 0x10;
  715. piped_diff = 9;
  716. }
  717. break;
  718. case 15:
  719. case 16:
  720. par->cmode = CMODE_16;
  721. if (p->total_vram > 0x200000) {
  722. r->mode = 2;
  723. r->radacal_ctrl = 0x24;
  724. piped_diff = 5;
  725. } else {
  726. r->mode = 1;
  727. r->radacal_ctrl = 0x14;
  728. piped_diff = 3;
  729. }
  730. break;
  731. case 32:
  732. par->cmode = CMODE_32;
  733. if (p->total_vram > 0x200000) {
  734. r->mode = 1;
  735. r->radacal_ctrl = 0x28;
  736. } else {
  737. r->mode = 0;
  738. r->radacal_ctrl = 0x18;
  739. }
  740. piped_diff = 1;
  741. break;
  742. default:
  743. return -EINVAL;
  744. }
  745. /*
  746. * adjust xres and vxres so that the corresponding memory widths are
  747. * 32-byte aligned
  748. */
  749. hstep = 31 >> par->cmode;
  750. par->xres = (var->xres + hstep) & ~hstep;
  751. par->vxres = (var->xres_virtual + hstep) & ~hstep;
  752. par->xoffset = (var->xoffset + hstep) & ~hstep;
  753. if (par->vxres < par->xres)
  754. par->vxres = par->xres;
  755. par->pitch = par->vxres << par->cmode;
  756. par->yres = var->yres;
  757. par->vyres = var->yres_virtual;
  758. par->yoffset = var->yoffset;
  759. if (par->vyres < par->yres)
  760. par->vyres = par->yres;
  761. par->sync = var->sync;
  762. if (par->pitch * par->vyres + CTRLFB_OFF > p->total_vram)
  763. return -EINVAL;
  764. if (par->xoffset + par->xres > par->vxres)
  765. par->xoffset = par->vxres - par->xres;
  766. if (par->yoffset + par->yres > par->vyres)
  767. par->yoffset = par->vyres - par->yres;
  768. pixclock = (var->pixclock < CONTROL_PIXCLOCK_MIN)? CONTROL_PIXCLOCK_MIN:
  769. var->pixclock;
  770. if (calc_clock_params(pixclock, r->clock_params))
  771. return -EINVAL;
  772. hperiod = ((var->left_margin + par->xres + var->right_margin
  773. + var->hsync_len) >> 1) - 2;
  774. hssync = hperiod + 1;
  775. hsblank = hssync - (var->right_margin >> 1);
  776. hesync = (var->hsync_len >> 1) - 1;
  777. heblank = (var->left_margin >> 1) + hesync;
  778. piped = heblank - piped_diff;
  779. heq = var->hsync_len >> 2;
  780. hlfln = (hperiod+2) >> 1;
  781. hserr = hssync-hesync;
  782. vperiod = (var->vsync_len + var->lower_margin + par->yres
  783. + var->upper_margin) << 1;
  784. vssync = vperiod - 2;
  785. vesync = (var->vsync_len << 1) - vperiod + vssync;
  786. veblank = (var->upper_margin << 1) + vesync;
  787. vsblank = vssync - (var->lower_margin << 1);
  788. vswin = (vsblank+vssync) >> 1;
  789. vewin = (vesync+veblank) >> 1;
  790. r->regs[0] = vswin;
  791. r->regs[1] = vsblank;
  792. r->regs[2] = veblank;
  793. r->regs[3] = vewin;
  794. r->regs[4] = vesync;
  795. r->regs[5] = vssync;
  796. r->regs[6] = vperiod;
  797. r->regs[7] = piped;
  798. r->regs[8] = hperiod;
  799. r->regs[9] = hsblank;
  800. r->regs[10] = heblank;
  801. r->regs[11] = hesync;
  802. r->regs[12] = hssync;
  803. r->regs[13] = heq;
  804. r->regs[14] = hlfln;
  805. r->regs[15] = hserr;
  806. if (par->xres >= 1280 && par->cmode >= CMODE_16)
  807. par->ctrl = 0x7f;
  808. else
  809. par->ctrl = 0x3b;
  810. if (mac_var_to_vmode(var, &par->vmode, &cmode))
  811. par->vmode = 0;
  812. return 0;
  813. }
  814. /*
  815. * Convert hardware data in par to an fb_var_screeninfo
  816. */
  817. static void control_par_to_var(struct fb_par_control *par, struct fb_var_screeninfo *var)
  818. {
  819. struct control_regints *rv;
  820. rv = (struct control_regints *) par->regvals.regs;
  821. memset(var, 0, sizeof(*var));
  822. var->xres = par->xres;
  823. var->yres = par->yres;
  824. var->xres_virtual = par->vxres;
  825. var->yres_virtual = par->vyres;
  826. var->xoffset = par->xoffset;
  827. var->yoffset = par->yoffset;
  828. switch(par->cmode) {
  829. default:
  830. case CMODE_8:
  831. var->bits_per_pixel = 8;
  832. var->red.length = 8;
  833. var->green.length = 8;
  834. var->blue.length = 8;
  835. break;
  836. case CMODE_16: /* RGB 555 */
  837. var->bits_per_pixel = 16;
  838. var->red.offset = 10;
  839. var->red.length = 5;
  840. var->green.offset = 5;
  841. var->green.length = 5;
  842. var->blue.length = 5;
  843. break;
  844. case CMODE_32: /* RGB 888 */
  845. var->bits_per_pixel = 32;
  846. var->red.offset = 16;
  847. var->red.length = 8;
  848. var->green.offset = 8;
  849. var->green.length = 8;
  850. var->blue.length = 8;
  851. var->transp.offset = 24;
  852. var->transp.length = 8;
  853. break;
  854. }
  855. var->height = -1;
  856. var->width = -1;
  857. var->vmode = FB_VMODE_NONINTERLACED;
  858. var->left_margin = (rv->heblank - rv->hesync) << 1;
  859. var->right_margin = (rv->hssync - rv->hsblank) << 1;
  860. var->hsync_len = (rv->hperiod + 2 - rv->hssync + rv->hesync) << 1;
  861. var->upper_margin = (rv->veblank - rv->vesync) >> 1;
  862. var->lower_margin = (rv->vssync - rv->vsblank) >> 1;
  863. var->vsync_len = (rv->vperiod - rv->vssync + rv->vesync) >> 1;
  864. var->sync = par->sync;
  865. /*
  866. * 10^12 * clock_params[0] / (3906400 * clock_params[1]
  867. * * 2^clock_params[2])
  868. * (10^12 * clock_params[0] / (3906400 * clock_params[1]))
  869. * >> clock_params[2]
  870. */
  871. /* (255990.17 * clock_params[0] / clock_params[1]) >> clock_params[2] */
  872. var->pixclock = CONTROL_PIXCLOCK_BASE * par->regvals.clock_params[0];
  873. var->pixclock /= par->regvals.clock_params[1];
  874. var->pixclock >>= par->regvals.clock_params[2];
  875. }
  876. /*
  877. * Set misc info vars for this driver
  878. */
  879. static void __init control_init_info(struct fb_info *info, struct fb_info_control *p)
  880. {
  881. /* Fill fb_info */
  882. info->par = &p->par;
  883. info->fbops = &controlfb_ops;
  884. info->pseudo_palette = p->pseudo_palette;
  885. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  886. info->screen_base = p->frame_buffer + CTRLFB_OFF;
  887. fb_alloc_cmap(&info->cmap, 256, 0);
  888. /* Fill fix common fields */
  889. strcpy(info->fix.id, "control");
  890. info->fix.mmio_start = p->control_regs_phys;
  891. info->fix.mmio_len = sizeof(struct control_regs);
  892. info->fix.type = FB_TYPE_PACKED_PIXELS;
  893. info->fix.smem_start = p->frame_buffer_phys + CTRLFB_OFF;
  894. info->fix.smem_len = p->total_vram - CTRLFB_OFF;
  895. info->fix.ywrapstep = 0;
  896. info->fix.type_aux = 0;
  897. info->fix.accel = FB_ACCEL_NONE;
  898. }
  899. static void control_cleanup(void)
  900. {
  901. struct fb_info_control *p = control_fb;
  902. if (!p)
  903. return;
  904. if (p->cmap_regs)
  905. iounmap(p->cmap_regs);
  906. if (p->control_regs)
  907. iounmap(p->control_regs);
  908. if (p->frame_buffer) {
  909. if (p->control_use_bank2)
  910. p->frame_buffer -= 0x600000;
  911. iounmap(p->frame_buffer);
  912. }
  913. if (p->cmap_regs_phys)
  914. release_mem_region(p->cmap_regs_phys, 0x1000);
  915. if (p->control_regs_phys)
  916. release_mem_region(p->control_regs_phys, p->control_regs_size);
  917. if (p->fb_orig_base)
  918. release_mem_region(p->fb_orig_base, p->fb_orig_size);
  919. kfree(p);
  920. }