cg14.c 15 KB

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  1. /* cg14.c: CGFOURTEEN frame buffer driver
  2. *
  3. * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
  4. * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
  5. * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
  6. *
  7. * Driver layout based loosely on tgafb.c, see that file for credits.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/errno.h>
  12. #include <linux/string.h>
  13. #include <linux/slab.h>
  14. #include <linux/delay.h>
  15. #include <linux/init.h>
  16. #include <linux/fb.h>
  17. #include <linux/mm.h>
  18. #include <asm/io.h>
  19. #include <asm/prom.h>
  20. #include <asm/of_device.h>
  21. #include <asm/fbio.h>
  22. #include "sbuslib.h"
  23. /*
  24. * Local functions.
  25. */
  26. static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
  27. unsigned, struct fb_info *);
  28. static int cg14_mmap(struct fb_info *, struct vm_area_struct *);
  29. static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
  30. static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);
  31. /*
  32. * Frame buffer operations
  33. */
  34. static struct fb_ops cg14_ops = {
  35. .owner = THIS_MODULE,
  36. .fb_setcolreg = cg14_setcolreg,
  37. .fb_pan_display = cg14_pan_display,
  38. .fb_fillrect = cfb_fillrect,
  39. .fb_copyarea = cfb_copyarea,
  40. .fb_imageblit = cfb_imageblit,
  41. .fb_mmap = cg14_mmap,
  42. .fb_ioctl = cg14_ioctl,
  43. #ifdef CONFIG_COMPAT
  44. .fb_compat_ioctl = sbusfb_compat_ioctl,
  45. #endif
  46. };
  47. #define CG14_MCR_INTENABLE_SHIFT 7
  48. #define CG14_MCR_INTENABLE_MASK 0x80
  49. #define CG14_MCR_VIDENABLE_SHIFT 6
  50. #define CG14_MCR_VIDENABLE_MASK 0x40
  51. #define CG14_MCR_PIXMODE_SHIFT 4
  52. #define CG14_MCR_PIXMODE_MASK 0x30
  53. #define CG14_MCR_TMR_SHIFT 2
  54. #define CG14_MCR_TMR_MASK 0x0c
  55. #define CG14_MCR_TMENABLE_SHIFT 1
  56. #define CG14_MCR_TMENABLE_MASK 0x02
  57. #define CG14_MCR_RESET_SHIFT 0
  58. #define CG14_MCR_RESET_MASK 0x01
  59. #define CG14_REV_REVISION_SHIFT 4
  60. #define CG14_REV_REVISION_MASK 0xf0
  61. #define CG14_REV_IMPL_SHIFT 0
  62. #define CG14_REV_IMPL_MASK 0x0f
  63. #define CG14_VBR_FRAMEBASE_SHIFT 12
  64. #define CG14_VBR_FRAMEBASE_MASK 0x00fff000
  65. #define CG14_VMCR1_SETUP_SHIFT 0
  66. #define CG14_VMCR1_SETUP_MASK 0x000001ff
  67. #define CG14_VMCR1_VCONFIG_SHIFT 9
  68. #define CG14_VMCR1_VCONFIG_MASK 0x00000e00
  69. #define CG14_VMCR2_REFRESH_SHIFT 0
  70. #define CG14_VMCR2_REFRESH_MASK 0x00000001
  71. #define CG14_VMCR2_TESTROWCNT_SHIFT 1
  72. #define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
  73. #define CG14_VMCR2_FBCONFIG_SHIFT 2
  74. #define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
  75. #define CG14_VCR_REFRESHREQ_SHIFT 0
  76. #define CG14_VCR_REFRESHREQ_MASK 0x000003ff
  77. #define CG14_VCR1_REFRESHENA_SHIFT 10
  78. #define CG14_VCR1_REFRESHENA_MASK 0x00000400
  79. #define CG14_VCA_CAD_SHIFT 0
  80. #define CG14_VCA_CAD_MASK 0x000003ff
  81. #define CG14_VCA_VERS_SHIFT 10
  82. #define CG14_VCA_VERS_MASK 0x00000c00
  83. #define CG14_VCA_RAMSPEED_SHIFT 12
  84. #define CG14_VCA_RAMSPEED_MASK 0x00001000
  85. #define CG14_VCA_8MB_SHIFT 13
  86. #define CG14_VCA_8MB_MASK 0x00002000
  87. #define CG14_MCR_PIXMODE_8 0
  88. #define CG14_MCR_PIXMODE_16 2
  89. #define CG14_MCR_PIXMODE_32 3
  90. struct cg14_regs{
  91. u8 mcr; /* Master Control Reg */
  92. u8 ppr; /* Packed Pixel Reg */
  93. u8 tms[2]; /* Test Mode Status Regs */
  94. u8 msr; /* Master Status Reg */
  95. u8 fsr; /* Fault Status Reg */
  96. u8 rev; /* Revision & Impl */
  97. u8 ccr; /* Clock Control Reg */
  98. u32 tmr; /* Test Mode Read Back */
  99. u8 mod; /* Monitor Operation Data Reg */
  100. u8 acr; /* Aux Control */
  101. u8 xxx0[6];
  102. u16 hct; /* Hor Counter */
  103. u16 vct; /* Vert Counter */
  104. u16 hbs; /* Hor Blank Start */
  105. u16 hbc; /* Hor Blank Clear */
  106. u16 hss; /* Hor Sync Start */
  107. u16 hsc; /* Hor Sync Clear */
  108. u16 csc; /* Composite Sync Clear */
  109. u16 vbs; /* Vert Blank Start */
  110. u16 vbc; /* Vert Blank Clear */
  111. u16 vss; /* Vert Sync Start */
  112. u16 vsc; /* Vert Sync Clear */
  113. u16 xcs;
  114. u16 xcc;
  115. u16 fsa; /* Fault Status Address */
  116. u16 adr; /* Address Registers */
  117. u8 xxx1[0xce];
  118. u8 pcg[0x100]; /* Pixel Clock Generator */
  119. u32 vbr; /* Frame Base Row */
  120. u32 vmcr; /* VBC Master Control */
  121. u32 vcr; /* VBC refresh */
  122. u32 vca; /* VBC Config */
  123. };
  124. #define CG14_CCR_ENABLE 0x04
  125. #define CG14_CCR_SELECT 0x02 /* HW/Full screen */
  126. struct cg14_cursor {
  127. u32 cpl0[32]; /* Enable plane 0 */
  128. u32 cpl1[32]; /* Color selection plane */
  129. u8 ccr; /* Cursor Control Reg */
  130. u8 xxx0[3];
  131. u16 cursx; /* Cursor x,y position */
  132. u16 cursy; /* Cursor x,y position */
  133. u32 color0;
  134. u32 color1;
  135. u32 xxx1[0x1bc];
  136. u32 cpl0i[32]; /* Enable plane 0 autoinc */
  137. u32 cpl1i[32]; /* Color selection autoinc */
  138. };
  139. struct cg14_dac {
  140. u8 addr; /* Address Register */
  141. u8 xxx0[255];
  142. u8 glut; /* Gamma table */
  143. u8 xxx1[255];
  144. u8 select; /* Register Select */
  145. u8 xxx2[255];
  146. u8 mode; /* Mode Register */
  147. };
  148. struct cg14_xlut{
  149. u8 x_xlut [256];
  150. u8 x_xlutd [256];
  151. u8 xxx0[0x600];
  152. u8 x_xlut_inc [256];
  153. u8 x_xlutd_inc [256];
  154. };
  155. /* Color look up table (clut) */
  156. /* Each one of these arrays hold the color lookup table (for 256
  157. * colors) for each MDI page (I assume then there should be 4 MDI
  158. * pages, I still wonder what they are. I have seen NeXTStep split
  159. * the screen in four parts, while operating in 24 bits mode. Each
  160. * integer holds 4 values: alpha value (transparency channel, thanks
  161. * go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue
  162. *
  163. * I currently use the clut instead of the Xlut
  164. */
  165. struct cg14_clut {
  166. u32 c_clut [256];
  167. u32 c_clutd [256]; /* i wonder what the 'd' is for */
  168. u32 c_clut_inc [256];
  169. u32 c_clutd_inc [256];
  170. };
  171. #define CG14_MMAP_ENTRIES 16
  172. struct cg14_par {
  173. spinlock_t lock;
  174. struct cg14_regs __iomem *regs;
  175. struct cg14_clut __iomem *clut;
  176. struct cg14_cursor __iomem *cursor;
  177. u32 flags;
  178. #define CG14_FLAG_BLANKED 0x00000001
  179. unsigned long physbase;
  180. unsigned long iospace;
  181. unsigned long fbsize;
  182. struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
  183. int mode;
  184. int ramsize;
  185. };
  186. static void __cg14_reset(struct cg14_par *par)
  187. {
  188. struct cg14_regs __iomem *regs = par->regs;
  189. u8 val;
  190. val = sbus_readb(&regs->mcr);
  191. val &= ~(CG14_MCR_PIXMODE_MASK);
  192. sbus_writeb(val, &regs->mcr);
  193. }
  194. static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  195. {
  196. struct cg14_par *par = (struct cg14_par *) info->par;
  197. unsigned long flags;
  198. /* We just use this to catch switches out of
  199. * graphics mode.
  200. */
  201. spin_lock_irqsave(&par->lock, flags);
  202. __cg14_reset(par);
  203. spin_unlock_irqrestore(&par->lock, flags);
  204. if (var->xoffset || var->yoffset || var->vmode)
  205. return -EINVAL;
  206. return 0;
  207. }
  208. /**
  209. * cg14_setcolreg - Optional function. Sets a color register.
  210. * @regno: boolean, 0 copy local, 1 get_user() function
  211. * @red: frame buffer colormap structure
  212. * @green: The green value which can be up to 16 bits wide
  213. * @blue: The blue value which can be up to 16 bits wide.
  214. * @transp: If supported the alpha value which can be up to 16 bits wide.
  215. * @info: frame buffer info structure
  216. */
  217. static int cg14_setcolreg(unsigned regno,
  218. unsigned red, unsigned green, unsigned blue,
  219. unsigned transp, struct fb_info *info)
  220. {
  221. struct cg14_par *par = (struct cg14_par *) info->par;
  222. struct cg14_clut __iomem *clut = par->clut;
  223. unsigned long flags;
  224. u32 val;
  225. if (regno >= 256)
  226. return 1;
  227. red >>= 8;
  228. green >>= 8;
  229. blue >>= 8;
  230. val = (red | (green << 8) | (blue << 16));
  231. spin_lock_irqsave(&par->lock, flags);
  232. sbus_writel(val, &clut->c_clut[regno]);
  233. spin_unlock_irqrestore(&par->lock, flags);
  234. return 0;
  235. }
  236. static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma)
  237. {
  238. struct cg14_par *par = (struct cg14_par *) info->par;
  239. return sbusfb_mmap_helper(par->mmap_map,
  240. par->physbase, par->fbsize,
  241. par->iospace, vma);
  242. }
  243. static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  244. {
  245. struct cg14_par *par = (struct cg14_par *) info->par;
  246. struct cg14_regs __iomem *regs = par->regs;
  247. struct mdi_cfginfo kmdi, __user *mdii;
  248. unsigned long flags;
  249. int cur_mode, mode, ret = 0;
  250. switch (cmd) {
  251. case MDI_RESET:
  252. spin_lock_irqsave(&par->lock, flags);
  253. __cg14_reset(par);
  254. spin_unlock_irqrestore(&par->lock, flags);
  255. break;
  256. case MDI_GET_CFGINFO:
  257. memset(&kmdi, 0, sizeof(kmdi));
  258. spin_lock_irqsave(&par->lock, flags);
  259. kmdi.mdi_type = FBTYPE_MDICOLOR;
  260. kmdi.mdi_height = info->var.yres;
  261. kmdi.mdi_width = info->var.xres;
  262. kmdi.mdi_mode = par->mode;
  263. kmdi.mdi_pixfreq = 72; /* FIXME */
  264. kmdi.mdi_size = par->ramsize;
  265. spin_unlock_irqrestore(&par->lock, flags);
  266. mdii = (struct mdi_cfginfo __user *) arg;
  267. if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
  268. ret = -EFAULT;
  269. break;
  270. case MDI_SET_PIXELMODE:
  271. if (get_user(mode, (int __user *) arg)) {
  272. ret = -EFAULT;
  273. break;
  274. }
  275. spin_lock_irqsave(&par->lock, flags);
  276. cur_mode = sbus_readb(&regs->mcr);
  277. cur_mode &= ~CG14_MCR_PIXMODE_MASK;
  278. switch(mode) {
  279. case MDI_32_PIX:
  280. cur_mode |= (CG14_MCR_PIXMODE_32 <<
  281. CG14_MCR_PIXMODE_SHIFT);
  282. break;
  283. case MDI_16_PIX:
  284. cur_mode |= (CG14_MCR_PIXMODE_16 <<
  285. CG14_MCR_PIXMODE_SHIFT);
  286. break;
  287. case MDI_8_PIX:
  288. break;
  289. default:
  290. ret = -ENOSYS;
  291. break;
  292. };
  293. if (!ret) {
  294. sbus_writeb(cur_mode, &regs->mcr);
  295. par->mode = mode;
  296. }
  297. spin_unlock_irqrestore(&par->lock, flags);
  298. break;
  299. default:
  300. ret = sbusfb_ioctl_helper(cmd, arg, info,
  301. FBTYPE_MDICOLOR, 8, par->fbsize);
  302. break;
  303. };
  304. return ret;
  305. }
  306. /*
  307. * Initialisation
  308. */
  309. static void __devinit cg14_init_fix(struct fb_info *info, int linebytes,
  310. struct device_node *dp)
  311. {
  312. const char *name = dp->name;
  313. strlcpy(info->fix.id, name, sizeof(info->fix.id));
  314. info->fix.type = FB_TYPE_PACKED_PIXELS;
  315. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  316. info->fix.line_length = linebytes;
  317. info->fix.accel = FB_ACCEL_SUN_CG14;
  318. }
  319. static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] __devinitdata = {
  320. {
  321. .voff = CG14_REGS,
  322. .poff = 0x80000000,
  323. .size = 0x1000
  324. },
  325. {
  326. .voff = CG14_XLUT,
  327. .poff = 0x80003000,
  328. .size = 0x1000
  329. },
  330. {
  331. .voff = CG14_CLUT1,
  332. .poff = 0x80004000,
  333. .size = 0x1000
  334. },
  335. {
  336. .voff = CG14_CLUT2,
  337. .poff = 0x80005000,
  338. .size = 0x1000
  339. },
  340. {
  341. .voff = CG14_CLUT3,
  342. .poff = 0x80006000,
  343. .size = 0x1000
  344. },
  345. {
  346. .voff = CG3_MMAP_OFFSET - 0x7000,
  347. .poff = 0x80000000,
  348. .size = 0x7000
  349. },
  350. {
  351. .voff = CG3_MMAP_OFFSET,
  352. .poff = 0x00000000,
  353. .size = SBUS_MMAP_FBSIZE(1)
  354. },
  355. {
  356. .voff = MDI_CURSOR_MAP,
  357. .poff = 0x80001000,
  358. .size = 0x1000
  359. },
  360. {
  361. .voff = MDI_CHUNKY_BGR_MAP,
  362. .poff = 0x01000000,
  363. .size = 0x400000
  364. },
  365. {
  366. .voff = MDI_PLANAR_X16_MAP,
  367. .poff = 0x02000000,
  368. .size = 0x200000
  369. },
  370. {
  371. .voff = MDI_PLANAR_C16_MAP,
  372. .poff = 0x02800000,
  373. .size = 0x200000
  374. },
  375. {
  376. .voff = MDI_PLANAR_X32_MAP,
  377. .poff = 0x03000000,
  378. .size = 0x100000
  379. },
  380. {
  381. .voff = MDI_PLANAR_B32_MAP,
  382. .poff = 0x03400000,
  383. .size = 0x100000
  384. },
  385. {
  386. .voff = MDI_PLANAR_G32_MAP,
  387. .poff = 0x03800000,
  388. .size = 0x100000
  389. },
  390. {
  391. .voff = MDI_PLANAR_R32_MAP,
  392. .poff = 0x03c00000,
  393. .size = 0x100000
  394. },
  395. { .size = 0 }
  396. };
  397. struct all_info {
  398. struct fb_info info;
  399. struct cg14_par par;
  400. };
  401. static void cg14_unmap_regs(struct of_device *op, struct all_info *all)
  402. {
  403. if (all->par.regs)
  404. of_iounmap(&op->resource[0],
  405. all->par.regs, sizeof(struct cg14_regs));
  406. if (all->par.clut)
  407. of_iounmap(&op->resource[0],
  408. all->par.clut, sizeof(struct cg14_clut));
  409. if (all->par.cursor)
  410. of_iounmap(&op->resource[0],
  411. all->par.cursor, sizeof(struct cg14_cursor));
  412. if (all->info.screen_base)
  413. of_iounmap(&op->resource[1],
  414. all->info.screen_base, all->par.fbsize);
  415. }
  416. static int __devinit cg14_init_one(struct of_device *op)
  417. {
  418. struct device_node *dp = op->node;
  419. struct all_info *all;
  420. int is_8mb, linebytes, i, err;
  421. all = kzalloc(sizeof(*all), GFP_KERNEL);
  422. if (!all)
  423. return -ENOMEM;
  424. spin_lock_init(&all->par.lock);
  425. sbusfb_fill_var(&all->info.var, dp->node, 8);
  426. all->info.var.red.length = 8;
  427. all->info.var.green.length = 8;
  428. all->info.var.blue.length = 8;
  429. linebytes = of_getintprop_default(dp, "linebytes",
  430. all->info.var.xres);
  431. all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
  432. if (!strcmp(dp->parent->name, "sbus") ||
  433. !strcmp(dp->parent->name, "sbi")) {
  434. all->par.physbase = op->resource[0].start;
  435. all->par.iospace = op->resource[0].flags & IORESOURCE_BITS;
  436. } else {
  437. all->par.physbase = op->resource[1].start;
  438. all->par.iospace = op->resource[0].flags & IORESOURCE_BITS;
  439. }
  440. all->par.regs = of_ioremap(&op->resource[0], 0,
  441. sizeof(struct cg14_regs), "cg14 regs");
  442. all->par.clut = of_ioremap(&op->resource[0], CG14_CLUT1,
  443. sizeof(struct cg14_clut), "cg14 clut");
  444. all->par.cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
  445. sizeof(struct cg14_cursor), "cg14 cursor");
  446. all->info.screen_base = of_ioremap(&op->resource[1], 0,
  447. all->par.fbsize, "cg14 ram");
  448. if (!all->par.regs || !all->par.clut || !all->par.cursor ||
  449. !all->info.screen_base)
  450. cg14_unmap_regs(op, all);
  451. is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) ==
  452. (8 * 1024 * 1024));
  453. BUILD_BUG_ON(sizeof(all->par.mmap_map) != sizeof(__cg14_mmap_map));
  454. memcpy(&all->par.mmap_map, &__cg14_mmap_map,
  455. sizeof(all->par.mmap_map));
  456. for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
  457. struct sbus_mmap_map *map = &all->par.mmap_map[i];
  458. if (!map->size)
  459. break;
  460. if (map->poff & 0x80000000)
  461. map->poff = (map->poff & 0x7fffffff) +
  462. (op->resource[0].start -
  463. op->resource[1].start);
  464. if (is_8mb &&
  465. map->size >= 0x100000 &&
  466. map->size <= 0x400000)
  467. map->size *= 2;
  468. }
  469. all->par.mode = MDI_8_PIX;
  470. all->par.ramsize = (is_8mb ? 0x800000 : 0x400000);
  471. all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  472. all->info.fbops = &cg14_ops;
  473. all->info.par = &all->par;
  474. __cg14_reset(&all->par);
  475. if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
  476. cg14_unmap_regs(op, all);
  477. kfree(all);
  478. return -ENOMEM;
  479. }
  480. fb_set_cmap(&all->info.cmap, &all->info);
  481. cg14_init_fix(&all->info, linebytes, dp);
  482. err = register_framebuffer(&all->info);
  483. if (err < 0) {
  484. fb_dealloc_cmap(&all->info.cmap);
  485. cg14_unmap_regs(op, all);
  486. kfree(all);
  487. return err;
  488. }
  489. dev_set_drvdata(&op->dev, all);
  490. printk("%s: cgfourteen at %lx:%lx, %dMB\n",
  491. dp->full_name,
  492. all->par.iospace, all->par.physbase,
  493. all->par.ramsize >> 20);
  494. return 0;
  495. }
  496. static int __devinit cg14_probe(struct of_device *dev, const struct of_device_id *match)
  497. {
  498. struct of_device *op = to_of_device(&dev->dev);
  499. return cg14_init_one(op);
  500. }
  501. static int __devexit cg14_remove(struct of_device *op)
  502. {
  503. struct all_info *all = dev_get_drvdata(&op->dev);
  504. unregister_framebuffer(&all->info);
  505. fb_dealloc_cmap(&all->info.cmap);
  506. cg14_unmap_regs(op, all);
  507. kfree(all);
  508. dev_set_drvdata(&op->dev, NULL);
  509. return 0;
  510. }
  511. static struct of_device_id cg14_match[] = {
  512. {
  513. .name = "cgfourteen",
  514. },
  515. {},
  516. };
  517. MODULE_DEVICE_TABLE(of, cg14_match);
  518. static struct of_platform_driver cg14_driver = {
  519. .name = "cg14",
  520. .match_table = cg14_match,
  521. .probe = cg14_probe,
  522. .remove = __devexit_p(cg14_remove),
  523. };
  524. int __init cg14_init(void)
  525. {
  526. if (fb_get_options("cg14fb", NULL))
  527. return -ENODEV;
  528. return of_register_driver(&cg14_driver, &of_bus_type);
  529. }
  530. void __exit cg14_exit(void)
  531. {
  532. of_unregister_driver(&cg14_driver);
  533. }
  534. module_init(cg14_init);
  535. module_exit(cg14_exit);
  536. MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
  537. MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
  538. MODULE_VERSION("2.0");
  539. MODULE_LICENSE("GPL");