au1100fb.h 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381
  1. /*
  2. * BRIEF MODULE DESCRIPTION
  3. * Hardware definitions for the Au1100 LCD controller
  4. *
  5. * Copyright 2002 MontaVista Software
  6. * Copyright 2002 Alchemy Semiconductor
  7. * Author: Alchemy Semiconductor, MontaVista Software
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  15. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  16. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  17. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  20. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24. *
  25. * You should have received a copy of the GNU General Public License along
  26. * with this program; if not, write to the Free Software Foundation, Inc.,
  27. * 675 Mass Ave, Cambridge, MA 02139, USA.
  28. */
  29. #ifndef _AU1100LCD_H
  30. #define _AU1100LCD_H
  31. #include <asm/mach-au1x00/au1000.h>
  32. #define print_err(f, arg...) printk(KERN_ERR DRIVER_NAME ": " f "\n", ## arg)
  33. #define print_warn(f, arg...) printk(KERN_WARNING DRIVER_NAME ": " f "\n", ## arg)
  34. #define print_info(f, arg...) printk(KERN_INFO DRIVER_NAME ": " f "\n", ## arg)
  35. #if DEBUG
  36. #define print_dbg(f, arg...) printk(__FILE__ ": " f "\n", ## arg)
  37. #else
  38. #define print_dbg(f, arg...) do {} while (0)
  39. #endif
  40. #if defined(__BIG_ENDIAN)
  41. #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_11
  42. #else
  43. #define LCD_CONTROL_DEFAULT_PO LCD_CONTROL_PO_00
  44. #endif
  45. #define LCD_CONTROL_DEFAULT_SBPPF LCD_CONTROL_SBPPF_565
  46. /********************************************************************/
  47. /* LCD controller restrictions */
  48. #define AU1100_LCD_MAX_XRES 800
  49. #define AU1100_LCD_MAX_YRES 600
  50. #define AU1100_LCD_MAX_BPP 16
  51. #define AU1100_LCD_MAX_CLK 48000000
  52. #define AU1100_LCD_NBR_PALETTE_ENTRIES 256
  53. /* Default number of visible screen buffer to allocate */
  54. #define AU1100FB_NBR_VIDEO_BUFFERS 4
  55. /********************************************************************/
  56. struct au1100fb_panel
  57. {
  58. const char name[25]; /* Full name <vendor>_<model> */
  59. u32 control_base; /* Mode-independent control values */
  60. u32 clkcontrol_base; /* Panel pixclock preferences */
  61. u32 horztiming;
  62. u32 verttiming;
  63. u32 xres; /* Maximum horizontal resolution */
  64. u32 yres; /* Maximum vertical resolution */
  65. u32 bpp; /* Maximum depth supported */
  66. };
  67. struct au1100fb_regs
  68. {
  69. u32 lcd_control;
  70. u32 lcd_intstatus;
  71. u32 lcd_intenable;
  72. u32 lcd_horztiming;
  73. u32 lcd_verttiming;
  74. u32 lcd_clkcontrol;
  75. u32 lcd_dmaaddr0;
  76. u32 lcd_dmaaddr1;
  77. u32 lcd_words;
  78. u32 lcd_pwmdiv;
  79. u32 lcd_pwmhi;
  80. u32 reserved[(0x0400-0x002C)/4];
  81. u32 lcd_pallettebase[256];
  82. };
  83. struct au1100fb_device {
  84. struct fb_info info; /* FB driver info record */
  85. struct au1100fb_panel *panel; /* Panel connected to this device */
  86. struct au1100fb_regs* regs; /* Registers memory map */
  87. size_t regs_len;
  88. unsigned int regs_phys;
  89. unsigned char* fb_mem; /* FrameBuffer memory map */
  90. size_t fb_len;
  91. dma_addr_t fb_phys;
  92. };
  93. /********************************************************************/
  94. #define LCD_CONTROL (AU1100_LCD_BASE + 0x0)
  95. #define LCD_CONTROL_SBB_BIT 21
  96. #define LCD_CONTROL_SBB_MASK (0x3 << LCD_CONTROL_SBB_BIT)
  97. #define LCD_CONTROL_SBB_1 (0 << LCD_CONTROL_SBB_BIT)
  98. #define LCD_CONTROL_SBB_2 (1 << LCD_CONTROL_SBB_BIT)
  99. #define LCD_CONTROL_SBB_3 (2 << LCD_CONTROL_SBB_BIT)
  100. #define LCD_CONTROL_SBB_4 (3 << LCD_CONTROL_SBB_BIT)
  101. #define LCD_CONTROL_SBPPF_BIT 18
  102. #define LCD_CONTROL_SBPPF_MASK (0x7 << LCD_CONTROL_SBPPF_BIT)
  103. #define LCD_CONTROL_SBPPF_655 (0 << LCD_CONTROL_SBPPF_BIT)
  104. #define LCD_CONTROL_SBPPF_565 (1 << LCD_CONTROL_SBPPF_BIT)
  105. #define LCD_CONTROL_SBPPF_556 (2 << LCD_CONTROL_SBPPF_BIT)
  106. #define LCD_CONTROL_SBPPF_1555 (3 << LCD_CONTROL_SBPPF_BIT)
  107. #define LCD_CONTROL_SBPPF_5551 (4 << LCD_CONTROL_SBPPF_BIT)
  108. #define LCD_CONTROL_WP (1<<17)
  109. #define LCD_CONTROL_WD (1<<16)
  110. #define LCD_CONTROL_C (1<<15)
  111. #define LCD_CONTROL_SM_BIT 13
  112. #define LCD_CONTROL_SM_MASK (0x3 << LCD_CONTROL_SM_BIT)
  113. #define LCD_CONTROL_SM_0 (0 << LCD_CONTROL_SM_BIT)
  114. #define LCD_CONTROL_SM_90 (1 << LCD_CONTROL_SM_BIT)
  115. #define LCD_CONTROL_SM_180 (2 << LCD_CONTROL_SM_BIT)
  116. #define LCD_CONTROL_SM_270 (3 << LCD_CONTROL_SM_BIT)
  117. #define LCD_CONTROL_DB (1<<12)
  118. #define LCD_CONTROL_CCO (1<<11)
  119. #define LCD_CONTROL_DP (1<<10)
  120. #define LCD_CONTROL_PO_BIT 8
  121. #define LCD_CONTROL_PO_MASK (0x3 << LCD_CONTROL_PO_BIT)
  122. #define LCD_CONTROL_PO_00 (0 << LCD_CONTROL_PO_BIT)
  123. #define LCD_CONTROL_PO_01 (1 << LCD_CONTROL_PO_BIT)
  124. #define LCD_CONTROL_PO_10 (2 << LCD_CONTROL_PO_BIT)
  125. #define LCD_CONTROL_PO_11 (3 << LCD_CONTROL_PO_BIT)
  126. #define LCD_CONTROL_MPI (1<<7)
  127. #define LCD_CONTROL_PT (1<<6)
  128. #define LCD_CONTROL_PC (1<<5)
  129. #define LCD_CONTROL_BPP_BIT 1
  130. #define LCD_CONTROL_BPP_MASK (0x7 << LCD_CONTROL_BPP_BIT)
  131. #define LCD_CONTROL_BPP_1 (0 << LCD_CONTROL_BPP_BIT)
  132. #define LCD_CONTROL_BPP_2 (1 << LCD_CONTROL_BPP_BIT)
  133. #define LCD_CONTROL_BPP_4 (2 << LCD_CONTROL_BPP_BIT)
  134. #define LCD_CONTROL_BPP_8 (3 << LCD_CONTROL_BPP_BIT)
  135. #define LCD_CONTROL_BPP_12 (4 << LCD_CONTROL_BPP_BIT)
  136. #define LCD_CONTROL_BPP_16 (5 << LCD_CONTROL_BPP_BIT)
  137. #define LCD_CONTROL_GO (1<<0)
  138. #define LCD_INTSTATUS (AU1100_LCD_BASE + 0x4)
  139. #define LCD_INTENABLE (AU1100_LCD_BASE + 0x8)
  140. #define LCD_INT_SD (1<<7)
  141. #define LCD_INT_OF (1<<6)
  142. #define LCD_INT_UF (1<<5)
  143. #define LCD_INT_SA (1<<3)
  144. #define LCD_INT_SS (1<<2)
  145. #define LCD_INT_S1 (1<<1)
  146. #define LCD_INT_S0 (1<<0)
  147. #define LCD_HORZTIMING (AU1100_LCD_BASE + 0xC)
  148. #define LCD_HORZTIMING_HN2_BIT 24
  149. #define LCD_HORZTIMING_HN2_MASK (0xFF << LCD_HORZTIMING_HN2_BIT)
  150. #define LCD_HORZTIMING_HN2_N(N) ((((N)-1) << LCD_HORZTIMING_HN2_BIT) & LCD_HORZTIMING_HN2_MASK)
  151. #define LCD_HORZTIMING_HN1_BIT 16
  152. #define LCD_HORZTIMING_HN1_MASK (0xFF << LCD_HORZTIMING_HN1_BIT)
  153. #define LCD_HORZTIMING_HN1_N(N) ((((N)-1) << LCD_HORZTIMING_HN1_BIT) & LCD_HORZTIMING_HN1_MASK)
  154. #define LCD_HORZTIMING_HPW_BIT 10
  155. #define LCD_HORZTIMING_HPW_MASK (0x3F << LCD_HORZTIMING_HPW_BIT)
  156. #define LCD_HORZTIMING_HPW_N(N) ((((N)-1) << LCD_HORZTIMING_HPW_BIT) & LCD_HORZTIMING_HPW_MASK)
  157. #define LCD_HORZTIMING_PPL_BIT 0
  158. #define LCD_HORZTIMING_PPL_MASK (0x3FF << LCD_HORZTIMING_PPL_BIT)
  159. #define LCD_HORZTIMING_PPL_N(N) ((((N)-1) << LCD_HORZTIMING_PPL_BIT) & LCD_HORZTIMING_PPL_MASK)
  160. #define LCD_VERTTIMING (AU1100_LCD_BASE + 0x10)
  161. #define LCD_VERTTIMING_VN2_BIT 24
  162. #define LCD_VERTTIMING_VN2_MASK (0xFF << LCD_VERTTIMING_VN2_BIT)
  163. #define LCD_VERTTIMING_VN2_N(N) ((((N)-1) << LCD_VERTTIMING_VN2_BIT) & LCD_VERTTIMING_VN2_MASK)
  164. #define LCD_VERTTIMING_VN1_BIT 16
  165. #define LCD_VERTTIMING_VN1_MASK (0xFF << LCD_VERTTIMING_VN1_BIT)
  166. #define LCD_VERTTIMING_VN1_N(N) ((((N)-1) << LCD_VERTTIMING_VN1_BIT) & LCD_VERTTIMING_VN1_MASK)
  167. #define LCD_VERTTIMING_VPW_BIT 10
  168. #define LCD_VERTTIMING_VPW_MASK (0x3F << LCD_VERTTIMING_VPW_BIT)
  169. #define LCD_VERTTIMING_VPW_N(N) ((((N)-1) << LCD_VERTTIMING_VPW_BIT) & LCD_VERTTIMING_VPW_MASK)
  170. #define LCD_VERTTIMING_LPP_BIT 0
  171. #define LCD_VERTTIMING_LPP_MASK (0x3FF << LCD_VERTTIMING_LPP_BIT)
  172. #define LCD_VERTTIMING_LPP_N(N) ((((N)-1) << LCD_VERTTIMING_LPP_BIT) & LCD_VERTTIMING_LPP_MASK)
  173. #define LCD_CLKCONTROL (AU1100_LCD_BASE + 0x14)
  174. #define LCD_CLKCONTROL_IB (1<<18)
  175. #define LCD_CLKCONTROL_IC (1<<17)
  176. #define LCD_CLKCONTROL_IH (1<<16)
  177. #define LCD_CLKCONTROL_IV (1<<15)
  178. #define LCD_CLKCONTROL_BF_BIT 10
  179. #define LCD_CLKCONTROL_BF_MASK (0x1F << LCD_CLKCONTROL_BF_BIT)
  180. #define LCD_CLKCONTROL_BF_N(N) ((((N)-1) << LCD_CLKCONTROL_BF_BIT) & LCD_CLKCONTROL_BF_MASK)
  181. #define LCD_CLKCONTROL_PCD_BIT 0
  182. #define LCD_CLKCONTROL_PCD_MASK (0x3FF << LCD_CLKCONTROL_PCD_BIT)
  183. #define LCD_CLKCONTROL_PCD_N(N) (((N) << LCD_CLKCONTROL_PCD_BIT) & LCD_CLKCONTROL_PCD_MASK)
  184. #define LCD_DMAADDR0 (AU1100_LCD_BASE + 0x18)
  185. #define LCD_DMAADDR1 (AU1100_LCD_BASE + 0x1C)
  186. #define LCD_DMA_SA_BIT 5
  187. #define LCD_DMA_SA_MASK (0x7FFFFFF << LCD_DMA_SA_BIT)
  188. #define LCD_DMA_SA_N(N) ((N) & LCD_DMA_SA_MASK)
  189. #define LCD_WORDS (AU1100_LCD_BASE + 0x20)
  190. #define LCD_WRD_WRDS_BIT 0
  191. #define LCD_WRD_WRDS_MASK (0xFFFFFFFF << LCD_WRD_WRDS_BIT)
  192. #define LCD_WRD_WRDS_N(N) ((((N)-1) << LCD_WRD_WRDS_BIT) & LCD_WRD_WRDS_MASK)
  193. #define LCD_PWMDIV (AU1100_LCD_BASE + 0x24)
  194. #define LCD_PWMDIV_EN (1<<12)
  195. #define LCD_PWMDIV_PWMDIV_BIT 0
  196. #define LCD_PWMDIV_PWMDIV_MASK (0xFFF << LCD_PWMDIV_PWMDIV_BIT)
  197. #define LCD_PWMDIV_PWMDIV_N(N) ((((N)-1) << LCD_PWMDIV_PWMDIV_BIT) & LCD_PWMDIV_PWMDIV_MASK)
  198. #define LCD_PWMHI (AU1100_LCD_BASE + 0x28)
  199. #define LCD_PWMHI_PWMHI1_BIT 12
  200. #define LCD_PWMHI_PWMHI1_MASK (0xFFF << LCD_PWMHI_PWMHI1_BIT)
  201. #define LCD_PWMHI_PWMHI1_N(N) (((N) << LCD_PWMHI_PWMHI1_BIT) & LCD_PWMHI_PWMHI1_MASK)
  202. #define LCD_PWMHI_PWMHI0_BIT 0
  203. #define LCD_PWMHI_PWMHI0_MASK (0xFFF << LCD_PWMHI_PWMHI0_BIT)
  204. #define LCD_PWMHI_PWMHI0_N(N) (((N) << LCD_PWMHI_PWMHI0_BIT) & LCD_PWMHI_PWMHI0_MASK)
  205. #define LCD_PALLETTEBASE (AU1100_LCD_BASE + 0x400)
  206. #define LCD_PALLETTE_MONO_MI_BIT 0
  207. #define LCD_PALLETTE_MONO_MI_MASK (0xF << LCD_PALLETTE_MONO_MI_BIT)
  208. #define LCD_PALLETTE_MONO_MI_N(N) (((N)<< LCD_PALLETTE_MONO_MI_BIT) & LCD_PALLETTE_MONO_MI_MASK)
  209. #define LCD_PALLETTE_COLOR_RI_BIT 8
  210. #define LCD_PALLETTE_COLOR_RI_MASK (0xF << LCD_PALLETTE_COLOR_RI_BIT)
  211. #define LCD_PALLETTE_COLOR_RI_N(N) (((N)<< LCD_PALLETTE_COLOR_RI_BIT) & LCD_PALLETTE_COLOR_RI_MASK)
  212. #define LCD_PALLETTE_COLOR_GI_BIT 4
  213. #define LCD_PALLETTE_COLOR_GI_MASK (0xF << LCD_PALLETTE_COLOR_GI_BIT)
  214. #define LCD_PALLETTE_COLOR_GI_N(N) (((N)<< LCD_PALLETTE_COLOR_GI_BIT) & LCD_PALLETTE_COLOR_GI_MASK)
  215. #define LCD_PALLETTE_COLOR_BI_BIT 0
  216. #define LCD_PALLETTE_COLOR_BI_MASK (0xF << LCD_PALLETTE_COLOR_BI_BIT)
  217. #define LCD_PALLETTE_COLOR_BI_N(N) (((N)<< LCD_PALLETTE_COLOR_BI_BIT) & LCD_PALLETTE_COLOR_BI_MASK)
  218. #define LCD_PALLETTE_TFT_DC_BIT 0
  219. #define LCD_PALLETTE_TFT_DC_MASK (0xFFFF << LCD_PALLETTE_TFT_DC_BIT)
  220. #define LCD_PALLETTE_TFT_DC_N(N) (((N)<< LCD_PALLETTE_TFT_DC_BIT) & LCD_PALLETTE_TFT_DC_MASK)
  221. /********************************************************************/
  222. /* List of panels known to work with the AU1100 LCD controller.
  223. * To add a new panel, enter the same specifications as the
  224. * Generic_TFT one, and MAKE SURE that it doesn't conflicts
  225. * with the controller restrictions. Restrictions are:
  226. *
  227. * STN color panels: max_bpp <= 12
  228. * STN mono panels: max_bpp <= 4
  229. * TFT panels: max_bpp <= 16
  230. * max_xres <= 800
  231. * max_yres <= 600
  232. */
  233. static struct au1100fb_panel known_lcd_panels[] =
  234. {
  235. /* 800x600x16bpp CRT */
  236. [0] = {
  237. .name = "CRT_800x600_16",
  238. .xres = 800,
  239. .yres = 600,
  240. .bpp = 16,
  241. .control_base = 0x0004886A |
  242. LCD_CONTROL_DEFAULT_PO | LCD_CONTROL_DEFAULT_SBPPF |
  243. LCD_CONTROL_BPP_16 | LCD_CONTROL_SBB_4,
  244. .clkcontrol_base = 0x00020000,
  245. .horztiming = 0x005aff1f,
  246. .verttiming = 0x16000e57,
  247. },
  248. /* just the standard LCD */
  249. [1] = {
  250. .name = "WWPC LCD",
  251. .xres = 240,
  252. .yres = 320,
  253. .bpp = 16,
  254. .control_base = 0x0006806A,
  255. .horztiming = 0x0A1010EF,
  256. .verttiming = 0x0301013F,
  257. .clkcontrol_base = 0x00018001,
  258. },
  259. /* Sharp 320x240 TFT panel */
  260. [2] = {
  261. .name = "Sharp_LQ038Q5DR01",
  262. .xres = 320,
  263. .yres = 240,
  264. .bpp = 16,
  265. .control_base =
  266. ( LCD_CONTROL_SBPPF_565
  267. | LCD_CONTROL_C
  268. | LCD_CONTROL_SM_0
  269. | LCD_CONTROL_DEFAULT_PO
  270. | LCD_CONTROL_PT
  271. | LCD_CONTROL_PC
  272. | LCD_CONTROL_BPP_16 ),
  273. .horztiming =
  274. ( LCD_HORZTIMING_HN2_N(8)
  275. | LCD_HORZTIMING_HN1_N(60)
  276. | LCD_HORZTIMING_HPW_N(12)
  277. | LCD_HORZTIMING_PPL_N(320) ),
  278. .verttiming =
  279. ( LCD_VERTTIMING_VN2_N(5)
  280. | LCD_VERTTIMING_VN1_N(17)
  281. | LCD_VERTTIMING_VPW_N(1)
  282. | LCD_VERTTIMING_LPP_N(240) ),
  283. .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
  284. },
  285. /* Hitachi SP14Q005 and possibly others */
  286. [3] = {
  287. .name = "Hitachi_SP14Qxxx",
  288. .xres = 320,
  289. .yres = 240,
  290. .bpp = 4,
  291. .control_base =
  292. ( LCD_CONTROL_C
  293. | LCD_CONTROL_BPP_4 ),
  294. .horztiming =
  295. ( LCD_HORZTIMING_HN2_N(1)
  296. | LCD_HORZTIMING_HN1_N(1)
  297. | LCD_HORZTIMING_HPW_N(1)
  298. | LCD_HORZTIMING_PPL_N(320) ),
  299. .verttiming =
  300. ( LCD_VERTTIMING_VN2_N(1)
  301. | LCD_VERTTIMING_VN1_N(1)
  302. | LCD_VERTTIMING_VPW_N(1)
  303. | LCD_VERTTIMING_LPP_N(240) ),
  304. .clkcontrol_base = LCD_CLKCONTROL_PCD_N(4),
  305. },
  306. /* Generic 640x480 TFT panel */
  307. [4] = {
  308. .name = "TFT_640x480_16",
  309. .xres = 640,
  310. .yres = 480,
  311. .bpp = 16,
  312. .control_base = 0x004806a | LCD_CONTROL_DEFAULT_PO,
  313. .horztiming = 0x3434d67f,
  314. .verttiming = 0x0e0e39df,
  315. .clkcontrol_base = LCD_CLKCONTROL_PCD_N(1),
  316. },
  317. /* Pb1100 LCDB 640x480 PrimeView TFT panel */
  318. [5] = {
  319. .name = "PrimeView_640x480_16",
  320. .xres = 640,
  321. .yres = 480,
  322. .bpp = 16,
  323. .control_base = 0x0004886a | LCD_CONTROL_DEFAULT_PO,
  324. .horztiming = 0x0e4bfe7f,
  325. .verttiming = 0x210805df,
  326. .clkcontrol_base = 0x00038001,
  327. },
  328. };
  329. struct au1100fb_drv_info {
  330. int panel_idx;
  331. char *opt_mode;
  332. };
  333. /********************************************************************/
  334. /* Inline helpers */
  335. #define panel_is_dual(panel) (panel->control_base & LCD_CONTROL_DP)
  336. #define panel_is_active(panel)(panel->control_base & LCD_CONTROL_PT)
  337. #define panel_is_color(panel) (panel->control_base & LCD_CONTROL_PC)
  338. #define panel_swap_rgb(panel) (panel->control_base & LCD_CONTROL_CCO)
  339. #endif /* _AU1100LCD_H */