amba-clcd.c 12 KB

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  1. /*
  2. * linux/drivers/video/amba-clcd.c
  3. *
  4. * Copyright (C) 2001 ARM Limited, by David A Rusling
  5. * Updated to 2.5, Deep Blue Solutions Ltd.
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file COPYING in the main directory of this archive
  9. * for more details.
  10. *
  11. * ARM PrimeCell PL110 Color LCD Controller
  12. */
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/string.h>
  17. #include <linux/slab.h>
  18. #include <linux/delay.h>
  19. #include <linux/mm.h>
  20. #include <linux/fb.h>
  21. #include <linux/init.h>
  22. #include <linux/ioport.h>
  23. #include <linux/list.h>
  24. #include <linux/amba/bus.h>
  25. #include <linux/amba/clcd.h>
  26. #include <linux/clk.h>
  27. #include <asm/sizes.h>
  28. #define to_clcd(info) container_of(info, struct clcd_fb, fb)
  29. /* This is limited to 16 characters when displayed by X startup */
  30. static const char *clcd_name = "CLCD FB";
  31. /*
  32. * Unfortunately, the enable/disable functions may be called either from
  33. * process or IRQ context, and we _need_ to delay. This is _not_ good.
  34. */
  35. static inline void clcdfb_sleep(unsigned int ms)
  36. {
  37. if (in_atomic()) {
  38. mdelay(ms);
  39. } else {
  40. msleep(ms);
  41. }
  42. }
  43. static inline void clcdfb_set_start(struct clcd_fb *fb)
  44. {
  45. unsigned long ustart = fb->fb.fix.smem_start;
  46. unsigned long lstart;
  47. ustart += fb->fb.var.yoffset * fb->fb.fix.line_length;
  48. lstart = ustart + fb->fb.var.yres * fb->fb.fix.line_length / 2;
  49. writel(ustart, fb->regs + CLCD_UBAS);
  50. writel(lstart, fb->regs + CLCD_LBAS);
  51. }
  52. static void clcdfb_disable(struct clcd_fb *fb)
  53. {
  54. u32 val;
  55. if (fb->board->disable)
  56. fb->board->disable(fb);
  57. val = readl(fb->regs + CLCD_CNTL);
  58. if (val & CNTL_LCDPWR) {
  59. val &= ~CNTL_LCDPWR;
  60. writel(val, fb->regs + CLCD_CNTL);
  61. clcdfb_sleep(20);
  62. }
  63. if (val & CNTL_LCDEN) {
  64. val &= ~CNTL_LCDEN;
  65. writel(val, fb->regs + CLCD_CNTL);
  66. }
  67. /*
  68. * Disable CLCD clock source.
  69. */
  70. clk_disable(fb->clk);
  71. }
  72. static void clcdfb_enable(struct clcd_fb *fb, u32 cntl)
  73. {
  74. /*
  75. * Enable the CLCD clock source.
  76. */
  77. clk_enable(fb->clk);
  78. /*
  79. * Bring up by first enabling..
  80. */
  81. cntl |= CNTL_LCDEN;
  82. writel(cntl, fb->regs + CLCD_CNTL);
  83. clcdfb_sleep(20);
  84. /*
  85. * and now apply power.
  86. */
  87. cntl |= CNTL_LCDPWR;
  88. writel(cntl, fb->regs + CLCD_CNTL);
  89. /*
  90. * finally, enable the interface.
  91. */
  92. if (fb->board->enable)
  93. fb->board->enable(fb);
  94. }
  95. static int
  96. clcdfb_set_bitfields(struct clcd_fb *fb, struct fb_var_screeninfo *var)
  97. {
  98. int ret = 0;
  99. memset(&var->transp, 0, sizeof(var->transp));
  100. var->red.msb_right = 0;
  101. var->green.msb_right = 0;
  102. var->blue.msb_right = 0;
  103. switch (var->bits_per_pixel) {
  104. case 1:
  105. case 2:
  106. case 4:
  107. case 8:
  108. var->red.length = var->bits_per_pixel;
  109. var->red.offset = 0;
  110. var->green.length = var->bits_per_pixel;
  111. var->green.offset = 0;
  112. var->blue.length = var->bits_per_pixel;
  113. var->blue.offset = 0;
  114. break;
  115. case 16:
  116. var->red.length = 5;
  117. var->blue.length = 5;
  118. /*
  119. * Green length can be 5 or 6 depending whether
  120. * we're operating in RGB555 or RGB565 mode.
  121. */
  122. if (var->green.length != 5 && var->green.length != 6)
  123. var->green.length = 6;
  124. break;
  125. case 32:
  126. if (fb->panel->cntl & CNTL_LCDTFT) {
  127. var->red.length = 8;
  128. var->green.length = 8;
  129. var->blue.length = 8;
  130. break;
  131. }
  132. default:
  133. ret = -EINVAL;
  134. break;
  135. }
  136. /*
  137. * >= 16bpp displays have separate colour component bitfields
  138. * encoded in the pixel data. Calculate their position from
  139. * the bitfield length defined above.
  140. */
  141. if (ret == 0 && var->bits_per_pixel >= 16) {
  142. if (fb->panel->cntl & CNTL_BGR) {
  143. var->blue.offset = 0;
  144. var->green.offset = var->blue.offset + var->blue.length;
  145. var->red.offset = var->green.offset + var->green.length;
  146. } else {
  147. var->red.offset = 0;
  148. var->green.offset = var->red.offset + var->red.length;
  149. var->blue.offset = var->green.offset + var->green.length;
  150. }
  151. }
  152. return ret;
  153. }
  154. static int clcdfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  155. {
  156. struct clcd_fb *fb = to_clcd(info);
  157. int ret = -EINVAL;
  158. if (fb->board->check)
  159. ret = fb->board->check(fb, var);
  160. if (ret == 0 &&
  161. var->xres_virtual * var->bits_per_pixel / 8 *
  162. var->yres_virtual > fb->fb.fix.smem_len)
  163. ret = -EINVAL;
  164. if (ret == 0)
  165. ret = clcdfb_set_bitfields(fb, var);
  166. return ret;
  167. }
  168. static int clcdfb_set_par(struct fb_info *info)
  169. {
  170. struct clcd_fb *fb = to_clcd(info);
  171. struct clcd_regs regs;
  172. fb->fb.fix.line_length = fb->fb.var.xres_virtual *
  173. fb->fb.var.bits_per_pixel / 8;
  174. if (fb->fb.var.bits_per_pixel <= 8)
  175. fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
  176. else
  177. fb->fb.fix.visual = FB_VISUAL_TRUECOLOR;
  178. fb->board->decode(fb, &regs);
  179. clcdfb_disable(fb);
  180. writel(regs.tim0, fb->regs + CLCD_TIM0);
  181. writel(regs.tim1, fb->regs + CLCD_TIM1);
  182. writel(regs.tim2, fb->regs + CLCD_TIM2);
  183. writel(regs.tim3, fb->regs + CLCD_TIM3);
  184. clcdfb_set_start(fb);
  185. clk_set_rate(fb->clk, (1000000000 / regs.pixclock) * 1000);
  186. fb->clcd_cntl = regs.cntl;
  187. clcdfb_enable(fb, regs.cntl);
  188. #ifdef DEBUG
  189. printk(KERN_INFO "CLCD: Registers set to\n"
  190. KERN_INFO " %08x %08x %08x %08x\n"
  191. KERN_INFO " %08x %08x %08x %08x\n",
  192. readl(fb->regs + CLCD_TIM0), readl(fb->regs + CLCD_TIM1),
  193. readl(fb->regs + CLCD_TIM2), readl(fb->regs + CLCD_TIM3),
  194. readl(fb->regs + CLCD_UBAS), readl(fb->regs + CLCD_LBAS),
  195. readl(fb->regs + CLCD_IENB), readl(fb->regs + CLCD_CNTL));
  196. #endif
  197. return 0;
  198. }
  199. static inline u32 convert_bitfield(int val, struct fb_bitfield *bf)
  200. {
  201. unsigned int mask = (1 << bf->length) - 1;
  202. return (val >> (16 - bf->length) & mask) << bf->offset;
  203. }
  204. /*
  205. * Set a single color register. The values supplied have a 16 bit
  206. * magnitude. Return != 0 for invalid regno.
  207. */
  208. static int
  209. clcdfb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
  210. unsigned int blue, unsigned int transp, struct fb_info *info)
  211. {
  212. struct clcd_fb *fb = to_clcd(info);
  213. if (regno < 16)
  214. fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) |
  215. convert_bitfield(blue, &fb->fb.var.blue) |
  216. convert_bitfield(green, &fb->fb.var.green) |
  217. convert_bitfield(red, &fb->fb.var.red);
  218. if (fb->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR && regno < 256) {
  219. int hw_reg = CLCD_PALETTE + ((regno * 2) & ~3);
  220. u32 val, mask, newval;
  221. newval = (red >> 11) & 0x001f;
  222. newval |= (green >> 6) & 0x03e0;
  223. newval |= (blue >> 1) & 0x7c00;
  224. /*
  225. * 3.2.11: if we're configured for big endian
  226. * byte order, the palette entries are swapped.
  227. */
  228. if (fb->clcd_cntl & CNTL_BEBO)
  229. regno ^= 1;
  230. if (regno & 1) {
  231. newval <<= 16;
  232. mask = 0x0000ffff;
  233. } else {
  234. mask = 0xffff0000;
  235. }
  236. val = readl(fb->regs + hw_reg) & mask;
  237. writel(val | newval, fb->regs + hw_reg);
  238. }
  239. return regno > 255;
  240. }
  241. /*
  242. * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
  243. * then the caller blanks by setting the CLUT (Color Look Up Table) to all
  244. * black. Return 0 if blanking succeeded, != 0 if un-/blanking failed due
  245. * to e.g. a video mode which doesn't support it. Implements VESA suspend
  246. * and powerdown modes on hardware that supports disabling hsync/vsync:
  247. * blank_mode == 2: suspend vsync
  248. * blank_mode == 3: suspend hsync
  249. * blank_mode == 4: powerdown
  250. */
  251. static int clcdfb_blank(int blank_mode, struct fb_info *info)
  252. {
  253. struct clcd_fb *fb = to_clcd(info);
  254. if (blank_mode != 0) {
  255. clcdfb_disable(fb);
  256. } else {
  257. clcdfb_enable(fb, fb->clcd_cntl);
  258. }
  259. return 0;
  260. }
  261. static int clcdfb_mmap(struct fb_info *info,
  262. struct vm_area_struct *vma)
  263. {
  264. struct clcd_fb *fb = to_clcd(info);
  265. unsigned long len, off = vma->vm_pgoff << PAGE_SHIFT;
  266. int ret = -EINVAL;
  267. len = info->fix.smem_len;
  268. if (off <= len && vma->vm_end - vma->vm_start <= len - off &&
  269. fb->board->mmap)
  270. ret = fb->board->mmap(fb, vma);
  271. return ret;
  272. }
  273. static struct fb_ops clcdfb_ops = {
  274. .owner = THIS_MODULE,
  275. .fb_check_var = clcdfb_check_var,
  276. .fb_set_par = clcdfb_set_par,
  277. .fb_setcolreg = clcdfb_setcolreg,
  278. .fb_blank = clcdfb_blank,
  279. .fb_fillrect = cfb_fillrect,
  280. .fb_copyarea = cfb_copyarea,
  281. .fb_imageblit = cfb_imageblit,
  282. .fb_mmap = clcdfb_mmap,
  283. };
  284. static int clcdfb_register(struct clcd_fb *fb)
  285. {
  286. int ret;
  287. fb->clk = clk_get(&fb->dev->dev, "CLCDCLK");
  288. if (IS_ERR(fb->clk)) {
  289. ret = PTR_ERR(fb->clk);
  290. goto out;
  291. }
  292. fb->fb.fix.mmio_start = fb->dev->res.start;
  293. fb->fb.fix.mmio_len = SZ_4K;
  294. fb->regs = ioremap(fb->fb.fix.mmio_start, fb->fb.fix.mmio_len);
  295. if (!fb->regs) {
  296. printk(KERN_ERR "CLCD: unable to remap registers\n");
  297. ret = -ENOMEM;
  298. goto free_clk;
  299. }
  300. fb->fb.fbops = &clcdfb_ops;
  301. fb->fb.flags = FBINFO_FLAG_DEFAULT;
  302. fb->fb.pseudo_palette = fb->cmap;
  303. strncpy(fb->fb.fix.id, clcd_name, sizeof(fb->fb.fix.id));
  304. fb->fb.fix.type = FB_TYPE_PACKED_PIXELS;
  305. fb->fb.fix.type_aux = 0;
  306. fb->fb.fix.xpanstep = 0;
  307. fb->fb.fix.ypanstep = 0;
  308. fb->fb.fix.ywrapstep = 0;
  309. fb->fb.fix.accel = FB_ACCEL_NONE;
  310. fb->fb.var.xres = fb->panel->mode.xres;
  311. fb->fb.var.yres = fb->panel->mode.yres;
  312. fb->fb.var.xres_virtual = fb->panel->mode.xres;
  313. fb->fb.var.yres_virtual = fb->panel->mode.yres;
  314. fb->fb.var.bits_per_pixel = fb->panel->bpp;
  315. fb->fb.var.grayscale = fb->panel->grayscale;
  316. fb->fb.var.pixclock = fb->panel->mode.pixclock;
  317. fb->fb.var.left_margin = fb->panel->mode.left_margin;
  318. fb->fb.var.right_margin = fb->panel->mode.right_margin;
  319. fb->fb.var.upper_margin = fb->panel->mode.upper_margin;
  320. fb->fb.var.lower_margin = fb->panel->mode.lower_margin;
  321. fb->fb.var.hsync_len = fb->panel->mode.hsync_len;
  322. fb->fb.var.vsync_len = fb->panel->mode.vsync_len;
  323. fb->fb.var.sync = fb->panel->mode.sync;
  324. fb->fb.var.vmode = fb->panel->mode.vmode;
  325. fb->fb.var.activate = FB_ACTIVATE_NOW;
  326. fb->fb.var.nonstd = 0;
  327. fb->fb.var.height = fb->panel->height;
  328. fb->fb.var.width = fb->panel->width;
  329. fb->fb.var.accel_flags = 0;
  330. fb->fb.monspecs.hfmin = 0;
  331. fb->fb.monspecs.hfmax = 100000;
  332. fb->fb.monspecs.vfmin = 0;
  333. fb->fb.monspecs.vfmax = 400;
  334. fb->fb.monspecs.dclkmin = 1000000;
  335. fb->fb.monspecs.dclkmax = 100000000;
  336. /*
  337. * Make sure that the bitfields are set appropriately.
  338. */
  339. clcdfb_set_bitfields(fb, &fb->fb.var);
  340. /*
  341. * Allocate colourmap.
  342. */
  343. fb_alloc_cmap(&fb->fb.cmap, 256, 0);
  344. /*
  345. * Ensure interrupts are disabled.
  346. */
  347. writel(0, fb->regs + CLCD_IENB);
  348. fb_set_var(&fb->fb, &fb->fb.var);
  349. printk(KERN_INFO "CLCD: %s hardware, %s display\n",
  350. fb->board->name, fb->panel->mode.name);
  351. ret = register_framebuffer(&fb->fb);
  352. if (ret == 0)
  353. goto out;
  354. printk(KERN_ERR "CLCD: cannot register framebuffer (%d)\n", ret);
  355. iounmap(fb->regs);
  356. free_clk:
  357. clk_put(fb->clk);
  358. out:
  359. return ret;
  360. }
  361. static int clcdfb_probe(struct amba_device *dev, void *id)
  362. {
  363. struct clcd_board *board = dev->dev.platform_data;
  364. struct clcd_fb *fb;
  365. int ret;
  366. if (!board)
  367. return -EINVAL;
  368. ret = amba_request_regions(dev, NULL);
  369. if (ret) {
  370. printk(KERN_ERR "CLCD: unable to reserve regs region\n");
  371. goto out;
  372. }
  373. fb = kmalloc(sizeof(struct clcd_fb), GFP_KERNEL);
  374. if (!fb) {
  375. printk(KERN_INFO "CLCD: could not allocate new clcd_fb struct\n");
  376. ret = -ENOMEM;
  377. goto free_region;
  378. }
  379. memset(fb, 0, sizeof(struct clcd_fb));
  380. fb->dev = dev;
  381. fb->board = board;
  382. ret = fb->board->setup(fb);
  383. if (ret)
  384. goto free_fb;
  385. ret = clcdfb_register(fb);
  386. if (ret == 0) {
  387. amba_set_drvdata(dev, fb);
  388. goto out;
  389. }
  390. fb->board->remove(fb);
  391. free_fb:
  392. kfree(fb);
  393. free_region:
  394. amba_release_regions(dev);
  395. out:
  396. return ret;
  397. }
  398. static int clcdfb_remove(struct amba_device *dev)
  399. {
  400. struct clcd_fb *fb = amba_get_drvdata(dev);
  401. amba_set_drvdata(dev, NULL);
  402. clcdfb_disable(fb);
  403. unregister_framebuffer(&fb->fb);
  404. iounmap(fb->regs);
  405. clk_put(fb->clk);
  406. fb->board->remove(fb);
  407. kfree(fb);
  408. amba_release_regions(dev);
  409. return 0;
  410. }
  411. static struct amba_id clcdfb_id_table[] = {
  412. {
  413. .id = 0x00041110,
  414. .mask = 0x000ffffe,
  415. },
  416. { 0, 0 },
  417. };
  418. static struct amba_driver clcd_driver = {
  419. .drv = {
  420. .name = "clcd-pl11x",
  421. },
  422. .probe = clcdfb_probe,
  423. .remove = clcdfb_remove,
  424. .id_table = clcdfb_id_table,
  425. };
  426. static int __init amba_clcdfb_init(void)
  427. {
  428. if (fb_get_options("ambafb", NULL))
  429. return -ENODEV;
  430. return amba_driver_register(&clcd_driver);
  431. }
  432. module_init(amba_clcdfb_init);
  433. static void __exit amba_clcdfb_exit(void)
  434. {
  435. amba_driver_unregister(&clcd_driver);
  436. }
  437. module_exit(amba_clcdfb_exit);
  438. MODULE_DESCRIPTION("ARM PrimeCell PL110 CLCD core driver");
  439. MODULE_LICENSE("GPL");