s3c-hsmmc.c 72 KB

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  1. /*
  2. * linux/drivers/mmc/s3c-hsmmc.c - Samsung S3C24XX HS-MMC driver
  3. *
  4. * $Id: s3c-hsmmc.c,v 1.73 2008/04/13 23:56:19 jsgood Exp $
  5. *
  6. * Copyright (C) 2006 Samsung Electronics, All Rights Reserved.
  7. * by Suh, Seung-Chull<sc.suh@samsung.com>
  8. *
  9. * This driver is made for High Speed MMC interface. This interface
  10. * is adopted and implemented since s3c2443 was made.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. * Modified by Ryu,Euiyoul <steven.ryu@samsung.com>
  17. * Modified by Suh, Seung-chull to support s3c6400
  18. *
  19. * Note: s3c-hsmmc.c can be used for 1 channel only at same time.
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/init.h>
  24. #include <linux/ioport.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/delay.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/highmem.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/mmc/host.h>
  31. #include <linux/mmc/protocol.h>
  32. #include <linux/mmc/card.h>
  33. #include <linux/err.h>
  34. #include <linux/clk.h>
  35. #include <linux/proc_fs.h>
  36. #include <linux/irq.h>
  37. #include <linux/major.h> //Qisda, Asaku Chen, 2009/08/20, for wifi power
  38. #include <asm/dma.h>
  39. #include <asm/dma-mapping.h>
  40. #include <asm/io.h>
  41. #include <asm/irq.h>
  42. #include <asm/scatterlist.h>
  43. #include <asm/sizes.h>
  44. #include <asm/mach/mmc.h>
  45. #include <asm/arch/regs-gpio.h>
  46. #include <asm/arch/regs-gpioj.h>
  47. #include <asm/arch/regs-hsmmc.h>
  48. #include <asm/plat-s3c24xx/clock.h>
  49. #include <asm/arch/dma.h>
  50. #include <asm/arch/hsmmc.h>
  51. #include <linux/cyevent.h>
  52. /*Qisda , wenny cheng , 20091224 , board id info {*/
  53. #include <../include/asm-arm/plat-s3c24xx/common-smdk.h>
  54. /*Qisda , wenny cheng , 20091224 , board id info }*/
  55. /*Trevor add for debug*/
  56. /*#define CONFIG_S3CMMC_DEBUG*/
  57. #ifdef CONFIG_S3CMMC_DEBUG
  58. #define DBG(x...) printk(PFX x)
  59. #else
  60. #define DBG(x...) do { } while (0)
  61. #endif
  62. #include "s3c-hsmmc.h"
  63. #define DRIVER_NAME "s3c-hsmmc"
  64. #define PFX DRIVER_NAME ": "
  65. #define MULTICARD_ON_SINGLEBUS_SUPPORT
  66. #undef MULTICARD_ON_SINGLEBUS_SUPPORT
  67. #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
  68. #if defined(CONFIG_PM)
  69. struct s3c_hsmmc_host *global_host[3];
  70. #endif
  71. static void s3c_hsmmc_tasklet_finish (unsigned long param);
  72. /*Qisda , wenny cheng , 20091224 , board id info {*/
  73. extern int board_id;
  74. /*Qisda , wenny cheng , 20091224 , board id info }*/
  75. static int inResume = 0; //howard, 2009/12/22, fix resume card-detect
  76. /*Qisda,2009/7/28,Leo SJ Yang {*/
  77. /*Fix: Must plug-in twice ,SD is reconginzed by system*/
  78. /* GEORGE 20090608 update for module on board.*/
  79. static int card_detect = 0;
  80. static int card_detect2 = 2;
  81. /* GEORGE 20090608 update for module on board.*/
  82. /*}Qisda,2009/7/28,Leo SJ Yang*/
  83. /* Qisda , howard hsu, 2010/01/16 , op_mode-delay key event {*/
  84. //extern void op_mode_delay_message_to_ap();
  85. /* } Qisda , howard hsu, 2010/01/16 , op_mode-delay key event */
  86. /* Qisda, howard hsu, 2010/01/21, SW_DEBOUNCE for sd card { */
  87. // disable it first, wait integration test
  88. #ifdef CONFIG_SD_SW_DEBOUNCE
  89. static int SDCardStatus = 16;
  90. #define SD_INSERTED 0
  91. #define SD_REMOVED 2
  92. #define CHECK_MSEC 50
  93. #define INSERT_MSEC 800
  94. #define REMOVE_MSEC 800
  95. static struct timer_list sd_detect_timer;
  96. static void sdcard_debounce_timer(unsigned long data);
  97. static int ReadSDCardStatus()
  98. {
  99. int SDStatus= 0;
  100. #if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  101. SDStatus = readl(S3C2410_GPFDAT);
  102. SDStatus &= SD_REMOVED; /* GPF1 */
  103. #elif defined(CONFIG_CPU_S3C6410)
  104. SDStatus = readl(S3C_GPNDAT);
  105. SDStatus &= 0x2000; /* GPN13 */
  106. #endif
  107. return SDStatus;
  108. }
  109. static void sdcard_debounce_timer(unsigned long data)
  110. {
  111. static unsigned int StayCount = 0;
  112. static unsigned int MaxCount = 2*INSERT_MSEC/CHECK_MSEC;
  113. static unsigned int MidCount = INSERT_MSEC/CHECK_MSEC;
  114. static unsigned int MinCount = INSERT_MSEC/CHECK_MSEC/2;
  115. static int LastSDCardStatus = 0xF;
  116. int RawStatus = ReadSDCardStatus();
  117. /* stay count in case of resume in progress */
  118. if (inResume == 1)
  119. {
  120. mod_timer(&sd_detect_timer ,jiffies+msecs_to_jiffies(CHECK_MSEC));
  121. return;
  122. }
  123. if ( SDCardStatus == RawStatus )
  124. {
  125. StayCount++;
  126. if (StayCount >= MaxCount)
  127. {
  128. StayCount = 0;
  129. LastSDCardStatus = SDCardStatus;
  130. del_timer(&sd_detect_timer);
  131. }
  132. else if (StayCount == MidCount)
  133. {
  134. struct s3c_hsmmc_host *s3c_host = global_host[0];
  135. struct mmc_host *host = s3c_host->mmc;
  136. if (SDCardStatus == LastSDCardStatus )
  137. {
  138. //StayCount = 0;
  139. //LastSDCardStatus = 0xF;
  140. }
  141. mmc_detect_change(host, 1);
  142. mod_timer(&sd_detect_timer, jiffies+msecs_to_jiffies(CHECK_MSEC));
  143. }
  144. else if ( StayCount==MinCount )
  145. {
  146. /* call detect twice for SD_INSERTED case */
  147. //if (SDCardStatus == LastSDCardStatus )
  148. if (SDCardStatus == SD_INSERTED )
  149. {
  150. struct s3c_hsmmc_host *s3c_host = global_host[0];
  151. struct mmc_host *host = s3c_host->mmc;
  152. mmc_detect_change(host, 1);
  153. }
  154. mod_timer(&sd_detect_timer, jiffies+msecs_to_jiffies(CHECK_MSEC));
  155. }
  156. else
  157. {
  158. mod_timer(&sd_detect_timer, jiffies+msecs_to_jiffies(CHECK_MSEC));
  159. }
  160. }
  161. else
  162. {
  163. SDCardStatus = RawStatus;
  164. if (SDCardStatus==SD_INSERTED) {
  165. MaxCount = 2*INSERT_MSEC/CHECK_MSEC;
  166. MidCount = INSERT_MSEC/CHECK_MSEC;
  167. }
  168. else {
  169. MaxCount = 2*REMOVE_MSEC/CHECK_MSEC;
  170. MidCount = REMOVE_MSEC/CHECK_MSEC;
  171. }
  172. StayCount = 0;
  173. mod_timer(&sd_detect_timer ,jiffies+msecs_to_jiffies(CHECK_MSEC));
  174. }
  175. }
  176. #endif /* CONFIG_SD_SW_DEBOUNCE */
  177. /* } Qisda, howard hsu, 2010/01/21, SW_DEBOUNCE for sd card */
  178. /*****************************************************************************\
  179. * *
  180. * Low level functions *
  181. * *
  182. \*****************************************************************************/
  183. static struct s3c_hsmmc_cfg s3c_hsmmc_platform = {
  184. .hwport = 0,
  185. .enabled = 0,
  186. .host_caps = (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE),
  187. .base = NULL,
  188. .highspeed = 0,
  189. /* ctrl for mmc */
  190. .fd_ctrl[0] = {
  191. .ctrl2 = 0xC0004100, /* ctrl2 for mmc */
  192. .ctrl3[0] = 0x80808080, /* ctrl3 for low speed */
  193. .ctrl3[1] = 0x00000080, /* ctrl3 for high speed */
  194. .ctrl4 = 0,
  195. },
  196. /* ctrl for sd */
  197. .fd_ctrl[1] = {
  198. .ctrl2 = 0xC0000100, /* ctrl2 for sd */
  199. .ctrl3[0] = 0, /* ctrl3 for low speed */
  200. .ctrl3[1] = 0, /* ctrl3 for high speed */
  201. .ctrl4 = 0,
  202. },
  203. };
  204. static int s3c_hsmmc_power_switch(int channel, int arg)
  205. {
  206. //printk("\n== s3c_hsmmc_power_switch, channel: %d, power: %d\n", channel, arg);
  207. if(arg){
  208. if(channel == 0){
  209. //Power on
  210. #ifdef CONFIG_QISDA_QD090B00
  211. /*Qisda , wenny cheng , 20091224 , board id info {*/
  212. //if((readl(S3C2416_GPKDAT) & (0x3<<3))){
  213. if(board_id!=QD090B00_S02){
  214. s3c2410_gpio_cfgpin(S3C2410_GPD14, S3C2410_GPD14_OUTP);
  215. s3c2410_gpio_setpin(S3C2410_GPD14, 1);
  216. }
  217. else{
  218. s3c2410_gpio_cfgpin(S3C2410_GPG2, S3C2410_GPG2_OUTP);
  219. s3c2410_gpio_setpin(S3C2410_GPG2, 1);
  220. }
  221. /*Qisda , wenny cheng , 20091224 , board id info }*/
  222. #endif
  223. #ifdef CONFIG_QISDA_QD060B00
  224. #ifdef CONFIG_QISDA_BK060B00
  225. s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_OUTP);
  226. s3c2410_gpio_setpin(S3C2410_GPH4, 1);
  227. #else
  228. s3c2410_gpio_cfgpin(S3C2410_GPG2, S3C2410_GPG2_OUTP);
  229. s3c2410_gpio_setpin(S3C2410_GPG2, 1);
  230. #endif
  231. #endif
  232. //Signal
  233. s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2450_GPE5_SD0_CLK);
  234. s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2450_GPE6_SD0_CMD);
  235. s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
  236. s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2450_GPE8_SD0_DAT1);
  237. s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2450_GPE9_SD0_DAT2);
  238. s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2450_GPE10_SD0_DAT3);
  239. }
  240. else if(channel == 1){
  241. s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2450_GPL8_SD1CMD);
  242. s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2450_GPL9_SD1CLK);
  243. s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
  244. s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
  245. s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
  246. s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
  247. }
  248. }
  249. else{
  250. if(channel == 0){
  251. //Power off
  252. #ifdef CONFIG_QISDA_QD090B00
  253. /*Qisda , wenny cheng , 20091224 , board id info {*/
  254. //if((readl(S3C2416_GPKDAT) & (0x3<<3))){
  255. if(board_id!=QD090B00_S02){
  256. s3c2410_gpio_cfgpin(S3C2410_GPD14, S3C2410_GPD14_OUTP);
  257. s3c2410_gpio_setpin(S3C2410_GPD14, 0);
  258. }
  259. else{
  260. s3c2410_gpio_cfgpin(S3C2410_GPG2, S3C2410_GPG2_OUTP);
  261. s3c2410_gpio_setpin(S3C2410_GPG2, 0);
  262. }
  263. /*Qisda , wenny cheng , 20091224 , board id info }*/
  264. #endif
  265. #ifdef CONFIG_QISDA_QD060B00
  266. #ifdef CONFIG_QISDA_BK060B00
  267. s3c2410_gpio_cfgpin(S3C2410_GPH4, S3C2410_GPH4_OUTP);
  268. s3c2410_gpio_setpin(S3C2410_GPH4, 0);
  269. #else
  270. s3c2410_gpio_cfgpin(S3C2410_GPG2, S3C2410_GPG2_OUTP);
  271. s3c2410_gpio_setpin(S3C2410_GPG2, 0);
  272. #endif
  273. #endif
  274. //Signal
  275. s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2410_GPE5_INP);
  276. s3c2410_gpio_pullup(S3C2410_GPE5, 1);
  277. s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2410_GPE6_INP);
  278. s3c2410_gpio_pullup(S3C2410_GPE6, 1);
  279. s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2410_GPE7_INP);
  280. s3c2410_gpio_pullup(S3C2410_GPE7, 1);
  281. s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_INP);
  282. s3c2410_gpio_pullup(S3C2410_GPE8, 1);
  283. s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2410_GPE9_INP);
  284. s3c2410_gpio_pullup(S3C2410_GPE9, 1);
  285. s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2410_GPE10_INP);
  286. s3c2410_gpio_pullup(S3C2410_GPE10, 1);
  287. }
  288. else if(channel == 1){
  289. s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2443_GPL8_INP);
  290. s3c2410_gpio_pullup(S3C2443_GPL8, 0);
  291. s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2443_GPL9_INP);
  292. s3c2410_gpio_pullup(S3C2443_GPL9, 1);
  293. s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C3443_GPL0_INP);
  294. s3c2410_gpio_pullup(S3C2443_GPL0, 0);
  295. s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2443_GPL1_INP);
  296. s3c2410_gpio_pullup(S3C2443_GPL1, 0);
  297. s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2443_GPL2_INP);
  298. s3c2410_gpio_pullup(S3C2443_GPL2, 0);
  299. s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2443_GPL3_INP);
  300. s3c2410_gpio_pullup(S3C2443_GPL3, 0);
  301. }
  302. }
  303. }
  304. /* s3c_hsmmc_get_platdata
  305. *
  306. * get the platform data associated with the given device, or return
  307. * the default if there is none
  308. */
  309. static struct s3c_hsmmc_cfg *s3c_hsmmc_get_platdata (struct device *dev)
  310. {
  311. if (dev->platform_data != NULL)
  312. return (struct s3c_hsmmc_cfg *)dev->platform_data;
  313. return &s3c_hsmmc_platform;
  314. }
  315. static void s3c_hsmmc_reset (struct s3c_hsmmc_host *host, u8 mask)
  316. {
  317. unsigned long timeout;
  318. s3c_hsmmc_writeb(mask, S3C_HSMMC_SWRST);
  319. if (mask & S3C_HSMMC_RESET_ALL)
  320. host->clock = (uint)-1;
  321. /* Wait max 100 ms */
  322. timeout = 100;
  323. /* hw clears the bit when it's done */
  324. while (s3c_hsmmc_readb(S3C_HSMMC_SWRST) & mask) {
  325. if (timeout == 0) {
  326. printk("%s: Reset 0x%x never completed. \n",
  327. mmc_hostname(host->mmc), (int)mask);
  328. return;
  329. }
  330. timeout--;
  331. mdelay(1);
  332. }
  333. }
  334. static void s3c_hsmmc_ios_init (struct s3c_hsmmc_host *host)
  335. {
  336. u32 intmask;
  337. s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL);
  338. intmask = S3C_HSMMC_INT_BUS_POWER | S3C_HSMMC_INT_DATA_END_BIT |
  339. S3C_HSMMC_INT_DATA_CRC | S3C_HSMMC_INT_DATA_TIMEOUT | S3C_HSMMC_INT_INDEX |
  340. S3C_HSMMC_INT_END_BIT | S3C_HSMMC_INT_CRC | S3C_HSMMC_INT_TIMEOUT |
  341. S3C_HSMMC_INT_CARD_REMOVE | S3C_HSMMC_INT_CARD_INSERT |
  342. S3C_HSMMC_INT_DATA_AVAIL | S3C_HSMMC_INT_SPACE_AVAIL |
  343. S3C_HSMMC_INT_DATA_END | S3C_HSMMC_INT_RESPONSE;
  344. #ifdef CONFIG_HSMMC_SCATTERGATHER
  345. intmask |= S3C_HSMMC_INT_DMA_END;
  346. #endif
  347. s3c_hsmmc_writel(intmask, S3C_HSMMC_NORINTSTSEN);
  348. s3c_hsmmc_writel(intmask, S3C_HSMMC_NORINTSIGEN);
  349. }
  350. /*****************************************************************************\
  351. * *
  352. * Tasklets *
  353. * *
  354. \*****************************************************************************/
  355. static void s3c_hsmmc_tasklet_card (ulong param)
  356. {
  357. struct s3c_hsmmc_host *host;
  358. unsigned long iflags;
  359. host = (struct s3c_hsmmc_host*)param;
  360. spin_lock_irqsave(&host->lock, iflags);
  361. if (!(s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & S3C_HSMMC_CARD_PRESENT)) {
  362. if (host->mrq) {
  363. printk(KERN_ERR "%s: Card removed during transfer!\n",
  364. mmc_hostname(host->mmc));
  365. printk(KERN_ERR "%s: Resetting controller.\n",
  366. mmc_hostname(host->mmc));
  367. s3c_hsmmc_reset(host, S3C_HSMMC_RESET_CMD);
  368. s3c_hsmmc_reset(host, S3C_HSMMC_RESET_DATA);
  369. host->mrq->cmd->error = MMC_ERR_FAILED;
  370. /* tasklet_schedule(&host->finish_tasklet); */
  371. s3c_hsmmc_tasklet_finish((unsigned long) host);
  372. }
  373. }
  374. spin_unlock_irqrestore(&host->lock, iflags);
  375. /* Qisda, howard hsu, 2010/01/21, SW_DEBOUNCE for sd card { */
  376. #ifdef CONFIG_SD_SW_DEBOUNCE
  377. int exist = timer_pending(&sd_detect_timer);
  378. if (exist == 0)
  379. {
  380. sd_detect_timer.expires = jiffies+msecs_to_jiffies(CHECK_MSEC);
  381. add_timer(&sd_detect_timer);
  382. }
  383. #else
  384. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  385. #endif /* CONFIG_SD_SW_DEBOUNCE */
  386. /* } Qisda, howard hsu, 2010/01/21, SW_DEBOUNCE for sd card */
  387. }
  388. static void s3c_hsmmc_activate_led(struct s3c_hsmmc_host *host)
  389. {
  390. #if 0
  391. u8 ctrl;
  392. ctrl = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
  393. ctrl |= S3C_HSMMC_CTRL_LED;
  394. s3c_hsmmc_writeb(ctrl, S3C_HSMMC_HOSTCTL);
  395. #endif
  396. #if 0 // for 6400
  397. s3c_gpio_cfgpin(S3C_GPJ13, S3C_GPJ13_SD0LED);
  398. #endif
  399. }
  400. static void s3c_hsmmc_deactivate_led(struct s3c_hsmmc_host *host)
  401. {
  402. #if 0
  403. u8 ctrl;
  404. ctrl = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
  405. ctrl &= ~S3C_HSMMC_CTRL_LED;
  406. s3c_hsmmc_writeb(ctrl, S3C_HSMMC_HOSTCTL);
  407. #endif
  408. #if 0 // for 6400
  409. s3c_gpio_cfgpin(S3C_GPJ13, S3C_GPJ13_INP);
  410. #endif
  411. }
  412. /*****************************************************************************\
  413. * *
  414. * Core functions *
  415. * *
  416. \*****************************************************************************/
  417. #ifdef CONFIG_HSMMC_SCATTERGATHER
  418. static inline uint s3c_hsmmc_build_dma_table (struct s3c_hsmmc_host *host,
  419. struct mmc_data *data)
  420. {
  421. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
  422. uint i, j = 0, sub_num = 0;
  423. dma_addr_t addr;
  424. uint size, length, end;
  425. int boundary, xor_bit;
  426. struct scatterlist * sg = data->sg;
  427. /* build dma table except last one */
  428. for (i=0; i<(host->sg_len-1); i++) {
  429. addr = sg[i].dma_address;
  430. size = sg[i].length;
  431. DBG("%d - addr: %08x, size: %08x\n", i, addr, size);
  432. for (; (j<CONFIG_S3C_HSMMC_MAX_HW_SEGS*4) && size; j++) {
  433. end = addr + size;
  434. xor_bit = min(7+(2+8+2), fls(addr^end) -1);
  435. DBG("%08x %08x %08x %d\n", addr, size, end, xor_bit);
  436. host->dblk[j].dma_address = addr;
  437. length = (end & ~((1<<xor_bit)-1)) - addr;
  438. boundary = xor_bit - (2+8+2);
  439. DBG("length: %x, boundary: %d\n", length, boundary);
  440. if (length < S3C_HSMMC_MALLOC_SIZE) {
  441. boundary = 0;
  442. if ((addr+length) & (S3C_HSMMC_MALLOC_SIZE-1)) {
  443. void *dest;
  444. DBG("#########error fixing: %08x, %x\n", addr, length);
  445. dest = host->sub_block[sub_num] + S3C_HSMMC_MALLOC_SIZE - length;
  446. if (data->flags & MMC_DATA_WRITE) { /* write */
  447. memcpy(dest, phys_to_virt(addr), length);
  448. }
  449. host->dblk[j].original = phys_to_virt(addr);
  450. host->dblk[j].dma_address = dma_map_single(NULL, dest, length, host->dma_dir);
  451. sub_num++;
  452. }
  453. }
  454. host->dblk[j].length = length;
  455. host->dblk[j].boundary = boundary;
  456. DBG(" %d: %08x, %08x %x\n",
  457. j, addr, length, boundary);
  458. addr += length;
  459. size -= length;
  460. }
  461. }
  462. /* the last one */
  463. host->dblk[j].dma_address = sg[i].dma_address;
  464. host->dblk[j].length = sg[i].length;
  465. host->dblk[j].boundary = 0x7;
  466. return (j+1);
  467. #elif defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  468. uint i;
  469. struct scatterlist * sg = data->sg;
  470. /* build dma table except the last one */
  471. for (i=0; i<(host->sg_len-1); i++) {
  472. host->sdma_descr_tbl[i].dma_address = sg[i].dma_address;
  473. host->sdma_descr_tbl[i].length_attr = (sg[i].length << 16) | (S3C_HSMMC_ADMA_ATTR_ACT_TRAN) |
  474. (S3C_HSMMC_ADMA_ATTR_VALID);
  475. DBG(" ADMA2 descr table[%d] - addr: %08x, size+attr: %08x\n", i, host->sdma_descr_tbl[i].dma_address,
  476. host->sdma_descr_tbl[i].length_attr);
  477. }
  478. /* the last one */
  479. host->sdma_descr_tbl[i].dma_address = sg[i].dma_address;
  480. host->sdma_descr_tbl[i].length_attr = (sg[i].length << 16) | (S3C_HSMMC_ADMA_ATTR_ACT_TRAN) |
  481. (S3C_HSMMC_ADMA_ATTR_END | S3C_HSMMC_ADMA_ATTR_VALID);
  482. DBG(" ADMA2 descr table[%d] - addr: %08x, size+attr: %08x\n", i, host->sdma_descr_tbl[i].dma_address,
  483. host->sdma_descr_tbl[i].length_attr);
  484. return (i);
  485. #endif
  486. }
  487. #endif
  488. static inline void s3c_hsmmc_prepare_data (struct s3c_hsmmc_host *host,
  489. struct mmc_command *cmd)
  490. {
  491. #if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  492. u8 reg8;
  493. #endif
  494. u32 reg;
  495. struct mmc_data *data = cmd->data;
  496. if (data == NULL) {
  497. reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN) | S3C_HSMMC_NIS_CMDCMP;
  498. s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN);
  499. return;
  500. }
  501. reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN) & ~S3C_HSMMC_NIS_CMDCMP;
  502. s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN);
  503. host->dma_dir = (data->flags & MMC_DATA_READ)
  504. ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
  505. #ifdef CONFIG_HSMMC_SCATTERGATHER
  506. host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  507. host->dma_dir);
  508. reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN);
  509. if (host->sg_len == 1) {
  510. reg &= ~S3C_HSMMC_NIS_DMA;
  511. } else {
  512. reg |= S3C_HSMMC_NIS_DMA;
  513. }
  514. s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN);
  515. #if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  516. reg8 = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
  517. reg8 |= S3C_HSMMC_CTRL_ADMA2_32;
  518. s3c_hsmmc_writeb(reg8, S3C_HSMMC_HOSTCTL);
  519. DBG("HOSTCTL(0x28) = 0x%02x\n", s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL));
  520. #endif
  521. DBG("data->flags(direction) = 0x%x\n", data->flags);
  522. DBG("data->blksz: %d\n", data->blksz);
  523. DBG("data->blocks: %d\n", data->blocks);
  524. DBG("data->sg_len: %d\n", data->sg_len);
  525. DBG("data->sg->addr: 0x%x\n", data->sg->dma_address);
  526. DBG("data->sg->length: 0x%x\n", data->sg->length);
  527. host->dma_blk = s3c_hsmmc_build_dma_table(host, data);
  528. host->next_blk = 0;
  529. #else
  530. DBG("data->flags(direction) = 0x%x\n", data->flags);
  531. DBG("data->blksz: %d\n", data->blksz);
  532. DBG("data->blocks: %d\n", data->blocks);
  533. DBG("data->sg_len: %d\n", data->sg_len);
  534. dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  535. host->dma_dir);
  536. #endif
  537. }
  538. static inline void s3c_hsmmc_set_transfer_mode (struct s3c_hsmmc_host *host,
  539. struct mmc_data *data)
  540. {
  541. u16 mode;
  542. mode = S3C_HSMMC_TRNS_DMA;
  543. if (data->stop)
  544. mode |= S3C_HSMMC_TRNS_ACMD12;
  545. if (data->flags & MMC_DATA_MULTI)
  546. mode |= S3C_HSMMC_TRNS_MULTI | S3C_HSMMC_TRNS_BLK_CNT_EN;
  547. if (data->flags & MMC_DATA_READ)
  548. mode |= S3C_HSMMC_TRNS_READ;
  549. s3c_hsmmc_writew(mode, S3C_HSMMC_TRNMOD);
  550. }
  551. static inline void s3c_hsmmc_send_register (struct s3c_hsmmc_host *host)
  552. {
  553. struct mmc_command *cmd = host->cmd;
  554. struct mmc_data *data = cmd->data;
  555. u32 cmd_val;
  556. if (data) {
  557. #ifdef CONFIG_HSMMC_SCATTERGATHER
  558. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
  559. struct s3c_hsmmc_dma_blk *dblk;
  560. dblk = &host->dblk[0];
  561. s3c_hsmmc_writew(S3C_HSMMC_MAKE_BLKSZ(dblk->boundary, data->blksz),
  562. S3C_HSMMC_BLKSIZE);
  563. s3c_hsmmc_writel(dblk->dma_address, S3C_HSMMC_SYSAD);
  564. #elif defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  565. s3c_hsmmc_writew(S3C_HSMMC_MAKE_BLKSZ(0x7, data->blksz), S3C_HSMMC_BLKSIZE);
  566. s3c_hsmmc_writel(virt_to_phys(host->sdma_descr_tbl), S3C_HSMMC_ADMASYSADDR);
  567. DBG("S3C_HSMMC_ADMASYSADDR(0x58) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_ADMASYSADDR));
  568. #endif
  569. #else
  570. s3c_hsmmc_writew(S3C_HSMMC_MAKE_BLKSZ(0x7, data->blksz), S3C_HSMMC_BLKSIZE);
  571. s3c_hsmmc_writel(sg_dma_address(data->sg), S3C_HSMMC_SYSAD);
  572. #endif
  573. s3c_hsmmc_writew(data->blocks, S3C_HSMMC_BLKCNT);
  574. s3c_hsmmc_set_transfer_mode(host, data);
  575. }
  576. s3c_hsmmc_writel(cmd->arg, S3C_HSMMC_ARGUMENT);
  577. cmd_val = (cmd->opcode << 8);
  578. if (cmd_val == (12<<8))
  579. cmd_val |= (3 << 6);
  580. if (cmd->flags & MMC_RSP_136) /* Long RSP */
  581. cmd_val |= S3C_HSMMC_CMD_RESP_LONG;
  582. else if (cmd->flags & MMC_RSP_BUSY) /* R1B */
  583. cmd_val |= S3C_HSMMC_CMD_RESP_SHORT_BUSY;
  584. else if (cmd->flags & MMC_RSP_PRESENT) /* Normal RSP */
  585. cmd_val |= S3C_HSMMC_CMD_RESP_SHORT;
  586. if (cmd->flags & MMC_RSP_OPCODE)
  587. cmd_val |= S3C_HSMMC_CMD_INDEX;
  588. if (cmd->flags & MMC_RSP_CRC)
  589. cmd_val |= S3C_HSMMC_CMD_CRC;
  590. if (data)
  591. cmd_val |= S3C_HSMMC_CMD_DATA;
  592. s3c_hsmmc_writew(cmd_val, S3C_HSMMC_CMDREG);
  593. }
  594. static inline void s3c_hsmmc_send_command (struct s3c_hsmmc_host *host,
  595. struct mmc_command *cmd)
  596. {
  597. u32 mask=1;
  598. ulong timeout;
  599. #if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  600. while (s3c_hsmmc_readl(S3C_HSMMC_CONTROL4) & mask);
  601. #endif
  602. DBG("Sending cmd=(%d), arg=0x%x\n", cmd->opcode, cmd->arg);
  603. /* Wait max 10 ms */
  604. timeout = 10;
  605. mask = S3C_HSMMC_CMD_INHIBIT;
  606. if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
  607. mask |= S3C_HSMMC_DATA_INHIBIT;
  608. while (s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & mask) {
  609. printk("########### waiting controller wakeup\n");
  610. if (timeout == 0) {
  611. printk(KERN_ERR "%s: Controller never released "
  612. "inhibit bit(s).\n", mmc_hostname(host->mmc));
  613. cmd->error = MMC_ERR_FAILED;
  614. /* tasklet_schedule(&host->finish_tasklet); */
  615. s3c_hsmmc_tasklet_finish((unsigned long) host);
  616. return;
  617. }
  618. timeout--;
  619. mdelay(1);
  620. }
  621. mod_timer(&host->timer, jiffies + 10 * HZ);
  622. host->cmd = cmd;
  623. s3c_hsmmc_prepare_data(host, cmd);
  624. s3c_hsmmc_send_register(host);
  625. }
  626. static void s3c_hsmmc_finish_data (struct s3c_hsmmc_host *host)
  627. {
  628. struct mmc_data *data;
  629. u16 blocks;
  630. //BUG_ON(!host->data);
  631. if(!host->data) return;
  632. data = host->data;
  633. host->data = NULL;
  634. dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
  635. (data->flags & MMC_DATA_READ)
  636. ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
  637. /*
  638. * Controller doesn't count down when in single block mode.
  639. */
  640. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  641. blocks = 0;
  642. else {
  643. blocks = s3c_hsmmc_readw(S3C_HSMMC_BLKCNT);
  644. }
  645. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  646. if ((data->error == MMC_ERR_NONE) && blocks) {
  647. printk(KERN_ERR "%s: Controller signalled completion even "
  648. "though there were blocks left. : %d\n",
  649. mmc_hostname(host->mmc), blocks);
  650. data->error = MMC_ERR_FAILED;
  651. }
  652. DBG("data->flags(direction) FINISHED = %d\n", data->flags);
  653. DBG("data->blksz FINISHED = %d\n", data->blksz);
  654. DBG("data->blocks FINISHED = %d\n", data->blocks);
  655. DBG("Not FINISHED blocks = %d\n", blocks);
  656. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  657. DBG("\n");
  658. /* tasklet_schedule(&host->finish_tasklet); */
  659. s3c_hsmmc_tasklet_finish((unsigned long) host);
  660. }
  661. static void s3c_hsmmc_finish_command (struct s3c_hsmmc_host *host)
  662. {
  663. int i;
  664. //BUG_ON(host->cmd == NULL);
  665. if(!host->cmd) return;
  666. if (host->cmd->flags & MMC_RSP_PRESENT) {
  667. if (host->cmd->flags & MMC_RSP_136) {
  668. /* CRC is stripped so we need to do some shifting. */
  669. for (i=0; i<4; i++) {
  670. host->cmd->resp[i] = s3c_hsmmc_readl(S3C_HSMMC_RSPREG0+ (3-i)*4) << 8;
  671. if (i != 3)
  672. host->cmd->resp[i] |= s3c_hsmmc_readb(S3C_HSMMC_RSPREG0 + (3-i)*4-1);
  673. DBG("cmd (%d) resp[%d] = 0x%x\n", host->cmd->opcode, i, host->cmd->resp[i]);
  674. }
  675. } else {
  676. host->cmd->resp[0] = s3c_hsmmc_readl(S3C_HSMMC_RSPREG0);
  677. DBG("cmd (%d) resp[%d] = 0x%x\n", host->cmd->opcode, 0, host->cmd->resp[0]);
  678. }
  679. }
  680. host->cmd->error = MMC_ERR_NONE;
  681. DBG("Ending cmd (%d)\n", host->cmd->opcode);
  682. DBG("\n");
  683. if (host->cmd->data)
  684. host->data = host->cmd->data;
  685. else
  686. /* tasklet_schedule(&host->finish_tasklet); */
  687. s3c_hsmmc_tasklet_finish((unsigned long) host);
  688. host->cmd = NULL;
  689. }
  690. static void s3c_hsmmc_tasklet_finish (unsigned long param)
  691. {
  692. struct s3c_hsmmc_host *host;
  693. unsigned long iflags;
  694. struct mmc_request *mrq;
  695. host = (struct s3c_hsmmc_host*)param;
  696. //BUG_ON(!host->mrq);
  697. if(!host->mrq) return;
  698. spin_lock_irqsave(&host->lock, iflags);
  699. del_timer(&host->timer);
  700. mrq = host->mrq;
  701. udelay(10);
  702. /*
  703. * The controller needs a reset of internal state machines
  704. * upon error conditions.
  705. */
  706. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  707. (mrq->data && (mrq->data->error != MMC_ERR_NONE)) ) {
  708. s3c_hsmmc_reset(host, S3C_HSMMC_RESET_CMD);
  709. s3c_hsmmc_reset(host, S3C_HSMMC_RESET_DATA);
  710. }
  711. host->mrq = NULL;
  712. host->cmd = NULL;
  713. host->data = NULL;
  714. s3c_hsmmc_deactivate_led(host);
  715. mmiowb();
  716. spin_unlock_irqrestore(&host->lock, iflags);
  717. mmc_request_done(host->mmc, mrq);
  718. }
  719. /*****************************************************************************
  720. * *
  721. * Interrupt handling *
  722. * *
  723. *****************************************************************************/
  724. static void s3c_hsmmc_cmd_irq (struct s3c_hsmmc_host *host, u32 intmask)
  725. {
  726. if (!host->cmd) {
  727. printk(KERN_ERR "%s: Got command interrupt 0x%08x even "
  728. "though no command operation was in progress.\n",
  729. mmc_hostname(host->mmc), (unsigned)intmask);
  730. return;
  731. }
  732. if (intmask & S3C_HSMMC_INT_TIMEOUT)
  733. host->cmd->error = MMC_ERR_TIMEOUT;
  734. else if (intmask & S3C_HSMMC_INT_CRC)
  735. host->cmd->error = MMC_ERR_BADCRC;
  736. else if (intmask & (S3C_HSMMC_INT_END_BIT | S3C_HSMMC_INT_INDEX))
  737. host->cmd->error = MMC_ERR_FAILED;
  738. else
  739. host->cmd->error = MMC_ERR_INVALID;
  740. /* tasklet_schedule(&host->finish_tasklet); */
  741. s3c_hsmmc_tasklet_finish((unsigned long) host);
  742. }
  743. static void s3c_hsmmc_data_irq (struct s3c_hsmmc_host *host, u32 intmask)
  744. {
  745. if (!host->data) {
  746. /*
  747. * A data end interrupt is sent together with the response
  748. * for the stop command.
  749. */
  750. if (intmask & S3C_HSMMC_INT_DATA_END)
  751. return;
  752. printk(KERN_ERR "%s: Got data interrupt even though no "
  753. "data operation was in progress.\n",
  754. mmc_hostname(host->mmc));
  755. return;
  756. }
  757. if (intmask & S3C_HSMMC_INT_DATA_TIMEOUT)
  758. host->data->error = MMC_ERR_TIMEOUT;
  759. else if (intmask & S3C_HSMMC_INT_DATA_CRC)
  760. host->data->error = MMC_ERR_BADCRC;
  761. else if (intmask & S3C_HSMMC_INT_DATA_END_BIT)
  762. host->data->error = MMC_ERR_FAILED;
  763. if (host->data->error != MMC_ERR_NONE)
  764. s3c_hsmmc_finish_data(host);
  765. }
  766. /*****************************************************************************\
  767. * *
  768. * Interrupt handling *
  769. * *
  770. \*****************************************************************************/
  771. /*
  772. * ISR for SDI Interface IRQ
  773. * Communication between driver and ISR works as follows:
  774. * host->mrq points to current request
  775. * host->complete_what tells the ISR when the request is considered done
  776. *
  777. * 1) Driver sets up host->mrq and host->complete_what
  778. * 2) Driver prepares the transfer
  779. * 3) Driver enables interrupts
  780. * 4) Driver starts transfer
  781. * 5) Driver waits for host->complete_rquest
  782. * 6) ISR checks for request status (errors and success)
  783. * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
  784. * 7) ISR completes host->complete_request
  785. * 8) ISR disables interrupts
  786. * 9) Driver wakes up and takes care of the request
  787. */
  788. static irqreturn_t s3c_hsmmc_irq (int irq, void *dev_id)
  789. {
  790. irqreturn_t result = 0;
  791. struct s3c_hsmmc_host *host = dev_id;
  792. struct mmc_request *mrq;
  793. u32 intsts;
  794. #ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
  795. uint i, org_irq_sts;
  796. #endif
  797. spin_lock(&host->lock);
  798. mrq = host->mrq;
  799. intsts = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTS);
  800. /* Sometimes, hsmmc does not update its status bit immediately
  801. * when it generates irqs. by scsuh.
  802. */
  803. #ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
  804. for (i=0; i<0x1000; i++) {
  805. if ((intsts = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTS)))
  806. break;
  807. }
  808. #endif
  809. if (unlikely(!intsts)) {
  810. result = IRQ_NONE;
  811. goto out;
  812. }
  813. intsts = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTS);
  814. #ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
  815. org_irq_sts = intsts;
  816. #endif
  817. DBG("Got interrupt = 0x%08x\n", intsts);
  818. if (unlikely(intsts & S3C_HSMMC_INT_CARD_CHANGE)) {
  819. u32 reg16;
  820. if (intsts & S3C_HSMMC_INT_CARD_INSERT)
  821. printk(PFX "card inserted.\n");
  822. else if (intsts & S3C_HSMMC_INT_CARD_REMOVE)
  823. printk(PFX "card removed.\n");
  824. reg16 = s3c_hsmmc_readw(S3C_HSMMC_NORINTSTSEN);
  825. s3c_hsmmc_writew(reg16 & ~S3C_HSMMC_INT_CARD_CHANGE,
  826. S3C_HSMMC_NORINTSTSEN);
  827. s3c_hsmmc_writew(S3C_HSMMC_INT_CARD_CHANGE, S3C_HSMMC_NORINTSTS);
  828. s3c_hsmmc_writew(reg16, S3C_HSMMC_NORINTSTSEN);
  829. intsts &= ~S3C_HSMMC_INT_CARD_CHANGE;
  830. tasklet_schedule(&host->card_tasklet);
  831. goto insert;
  832. }
  833. if (likely(!(intsts & S3C_HSMMC_NIS_ERR))) {
  834. s3c_hsmmc_writel(intsts, S3C_HSMMC_NORINTSTS);
  835. if (intsts & S3C_HSMMC_NIS_CMDCMP) {
  836. DBG("command done\n");
  837. s3c_hsmmc_finish_command(host);
  838. }
  839. if (intsts & S3C_HSMMC_NIS_TRSCMP) {
  840. DBG("transfer done\n\n");
  841. s3c_hsmmc_finish_command(host);
  842. s3c_hsmmc_finish_data(host);
  843. intsts &= ~S3C_HSMMC_NIS_DMA;
  844. }
  845. #ifdef CONFIG_HSMMC_SCATTERGATHER
  846. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
  847. if (intsts & S3C_HSMMC_NIS_DMA) {
  848. struct s3c_hsmmc_dma_blk *dblk;
  849. dblk = &host->dblk[host->next_blk];
  850. if (dblk->original) {
  851. /* on read */
  852. if (host->dma_dir == DMA_FROM_DEVICE) {
  853. memcpy(dblk->original, phys_to_virt(dblk->dma_address), dblk->length);
  854. }
  855. dma_unmap_single(NULL, dblk->dma_address, dblk->length, host->dma_dir);
  856. dblk->original = 0;
  857. }
  858. host->next_blk++;
  859. dblk = &host->dblk[host->next_blk];
  860. if (host->next_blk == (host->dma_blk-1)) {
  861. u32 reg;
  862. reg = s3c_hsmmc_readl(S3C_HSMMC_NORINTSTSEN);
  863. reg &= ~S3C_HSMMC_NIS_DMA;
  864. s3c_hsmmc_writel(reg, S3C_HSMMC_NORINTSTSEN);
  865. }
  866. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  867. s3c_hsmmc_writew((dblk->boundary<<12 | 0x200), S3C_HSMMC_BLKSIZE);
  868. s3c_hsmmc_writel(dblk->dma_address, S3C_HSMMC_SYSAD);
  869. }
  870. #endif
  871. #endif
  872. } else {
  873. DBG("command FAIL : found bad irq [0x%8x]\n", intsts);
  874. DBG("\n");
  875. if (intsts & S3C_HSMMC_INT_CMD_MASK) {
  876. s3c_hsmmc_writel(intsts & S3C_HSMMC_INT_CMD_MASK, S3C_HSMMC_NORINTSTS);
  877. s3c_hsmmc_cmd_irq(host, intsts & S3C_HSMMC_INT_CMD_MASK);
  878. }
  879. if (intsts & S3C_HSMMC_INT_DATA_MASK) {
  880. s3c_hsmmc_writel(intsts & S3C_HSMMC_INT_DATA_MASK, S3C_HSMMC_NORINTSTS);
  881. s3c_hsmmc_finish_command(host);
  882. s3c_hsmmc_data_irq(host, intsts & S3C_HSMMC_INT_DATA_MASK);
  883. }
  884. intsts &= ~(S3C_HSMMC_INT_CMD_MASK | S3C_HSMMC_INT_DATA_MASK);
  885. }
  886. /* XXX: fix later by scsuh */
  887. #if 0
  888. if (intsts & S3C_HSMMC_INT_BUS_POWER) {
  889. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  890. mmc_hostname(host->mmc));
  891. s3c_hsmmc_writel(S3C_HSMMC_INT_BUS_POWER, S3C_HSMMC_NORINTSTS);
  892. }
  893. intsts &= S3C_HSMMC_INT_BUS_POWER;
  894. if (intsts) {
  895. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x.\n",
  896. mmc_hostname(host->mmc), intsts);
  897. s3c_hsmmc_writel(intsts, S3C_HSMMC_NORINTSTS);
  898. }
  899. #endif
  900. #ifdef CONFIG_HSMMC_S3C_IRQ_WORKAROUND
  901. for (i=0; i<0x1000; i++) {
  902. if (org_irq_sts != s3c_hsmmc_readl(S3C_HSMMC_NORINTSTS))
  903. break;
  904. }
  905. #endif
  906. insert:
  907. result = IRQ_HANDLED;
  908. mmiowb();
  909. out:
  910. spin_unlock(&host->lock);
  911. return result;
  912. }
  913. static irqreturn_t s3c_hsmmc_irq_cd (int irq, void *dev_id)
  914. {
  915. struct s3c_hsmmc_host *host = dev_id;
  916. int ext_CD_int = 0;
  917. CyEvent_t CyEvent = NEW_CYEVENT(CYEVENT_TYPE_SYSTEM);
  918. CyEvent.flags |= CYEVENT_FLAG_SD_MESSAGE;
  919. #if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  920. ext_CD_int = readl(S3C2410_GPFDAT);
  921. ext_CD_int &= 0x2; /* GPF1 */
  922. #elif defined(CONFIG_CPU_S3C6410)
  923. ext_CD_int = readl(S3C_GPNDAT);
  924. ext_CD_int &= 0x2000; /* GPN13 */
  925. #endif
  926. //printk("\ns3c_hsmmc_irq_cd, ext_CD_int: %d, card_detect: %d, card_detect2: %d\n", ext_CD_int, card_detect, card_detect2);
  927. if(ext_CD_int && card_detect)
  928. {
  929. printk("s3c-hsmmc channel-0(EXT): card removed.\n");
  930. /*Qisda Qube for sd card detect20091124*/
  931. //set_irq_type(host->irq_cd, IRQT_FALLING);
  932. set_irq_type(host->irq_cd, IRQT_LOW);
  933. /*Qisda Qube for sd card detect20091124*/
  934. card_detect = 0;
  935. //Qisda, Asaku Chen, 2009/11/03, SD power off
  936. s3c_hsmmc_power_switch(0, 0);
  937. card_detect2 = 2;
  938. /* Send CyIO event */
  939. /* SD OUT */
  940. CyEvent_PushNewUniqueEvent(&CyEvent);
  941. }
  942. else if(!ext_CD_int && !card_detect)
  943. {
  944. printk("s3c-hsmmc channel-0(EXT): card inserted.\n");
  945. /*Qisda Qube for sd card detect20091124*/
  946. //set_irq_type(host->irq_cd, IRQT_RISING);
  947. set_irq_type(host->irq_cd, IRQT_HIGH);
  948. /*Qisda Qube for sd card detect20091124*/
  949. //Qisda, Asaku Chen, 2009/11/03, SD power on
  950. if (inResume!=1)//howard, 2009/12/22, fix resume card-detect
  951. {
  952. card_detect = 1;
  953. s3c_hsmmc_power_switch(0, 1);
  954. }
  955. if(card_detect2 == 3){
  956. printk("resume host first\n");
  957. s3c_hsmmc_ios_init(host);
  958. mmc_resume_host(host->mmc);
  959. card_detect2 = 2;
  960. }
  961. /* Send CyIO event */
  962. /* SD IN */
  963. CyEvent.flags |= CYEVENT_FLAG_SYS_STATUS;
  964. CyEvent_PushNewUniqueEvent(&CyEvent);
  965. }
  966. //Qisda, Asaku Chen, 2009/11/03 {
  967. else if(card_detect2 == 1){
  968. printk("SD power on\n");
  969. s3c_hsmmc_power_switch(0, 1);
  970. card_detect2 = 2;
  971. }
  972. else if(card_detect2 == 0){
  973. printk("SD power off\n");
  974. s3c_hsmmc_power_switch(0, 0);
  975. card_detect2 = -1;
  976. }
  977. //Qisda, Asaku Chen, 2009/11/03 }
  978. else
  979. return IRQ_HANDLED;
  980. tasklet_schedule(&host->card_tasklet);
  981. mmiowb();
  982. spin_unlock(&host->lock);
  983. return IRQ_HANDLED;
  984. }
  985. static void s3c_hsmmc_check_status (unsigned long data)
  986. {
  987. struct s3c_hsmmc_host *host = (struct s3c_hsmmc_host *)data;
  988. s3c_hsmmc_irq(0, host);
  989. }
  990. static void s3c_hsmmc_request (struct mmc_host *mmc, struct mmc_request *mrq)
  991. {
  992. struct s3c_hsmmc_host *host = mmc_priv(mmc);
  993. unsigned long flags;
  994. DBG("hsmmc(%d) request: [CMD] opcode:%d arg:0x%08x flags:0x%02x retries:%u\n",
  995. host->plat_data->hwport,
  996. mrq->cmd->opcode, mrq->cmd->arg, mrq->cmd->flags, mrq->cmd->retries);
  997. spin_lock_irqsave(&host->lock, flags);
  998. WARN_ON(host->mrq != NULL);
  999. s3c_hsmmc_activate_led(host);
  1000. host->mrq = mrq;
  1001. if ((s3c_hsmmc_readl(S3C_HSMMC_PRNSTS) & S3C_HSMMC_CARD_PRESENT) || card_detect) {
  1002. s3c_hsmmc_send_command(host, mrq->cmd);
  1003. } else {
  1004. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  1005. /* tasklet_schedule(&host->finish_tasklet); */
  1006. s3c_hsmmc_tasklet_finish((unsigned long) host);
  1007. }
  1008. mmiowb();
  1009. spin_unlock_irqrestore(&host->lock, flags);
  1010. }
  1011. /* return 0: OK
  1012. * return -1: error
  1013. */
  1014. static int s3c_set_bus_width (struct s3c_hsmmc_host *host, uint width)
  1015. {
  1016. u8 reg;
  1017. reg = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
  1018. switch (width) {
  1019. case MMC_BUS_WIDTH_1:
  1020. reg &= ~(S3C_HSMMC_CTRL_4BIT | S3C_HSMMC_CTRL_8BIT);
  1021. DBG("bus width: 1 bit\n");
  1022. break;
  1023. case MMC_BUS_WIDTH_4:
  1024. DBG("bus width: 4 bit\n");
  1025. reg &= ~(S3C_HSMMC_CTRL_8BIT);
  1026. reg |= S3C_HSMMC_CTRL_4BIT;
  1027. break;
  1028. default:
  1029. DBG("bus width: Error\n");
  1030. return -1;
  1031. }
  1032. s3c_hsmmc_writeb(reg, S3C_HSMMC_HOSTCTL);
  1033. DBG("HOSTCTL(0x28) = 0x%02x\n", s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL));
  1034. return 0;
  1035. }
  1036. static void s3c_hsmmc_set_clock (struct s3c_hsmmc_host *host, ulong clock)
  1037. {
  1038. struct s3c_hsmmc_cfg *cfg = host->plat_data;
  1039. //int cardtype = host->mmc->mode;
  1040. int cardtype = MMC_MODE_MMC;
  1041. u32 val = 0, tmp_clk = 0, clk_src = 0, i, j;
  1042. u16 div = (u16)-1;
  1043. ulong timeout;
  1044. u8 ctrl;
  1045. /* if we already set, just out. */
  1046. if (clock == host->clock) {
  1047. printk("%p:host->clock0 : %d Hz\n", host->base, host->clock);
  1048. return;
  1049. }
  1050. /* before setting clock, clkcon must be disabled. */
  1051. s3c_hsmmc_writew(0, S3C_HSMMC_CLKCON);
  1052. s3c_hsmmc_writeb(S3C_HSMMC_TIMEOUT_MAX, S3C_HSMMC_TIMEOUTCON);
  1053. /* change the edge type according to frequency */
  1054. ctrl = s3c_hsmmc_readb(S3C_HSMMC_HOSTCTL);
  1055. if (cfg->highspeed)
  1056. ctrl |= S3C_HSMMC_CTRL_HIGHSPEED;
  1057. else
  1058. ctrl &= ~S3C_HSMMC_CTRL_HIGHSPEED;
  1059. s3c_hsmmc_writeb(ctrl, S3C_HSMMC_HOSTCTL);
  1060. if (clock == 0) {
  1061. DBG(" In case of 0 Hz of clock, I'm afraid DO NOTHING ..\n");
  1062. return;
  1063. }
  1064. /* calculate optimal clock. by scsuh */
  1065. DBG("Requested clock is %ld Hz\n", clock);
  1066. for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
  1067. if ((tmp_clk = clk_get_rate(host->clk[i])) <= clock) {
  1068. if (tmp_clk >= val) {
  1069. val = tmp_clk;
  1070. div = 0;
  1071. clk_src = i+1;
  1072. }
  1073. }
  1074. for (j=0x1; j<=0x80; j <<= 1) {
  1075. tmp_clk = clk_get_rate(host->clk[i]) / (j<<1);
  1076. if ((val < tmp_clk) && (tmp_clk <= clock)) {
  1077. val = tmp_clk;
  1078. div = j;
  1079. clk_src = i+1;
  1080. break;
  1081. }
  1082. }
  1083. DBG(" tmp_val[%d]: %d\n", i, val);
  1084. }
  1085. DBG("Optimal clock : %d Hz, div: 0x%x, SelBaseclk_src: %d\n", val, div, clk_src);
  1086. /* CONTROL2 */
  1087. s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl2 | (clk_src << 4), S3C_HSMMC_CONTROL2);
  1088. /* CONTROL3 */
  1089. if (clock > 25000000)
  1090. s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl3[SPEED_HIGH], S3C_HSMMC_CONTROL3);
  1091. else
  1092. s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl3[SPEED_NORMAL], S3C_HSMMC_CONTROL3);
  1093. #if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1094. s3c_hsmmc_writel(cfg->fd_ctrl[cardtype].ctrl4 << 16, S3C_HSMMC_CONTROL4);
  1095. #endif
  1096. s3c_hsmmc_writew(((div << 8) | S3C_HSMMC_CLOCK_INT_EN), S3C_HSMMC_CLKCON);
  1097. timeout = 10;
  1098. while (!((val = s3c_hsmmc_readw(S3C_HSMMC_CLKCON))
  1099. & S3C_HSMMC_CLOCK_INT_STABLE)) {
  1100. if (!timeout) {
  1101. printk("Error in INTERNAL clock stabilization: %08x\n", val);
  1102. return;
  1103. }
  1104. timeout--;
  1105. mdelay(1);
  1106. }
  1107. s3c_hsmmc_writew(val | S3C_HSMMC_CLOCK_CARD_EN, S3C_HSMMC_CLKCON);
  1108. timeout = 10;
  1109. while (!((val = s3c_hsmmc_readw(S3C_HSMMC_CLKCON))
  1110. & S3C_HSMMC_CLOCK_EXT_STABLE)) {
  1111. if (!timeout) {
  1112. printk("Error in EXTERNAL clock stabilization: %08x\n", val);
  1113. return;
  1114. }
  1115. timeout--;
  1116. mdelay(1);
  1117. }
  1118. }
  1119. static void s3c_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  1120. {
  1121. struct s3c_hsmmc_host *host = mmc_priv(mmc);
  1122. unsigned long iflags;
  1123. spin_lock_irqsave(&host->lock, iflags);
  1124. /*
  1125. * Reset the chip on each power off.
  1126. * Should clear out any weird states.
  1127. */
  1128. if (ios->power_mode == MMC_POWER_OFF) {
  1129. s3c_hsmmc_writew(0, S3C_HSMMC_NORINTSIGEN);
  1130. s3c_hsmmc_ios_init(host);
  1131. //Qisda, Asaku Chen, 2009/11/03 {
  1132. if(host->plat_data->hwport==0){
  1133. //printk("== s3c_hsmmc_set_ios: %d, MMC_POWER_OFF\n", host->plat_data->hwport);
  1134. s3c_hsmmc_power_switch(0, 0);
  1135. }
  1136. }
  1137. else{
  1138. //Enable SD power
  1139. if((host->plat_data->hwport==0) && (card_detect2 > 0)){
  1140. //printk("== s3c_hsmmc_set_ios: %d, MMC_POWER_ON\n", host->plat_data->hwport);
  1141. s3c_hsmmc_power_switch(0, 1);
  1142. }
  1143. }
  1144. if((ios->power_mode == MMC_POWER_OFF) && (host->plat_data->hwport==0)){
  1145. //do nothing
  1146. }else{
  1147. if (host->plat_data->enabled)
  1148. hsmmc_set_gpio(host->plat_data->hwport, host->plat_data->bus_width);
  1149. }
  1150. if((host->plat_data->hwport == 1) && (ios->clock > 26000000)){
  1151. ios->clock = 26000000;
  1152. }
  1153. DBG("ios->clock: %d Hz\n", ios->clock);
  1154. s3c_hsmmc_set_clock(host, ios->clock);
  1155. DBG("ios->bus_width: %d\n", ios->bus_width);
  1156. s3c_set_bus_width(host, ios->bus_width);
  1157. DBG("S3C_HSMMC_CONTROL2(0x80) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_CONTROL2));
  1158. DBG("S3C_HSMMC_CONTROL3(0x84) = 0x%08x\n", s3c_hsmmc_readl(S3C_HSMMC_CONTROL3));
  1159. DBG("S3C_HSMMC_CLKCON (0x2c) = 0x%04x\n", s3c_hsmmc_readw(S3C_HSMMC_CLKCON));
  1160. if (ios->power_mode == MMC_POWER_OFF)
  1161. s3c_hsmmc_writeb(S3C_HSMMC_POWER_OFF, S3C_HSMMC_PWRCON);
  1162. else
  1163. s3c_hsmmc_writeb(S3C_HSMMC_POWER_ON_ALL, S3C_HSMMC_PWRCON);
  1164. udelay(1000);
  1165. spin_unlock_irqrestore(&host->lock, iflags);
  1166. }
  1167. static struct mmc_host_ops s3c_hsmmc_ops = {
  1168. .request = s3c_hsmmc_request,
  1169. .set_ios = s3c_hsmmc_set_ios,
  1170. };
  1171. //Qisda, Asaku Chen, 2009/08/20, for wifi power {
  1172. static int s3c_wifi_open(struct inode *inode, struct file *file)
  1173. {
  1174. return 0;
  1175. }
  1176. #define S3C_WIFI_POWER_ON 1
  1177. #define S3C_WIFI_POWER_OFF 2
  1178. #define S3C_READ_TILT_STATUS 3
  1179. #define S3C_READ_GPIO_VALUE 4
  1180. #define S3C_SET_GPIO_ADDR 5
  1181. #define S3C_WRITE_GPIO_VALUE 6
  1182. #define S3C_READ_HW_VERSION 7
  1183. #define S3C_TCON_ERASE 10
  1184. #define S3C_TCON_ID 11
  1185. #define S3C_TCON_READ 12
  1186. #define S3C_TCON_BYTE_COUNT 13
  1187. #define S3C_TCON_WRITE 14
  1188. #define MMC_DEVICE_POWER_STATE 20
  1189. #define S3C_BT_POWER_ON 1
  1190. #define S3C_BT_POWER_OFF 2
  1191. static unsigned char s3c_tcon_read_byte(void)
  1192. {
  1193. /*
  1194. Unsigned char Get data () //Receive a byte from Serial flash
  1195. {
  1196. unsigned char k, temdata =0, i;
  1197. for ( k = 0; k++; k< 8)
  1198. {
  1199. if ( SO == 1 )
  1200. {
  1201. i = (0x80 >> k);
  1202. temdata = (temdata || i);
  1203. }
  1204. SCLK = 1;
  1205. SCLK = 0;
  1206. }
  1207. return (temdata);
  1208. }
  1209. */
  1210. unsigned char k, temdata =0, i=0;
  1211. u32 read_pin;
  1212. for(k=0; k<8; k++){
  1213. read_pin = (readl(S3C2410_GPEDAT) & (1<<11));
  1214. //printk(" [%d]: 0x%X 0x%X\n", k, read_pin, readl(S3C2410_GPEDAT));
  1215. if(read_pin){
  1216. i = (0x80 >> k);
  1217. temdata = (temdata | i);
  1218. }
  1219. s3c2410_gpio_setpin(S3C2410_GPE13, 1);
  1220. udelay(2);
  1221. s3c2410_gpio_setpin(S3C2410_GPE13, 0);
  1222. udelay(2);
  1223. }
  1224. //printk("s3c_tcon_read_byte: 0x%2X\n", temdata);
  1225. return (temdata);
  1226. }
  1227. static void s3c_tcon_write_byte(char w_data)
  1228. {
  1229. /*
  1230. Send data (unsigned char indata) // Send 1 byte data to Serial flash
  1231. {
  1232. unsigned char k;
  1233. for ( k = 0; k++; k< 8)
  1234. {
  1235. if( (indata & 0x80) == 0x80)
  1236. SI = 1;
  1237. else
  1238. SI = 0;
  1239. SCLK = 1;
  1240. SCLK = 0;
  1241. indata = (indata << 1);
  1242. }
  1243. }
  1244. */
  1245. unsigned char k;
  1246. //printk("s3c_tcon_write_byte: 0x%2X\n", w_data);
  1247. for(k=0; k<8; k++){
  1248. if((w_data & 0x80))
  1249. s3c2410_gpio_setpin(S3C2410_GPE12, 1);
  1250. else
  1251. s3c2410_gpio_setpin(S3C2410_GPE12, 0);
  1252. s3c2410_gpio_setpin(S3C2410_GPE13, 1);
  1253. udelay(2);
  1254. s3c2410_gpio_setpin(S3C2410_GPE13, 0);
  1255. udelay(2);
  1256. w_data = (w_data << 1);
  1257. }
  1258. }
  1259. extern void mmc_rescan(struct work_struct *work);
  1260. static int s3c_wifi_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1261. {
  1262. static char s3c_power_off = 0;
  1263. static unsigned int gpio_addr = 0;
  1264. static unsigned int tcon_byte_count;
  1265. static unsigned int tcon_address;
  1266. unsigned char tcon_buffer[128];
  1267. unsigned char r_data;
  1268. int ret, i;
  1269. u32 read_pin;
  1270. switch(cmd){
  1271. #ifdef CONFIG_QISDA_BK060B00
  1272. case S3C_WIFI_POWER_ON:
  1273. printk("BCM4329-WIFI_BT_POWER_ON\n");
  1274. //TCON Flash disable, and select WiFi
  1275. s3c2410_gpio_cfgpin(S3C2410_GPH6, S3C2410_GPH6_OUTP);
  1276. s3c2410_gpio_setpin(S3C2410_GPH6, 0);
  1277. //bcm4329 module power on control
  1278. //GPK7, WIFI PA 3.3V
  1279. writel(((readl(S3C2416_GPKCON) & ~(1<<15)) | (1<<14)), S3C2416_GPKCON);
  1280. writel((readl(S3C2416_GPKDAT) | (1<<7)), S3C2416_GPKDAT);
  1281. //GPK6, PA 1.8V
  1282. writel(((readl(S3C2416_GPKCON) & ~(1<<13)) | (1<<12)), S3C2416_GPKCON);
  1283. writel((readl(S3C2416_GPKDAT) | (1<<6)), S3C2416_GPKDAT);
  1284. //GPK5, PA 3.3V
  1285. writel(((readl(S3C2416_GPKCON) & ~(1<<11)) | (1<<10)), S3C2416_GPKCON);
  1286. writel((readl(S3C2416_GPKDAT) | (1<<5)), S3C2416_GPKDAT);
  1287. //GPK9 (green light), pull high
  1288. writel(((readl(S3C2416_GPKCON) & ~(1<<19)) | (1<<18)), S3C2416_GPKCON);
  1289. writel((readl(S3C2416_GPKDAT) | (1<<9)), S3C2416_GPKDAT);
  1290. //WIFI_BT_EN (GPD11) pull high
  1291. s3c2410_gpio_cfgpin(S3C2410_GPD11, S3C2410_GPD11_OUTP);
  1292. s3c2410_gpio_setpin(S3C2410_GPD11, 0);
  1293. //writel(((readl(S3C2416_GPGCON) & ~(1<<9)) | (1<<8)), S3C2416_GPGCON);
  1294. //writel((readl(S3C2416_GPGDAT) & ~(1<<4)), S3C2416_GPGDAT);
  1295. mdelay(1);
  1296. s3c2410_gpio_setpin(S3C2410_GPD11, 1);
  1297. //writel((readl(S3C2416_GPGDAT) | (1<<4)), S3C2416_GPGDAT);
  1298. mdelay(20);
  1299. //EXT_N_WIFI_RST (GPD8) pull high
  1300. s3c2410_gpio_cfgpin(S3C2410_GPD8, S3C2410_GPD8_OUTP);
  1301. s3c2410_gpio_setpin(S3C2410_GPD8, 0);
  1302. //writel(((readl(S3C2416_GPDCON) & ~(1<<17)) | (1<<16)), S3C2416_GPDCON);
  1303. //writel((readl(S3C2416_GPDDAT) & ~(1<<8)), S3C2416_GPDDAT);
  1304. mdelay(1);
  1305. s3c2410_gpio_setpin(S3C2410_GPD8, 1);
  1306. //writel((readl(S3C2416_GPDDAT) | (1<<8)), S3C2416_GPDDAT);
  1307. mdelay(20);
  1308. //EXT_N_BT_RST (GPA2) pull high
  1309. s3c2410_gpio_cfgpin(S3C2410_GPA2, S3C2410_GPA2_OUT);
  1310. s3c2410_gpio_setpin(S3C2410_GPA2, 0);
  1311. mdelay(1);
  1312. s3c2410_gpio_setpin(S3C2410_GPA2, 1);
  1313. mdelay(20);
  1314. //UART1 CTS1 (GPH10) set
  1315. s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPH10_CLKOUT1);
  1316. //writel(((readl(S3C2416_GPHCON) | (1<<21)) & ~ (1<<20)), S3C2416_GPHCON);
  1317. //writel(((readl(S3C2416_GPHUDP) & ~ (1<<21)) & ~ (1<<20)), S3C2416_GPHUDP);
  1318. //writel((readl(S3C2416_GPHDAT) & ~(1<<10)), S3C2416_GPHDAT);
  1319. mdelay(1);
  1320. //UART1 RTS1 (GPH11) set
  1321. s3c2410_gpio_cfgpin(S3C2410_GPH11, S3C2410_GPH11_nRTS);
  1322. //writel(((readl(S3C2416_GPHCON) | (1<<23)) & ~(1<<22)), S3C2416_GPHCON);
  1323. //writel((readl(S3C2416_GPHDAT) & ~(1<<11)), S3C2416_GPHDAT);
  1324. //writel(((readl(S3C2416_GPHUDP) & ~ (1<<23)) & ~ (1<<22)), S3C2416_GPHUDP);
  1325. mdelay(1);
  1326. break;
  1327. case S3C_WIFI_POWER_OFF:
  1328. printk("BCM4329-WIFI_POWER_OFF\n");
  1329. //TCON Flash disable, and select WiFi
  1330. s3c2410_gpio_cfgpin(S3C2410_GPH6, S3C2410_GPH6_OUTP);
  1331. s3c2410_gpio_setpin(S3C2410_GPH6, 0);
  1332. //bcm4329 module power off control
  1333. //EXT_N_WIFI_RST (GPD8) pull down
  1334. s3c2410_gpio_cfgpin(S3C2410_GPD8, S3C2410_GPD8_OUTP);
  1335. s3c2410_gpio_setpin(S3C2410_GPD8, 0);
  1336. //WIFI_BT_EN (GPD11) pull down
  1337. s3c2410_gpio_cfgpin(S3C2410_GPD11, S3C2410_GPD11_OUTP);
  1338. s3c2410_gpio_setpin(S3C2410_GPD11, 0);
  1339. //EXT_N_BT_RST (GPA2) pull down
  1340. s3c2410_gpio_cfgpin(S3C2410_GPA2, S3C2410_GPA2_OUT);
  1341. s3c2410_gpio_setpin(S3C2410_GPA2, 0);
  1342. mdelay(20);
  1343. //GPK9 (green light), pull down
  1344. writel(((readl(S3C2416_GPKCON) & ~(1<<19)) | (1<<18)), S3C2416_GPKCON);
  1345. writel((readl(S3C2416_GPKDAT) & ~(1<<9)), S3C2416_GPKDAT);
  1346. //GPK7, WIFI PA 3.3V
  1347. writel(((readl(S3C2416_GPKCON) & ~(1<<15)) | (1<<14)), S3C2416_GPKCON);
  1348. writel((readl(S3C2416_GPKDAT) & ~(1<<7)), S3C2416_GPKDAT);
  1349. //GPK6, PA 1.8V
  1350. writel(((readl(S3C2416_GPKCON) & ~(1<<13)) | (1<<12)), S3C2416_GPKCON);
  1351. writel((readl(S3C2416_GPKDAT) & ~(1<<6)), S3C2416_GPKDAT);
  1352. //GPK5, PA 3.3V
  1353. writel(((readl(S3C2416_GPKCON) & ~(1<<11)) | (1<<10)), S3C2416_GPKCON);
  1354. writel((readl(S3C2416_GPKDAT) & ~(1<<5)), S3C2416_GPKDAT);
  1355. break;
  1356. #else
  1357. case S3C_WIFI_POWER_ON:
  1358. printk("WIFI_POWER_ON\n");
  1359. //TCON Flash disable, and select WiFi
  1360. s3c2410_gpio_cfgpin(S3C2410_GPH6, S3C2410_GPH6_OUTP);
  1361. s3c2410_gpio_setpin(S3C2410_GPH6, 0);
  1362. //GPL13, SPI_CS
  1363. s3c2410_gpio_cfgpin(S3C2410_GPL13, S3C2410_GPL13_SS0);
  1364. //SPI DI
  1365. s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_SPIMISO0);
  1366. //SPI DO
  1367. s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_SPIMOSI0);
  1368. //SPI CLK
  1369. s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_SPICLK0);
  1370. //GPK6, PA 1.8V
  1371. writel(((readl(S3C2416_GPKCON) & ~(1<<13)) | (1<<12)), S3C2416_GPKCON);
  1372. writel((readl(S3C2416_GPKDAT) | (1<<6)), S3C2416_GPKDAT);
  1373. //GPK5, PA 3.3V
  1374. writel(((readl(S3C2416_GPKCON) & ~(1<<11)) | (1<<10)), S3C2416_GPKCON);
  1375. writel((readl(S3C2416_GPKDAT) | (1<<5)), S3C2416_GPKDAT);
  1376. //GPD8, RESET
  1377. s3c2410_gpio_cfgpin(S3C2410_GPD8, S3C2410_GPD8_OUTP);
  1378. s3c2410_gpio_setpin(S3C2410_GPD8, 0);
  1379. mdelay(1);
  1380. s3c2410_gpio_setpin(S3C2410_GPD8, 1);
  1381. mdelay(20);
  1382. break;
  1383. case S3C_WIFI_POWER_OFF:
  1384. printk("WIFI_POWER_OFF\n");
  1385. //TCON Flash disable, and select WiFi
  1386. s3c2410_gpio_cfgpin(S3C2410_GPH6, S3C2410_GPH6_OUTP);
  1387. s3c2410_gpio_setpin(S3C2410_GPH6, 0);
  1388. //GPK5, PA 3.3V
  1389. writel(((readl(S3C2416_GPKCON) & ~(1<<11)) | (1<<10)), S3C2416_GPKCON);
  1390. writel((readl(S3C2416_GPKDAT) & ~(1<<5)), S3C2416_GPKDAT);
  1391. //GPK6, PA 1.8V
  1392. writel(((readl(S3C2416_GPKCON) & ~(1<<13)) | (1<<12)), S3C2416_GPKCON);
  1393. writel((readl(S3C2416_GPKDAT) & ~(1<<6)), S3C2416_GPKDAT);
  1394. //GPD8, RESET
  1395. s3c2410_gpio_cfgpin(S3C2410_GPD8, S3C2410_GPD8_OUTP);
  1396. s3c2410_gpio_setpin(S3C2410_GPD8, 0);
  1397. //GPL13, SPI_CS
  1398. s3c2410_gpio_cfgpin(S3C2410_GPL13, S3C2410_GPL13_OUTP);
  1399. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1400. //SPI DI
  1401. s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_INP);
  1402. s3c2410_gpio_pullup(S3C2410_GPE11, 1);
  1403. //SPI DO
  1404. s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_INP);
  1405. s3c2410_gpio_pullup(S3C2410_GPE12, 1);
  1406. //SPI CLK
  1407. s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_INP);
  1408. s3c2410_gpio_pullup(S3C2410_GPE13, 1);
  1409. break;
  1410. #endif
  1411. case S3C_READ_TILT_STATUS:
  1412. if( ((readl(S3C2410_GPDDAT) & (0x3<<10)) >> 10) == 2){
  1413. return 270;
  1414. }
  1415. else if( ((readl(S3C2410_GPDDAT) & (0x3<<10)) >> 10) == 1){
  1416. return 90;
  1417. }
  1418. else if( ((readl(S3C2410_GPDDAT) & (0x3<<10)) >> 10) == 3){
  1419. return 180;
  1420. }
  1421. else{
  1422. return 0;
  1423. }
  1424. break;
  1425. case S3C_READ_GPIO_VALUE:
  1426. printk("S3C_READ_GPIO_VALUE\n");
  1427. printk("addr: 0x%x\n", arg+0x56000000);
  1428. arg = arg + S3C24XX_VA_GPIO;
  1429. printk("value: 0x%x\n", readl(arg));
  1430. break;
  1431. case S3C_SET_GPIO_ADDR:
  1432. printk("S3C_SET_GPIO_ADDR\n");
  1433. printk("set addr: 0x%x\n", arg + 0x56000000);
  1434. gpio_addr = arg + S3C24XX_VA_GPIO;
  1435. break;
  1436. case S3C_WRITE_GPIO_VALUE:
  1437. printk("S3C_WRITE_GPIO_VALUE\n");
  1438. printk("set addr: 0x%x, value: 0x%x\n", (gpio_addr-0xA0400000), arg);
  1439. writel(arg, gpio_addr);
  1440. break;
  1441. case MMC_DEVICE_POWER_STATE:
  1442. printk("MMC_DEVICE_POWER_STATE: %d\n", arg);
  1443. if(arg == 0){
  1444. card_detect2 = 1;
  1445. s3c_hsmmc_irq_cd (0, global_host[0]);
  1446. }
  1447. else if(arg == 3){
  1448. card_detect2 = 0;
  1449. s3c_hsmmc_irq_cd (0, global_host[0]);
  1450. }
  1451. else{
  1452. printk("no such state\n");
  1453. }
  1454. break;
  1455. case S3C_READ_HW_VERSION:
  1456. //printk("S3C_READ_HW_VERSION\n");
  1457. read_pin = readl(S3C2416_GPKDAT) & 0x1E;
  1458. //printk(" read_pin: 0x%x\n", read_pin);
  1459. ret = 0;
  1460. if((read_pin & (1<<4)))
  1461. ret = ret + 0x1000;
  1462. if((read_pin & (1<<3)))
  1463. ret = ret + 0x0100;
  1464. if((read_pin & (1<<2)))
  1465. ret = ret + 0x0010;
  1466. if((read_pin & (1<<1)))
  1467. ret = ret + 0x0001;
  1468. printk("Board ID: 0x%04x\n", ret);
  1469. return ret;
  1470. break;
  1471. case S3C_TCON_ERASE:
  1472. printk("S3C_TCON_ERASE\n");
  1473. //WiFi off
  1474. //GPK5, PA 3.3V off
  1475. writel(((readl(S3C2416_GPKCON) & ~(1<<11)) | (1<<10)), S3C2416_GPKCON);
  1476. writel((readl(S3C2416_GPKDAT) & ~(1<<5)), S3C2416_GPKDAT);
  1477. //GPK6, PA 1.8V
  1478. writel(((readl(S3C2416_GPKCON) & ~(1<<13)) | (1<<12)), S3C2416_GPKCON);
  1479. writel((readl(S3C2416_GPKDAT) & ~(1<<6)), S3C2416_GPKDAT);
  1480. //GPD8, RESET
  1481. s3c2410_gpio_cfgpin(S3C2410_GPD8, S3C2410_GPD8_OUTP);
  1482. s3c2410_gpio_setpin(S3C2410_GPD8, 0);
  1483. //GPH6, TCON_FLASH enable, and select TCON flash
  1484. s3c2410_gpio_cfgpin(S3C2410_GPH6, S3C2410_GPH6_OUTP);
  1485. s3c2410_gpio_setpin(S3C2410_GPH6, 1);
  1486. mdelay(200);
  1487. //Set GPIO for TCON update
  1488. //Chip Select
  1489. s3c2410_gpio_cfgpin(S3C2410_GPL13, S3C2410_GPL13_OUTP);
  1490. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1491. //GPE11 SPIMISO0
  1492. s3c2410_gpio_cfgpin(S3C2410_GPE11, S3C2410_GPE11_INP);
  1493. s3c2410_gpio_pullup(S3C2410_GPE11, 0);
  1494. //GPE12 SPIMOSI0
  1495. s3c2410_gpio_cfgpin(S3C2410_GPE12, S3C2410_GPE12_OUTP);
  1496. s3c2410_gpio_setpin(S3C2410_GPE12, 1);
  1497. //GPE13 SPI CLK
  1498. s3c2410_gpio_cfgpin(S3C2410_GPE13, S3C2410_GPE13_OUTP);
  1499. s3c2410_gpio_setpin(S3C2410_GPE13, 0);
  1500. msleep(50);
  1501. //Erase TCON Flash
  1502. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1503. udelay(50);
  1504. s3c_tcon_write_byte(0x06); //Setting Write Enable Latch bit
  1505. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1506. udelay(50);
  1507. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1508. udelay(50);
  1509. s3c_tcon_write_byte(0x60); //Write Chip Erase command
  1510. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1511. msleep(500);
  1512. do{
  1513. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1514. udelay(50);
  1515. s3c_tcon_write_byte(0x05); //Write Read Status command
  1516. r_data = s3c_tcon_read_byte();
  1517. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1518. //printk("r_data: 0x%02x\n", r_data);
  1519. msleep(500);
  1520. }while(r_data & 0x01);
  1521. tcon_byte_count = 0;
  1522. tcon_address = 0;
  1523. break;
  1524. case S3C_TCON_ID:
  1525. printk("S3C_TCON_ID: ");
  1526. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1527. udelay(50);
  1528. s3c_tcon_write_byte(0x9F);
  1529. r_data = s3c_tcon_read_byte();
  1530. printk("0x%02X ", r_data);
  1531. r_data = s3c_tcon_read_byte();
  1532. printk("0x%02X ", r_data);
  1533. r_data = s3c_tcon_read_byte();
  1534. printk("0x%02X\n", r_data);
  1535. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1536. break;
  1537. case S3C_TCON_READ:
  1538. printk("S3C_TCON_READ\n");
  1539. printk("\n\ns3c_tcon_read_content 1\n");
  1540. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1541. udelay(50);
  1542. s3c_tcon_write_byte(0x03);
  1543. s3c_tcon_write_byte(0x00);
  1544. s3c_tcon_write_byte(0x00);
  1545. s3c_tcon_write_byte(0x00);
  1546. for(i=0; i<300; i++){
  1547. printk("0x%02x\n", s3c_tcon_read_byte());
  1548. }
  1549. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1550. msleep(50);
  1551. printk("\n\ns3c_tcon_read_content 2\n");
  1552. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1553. udelay(50);
  1554. s3c_tcon_write_byte(0x03);
  1555. s3c_tcon_write_byte(0x02);
  1556. s3c_tcon_write_byte(0x0F);
  1557. s3c_tcon_write_byte(0xA0);
  1558. for(i=0; i<40; i++){
  1559. printk("0x%02x\n", s3c_tcon_read_byte());
  1560. }
  1561. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1562. break;
  1563. case S3C_TCON_BYTE_COUNT:
  1564. tcon_byte_count = arg;
  1565. //printk("S3C_TCON_BYTE_COUNT: %d\n", tcon_byte_count);
  1566. break;
  1567. case S3C_TCON_WRITE:
  1568. //printk("+ S3C_TCON_WRITE: %d\n ", tcon_address);
  1569. copy_from_user(tcon_buffer, arg, tcon_byte_count);
  1570. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1571. udelay(20);
  1572. s3c_tcon_write_byte(0x06); //Setting Write Enable Latch bit
  1573. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1574. udelay(20);
  1575. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1576. udelay(20);
  1577. //printk("0x%x 0x%x 0x%x\n", (tcon_address & 0xFF0000) >> 16, (tcon_address & 0xFF00) >> 8, (tcon_address & 0xFF));
  1578. s3c_tcon_write_byte(0x02); //Write Page Program command
  1579. s3c_tcon_write_byte( (tcon_address & 0xFF0000) >> 16 );
  1580. s3c_tcon_write_byte( (tcon_address & 0xFF00) >> 8 );
  1581. s3c_tcon_write_byte( (tcon_address & 0xFF) );
  1582. for(i=0; i<tcon_byte_count; i++){
  1583. //printk("0x%02X ", tcon_buffer[i]);
  1584. s3c_tcon_write_byte(tcon_buffer[i]);
  1585. }
  1586. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1587. udelay(400);
  1588. do{
  1589. s3c2410_gpio_setpin(S3C2410_GPL13, 0);
  1590. udelay(50);
  1591. s3c_tcon_write_byte(0x05); //Write Read Status command
  1592. r_data = s3c_tcon_read_byte();
  1593. s3c2410_gpio_setpin(S3C2410_GPL13, 1);
  1594. //printk("r_data: 0x%02x\n", r_data);
  1595. udelay(100);
  1596. }while(r_data & 0x01);
  1597. tcon_address = tcon_address + tcon_byte_count;
  1598. //printk("\n- S3C_TCON_WRITE: %d\n\n", tcon_address);
  1599. break;
  1600. default:
  1601. printk("no this command\n");
  1602. }
  1603. return 0;
  1604. }
  1605. #ifdef CONFIG_QISDA_BK060B00
  1606. static int s3c_bt_open(struct inode *inode, struct file *file);
  1607. static int s3c_bt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg);
  1608. /* File operations struct for character device */
  1609. static const struct file_operations s3c_bt_fops = {
  1610. .owner = THIS_MODULE,
  1611. .ioctl = s3c_bt_ioctl,
  1612. .open = s3c_bt_open,
  1613. .release = NULL
  1614. };
  1615. //Qisda, Ralph Chang, 2010/02/09, for bt power }
  1616. //Qisda, Ralph Chang, 2010/02/09, for bt power {
  1617. static int s3c_bt_open(struct inode *inode, struct file *file)
  1618. {
  1619. return 0;
  1620. }
  1621. static int s3c_bt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1622. {
  1623. switch(cmd){
  1624. case S3C_BT_POWER_ON:
  1625. printk("BCM4329-BT_POWER_ON\n");
  1626. //bcm4329 module power on control
  1627. //GPK7, WIFI PA 3.3V
  1628. writel(((readl(S3C2416_GPKCON) & ~(1<<15)) | (1<<14)), S3C2416_GPKCON);
  1629. writel((readl(S3C2416_GPKDAT) | (1<<7)), S3C2416_GPKDAT);
  1630. //GPK6, PA 1.8V
  1631. writel(((readl(S3C2416_GPKCON) & ~(1<<13)) | (1<<12)), S3C2416_GPKCON);
  1632. writel((readl(S3C2416_GPKDAT) | (1<<6)), S3C2416_GPKDAT);
  1633. //GPK5, PA 3.3V
  1634. writel(((readl(S3C2416_GPKCON) & ~(1<<11)) | (1<<10)), S3C2416_GPKCON);
  1635. writel((readl(S3C2416_GPKDAT) | (1<<5)), S3C2416_GPKDAT);
  1636. mdelay(1);
  1637. //GPL8 (blue light), pull high
  1638. //printk ("\n GPL8 (blue light), pull high\n");
  1639. //writel(((readl(S3C2416_GPLCON) & ~(1<<17)) | (1<<16)), S3C2416_GPLCON);
  1640. //writel((readl(S3C2416_GPLDAT) | (1<<8)), S3C2416_GPLDAT);
  1641. //writel(((readl(S3C2416_GPLUDP) | (1<<17)) & ~(1<<16)), S3C2416_GPLUDP); //pull up enable
  1642. //s3c2410_gpio_cfgpin(S3C2410_GPL8, S3C2410_GPL8_OUTP);
  1643. //s3c2410_gpio_setpin(S3C2410_GPL8, 1);
  1644. //s3c2410_gpio_pullup(S3C2410_GPL8, 1);
  1645. //WIFI_BT_EN (GPD11) pull high
  1646. s3c2410_gpio_cfgpin(S3C2410_GPD11, S3C2410_GPD11_OUTP);
  1647. s3c2410_gpio_setpin(S3C2410_GPD11, 0);
  1648. //writel(((readl(S3C2416_GPGCON) & ~(1<<9)) | (1<<8)), S3C2416_GPGCON);
  1649. //writel((readl(S3C2416_GPGDAT) & ~(1<<4)), S3C2416_GPGDAT);
  1650. mdelay(1);
  1651. s3c2410_gpio_setpin(S3C2410_GPD11, 1);
  1652. //writel((readl(S3C2416_GPGDAT) | (1<<4)), S3C2416_GPGDAT);
  1653. mdelay(20);
  1654. /*
  1655. printk("EXT_N_WIFI_RST (GPD8) set high\n");
  1656. //s3c2410_gpio_cfgpin(S3C2410_GPD8, S3C2410_GPD8_OUTP);
  1657. //s3c2410_gpio_setpin(S3C2410_GPD8, 0);
  1658. writel(((readl(S3C2416_GPDCON) & ~(1<<17)) | (1<<16)), S3C2416_GPDCON);
  1659. writel((readl(S3C2416_GPDDAT) & ~(1<<8)), S3C2416_GPDDAT);
  1660. mdelay(1);
  1661. //s3c2410_gpio_setpin(S3C2410_GPD8, 1);
  1662. writel((readl(S3C2416_GPDDAT) | (1<<8)), S3C2416_GPDDAT);
  1663. mdelay(20);
  1664. */
  1665. //EXT_N_BT_RST (GPA2) pull high
  1666. s3c2410_gpio_cfgpin(S3C2410_GPA2, S3C2410_GPA2_OUT);
  1667. s3c2410_gpio_setpin(S3C2410_GPA2, 0);
  1668. mdelay(1);
  1669. s3c2410_gpio_setpin(S3C2410_GPA2, 1);
  1670. mdelay(20);
  1671. //UART1 CTS1 (GPH10) set
  1672. s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPH10_CLKOUT1);
  1673. //writel(((readl(S3C2416_GPHCON) | (1<<21)) & ~ (1<<20)), S3C2416_GPHCON);
  1674. //writel(((readl(S3C2416_GPHUDP) & ~ (1<<21)) & ~ (1<<20)), S3C2416_GPHUDP);
  1675. //writel((readl(S3C2416_GPHDAT) & ~(1<<10)), S3C2416_GPHDAT);
  1676. mdelay(1);
  1677. //"UART1 RTS1 (GPH11) set
  1678. s3c2410_gpio_cfgpin(S3C2410_GPH11, S3C2410_GPH11_nRTS);
  1679. //writel(((readl(S3C2416_GPHCON) | (1<<23)) & ~(1<<22)), S3C2416_GPHCON);
  1680. //writel((readl(S3C2416_GPHDAT) & ~(1<<11)), S3C2416_GPHDAT);
  1681. //writel(((readl(S3C2416_GPHUDP) & ~ (1<<23)) & ~ (1<<22)), S3C2416_GPHUDP);
  1682. mdelay(1);
  1683. break;
  1684. case S3C_BT_POWER_OFF:
  1685. printk("BCM4329-BT_POWER_OFF\n");
  1686. //bcm4329 module power off control
  1687. //EXT_N_BT_RST (GPA2) pull down
  1688. s3c2410_gpio_cfgpin(S3C2410_GPA2, S3C2410_GPA2_OUT);
  1689. s3c2410_gpio_setpin(S3C2410_GPA2, 0);
  1690. mdelay(20);
  1691. //WIFI_BT_EN (GPD11) pull down
  1692. s3c2410_gpio_cfgpin(S3C2410_GPD11, S3C2410_GPD11_OUTP);
  1693. s3c2410_gpio_setpin(S3C2410_GPD11, 0);
  1694. //GPL8 (blue light), pull down
  1695. //writel(((readl(S3C2416_GPLCON) & ~(1<<17)) | (1<<16)), S3C2416_GPLCON);
  1696. //writel((readl(S3C2416_GPLDAT) & ~(1<<8)), S3C2416_GPLDAT);
  1697. //s3c2410_gpio_cfgpin(S3C2410_GPL8, S3C2410_GPL8_OUTP);
  1698. //s3c2410_gpio_setpin(S3C2410_GPL8, 0);
  1699. //GPK7, WIFI PA 3.3V
  1700. writel(((readl(S3C2416_GPKCON) & ~(1<<15)) | (1<<14)), S3C2416_GPKCON);
  1701. writel((readl(S3C2416_GPKDAT) & ~(1<<7)), S3C2416_GPKDAT);
  1702. //GPK6, PA 1.8V
  1703. writel(((readl(S3C2416_GPKCON) & ~(1<<13)) | (1<<12)), S3C2416_GPKCON);
  1704. writel((readl(S3C2416_GPKDAT) & ~(1<<6)), S3C2416_GPKDAT);
  1705. //GPK5, PA 3.3V
  1706. writel(((readl(S3C2416_GPKCON) & ~(1<<11)) | (1<<10)), S3C2416_GPKCON);
  1707. writel((readl(S3C2416_GPKDAT) & ~(1<<5)), S3C2416_GPKDAT);
  1708. break;
  1709. default:
  1710. printk("no this command\n");
  1711. }
  1712. return 0;
  1713. }
  1714. #endif
  1715. /* File operations struct for character device */
  1716. static const struct file_operations s3c_wifi_fops = {
  1717. .owner = THIS_MODULE,
  1718. .ioctl = s3c_wifi_ioctl,
  1719. .open = s3c_wifi_open,
  1720. .release = NULL
  1721. };
  1722. //Qisda, Asaku Chen, 2009/08/20, for wifi power }
  1723. static int s3c_hsmmc_probe (struct platform_device *pdev)
  1724. {
  1725. struct mmc_host *mmc;
  1726. struct s3c_hsmmc_host *host;
  1727. struct s3c_hsmmc_cfg *plat_data;
  1728. uint i;
  1729. int ret;
  1730. #if 0
  1731. unsigned long gpdat;
  1732. unsigned long gpcon;
  1733. /* Trevor Fix QISDA WIFIPMP SD_GPIO, Move to hsmmc_set_gpio*/
  1734. gpcon = __raw_readl(S3C_GPL1CON);
  1735. gpcon = (gpcon & ~(0xf<<12)) | (1<<12); // SD_GPIO(GPL11) Enable control
  1736. __raw_writel(gpcon, S3C_GPL1CON);
  1737. gpdat = __raw_readl(S3C_GPLDAT);
  1738. gpdat |= (1<<11);
  1739. __raw_writel(gpdat, S3C_GPLDAT);
  1740. #endif
  1741. mmc = mmc_alloc_host(sizeof(struct s3c_hsmmc_host), &pdev->dev);
  1742. if (!mmc)
  1743. ret = -ENOMEM;
  1744. plat_data = s3c_hsmmc_get_platdata(&pdev->dev);
  1745. //Qisda, Asaku Chen, 2009/08/20, for wifi power {
  1746. if(plat_data->hwport==1){
  1747. if (register_chrdev (S3C_WIFI_MAJOR, "s3c_wifi_cmd", &s3c_wifi_fops)) {
  1748. printk("unable to get major S3C_WIFI_MAJOR\n");
  1749. }
  1750. }
  1751. //Qisda, Asaku Chen, 2009/08/20, for wifi power }
  1752. #ifdef CONFIG_QISDA_BK060B00
  1753. //Qisda, Ralph Chang, 2010/02/09, for bt power {
  1754. if(plat_data->hwport==1){
  1755. if (register_chrdev (S3C_BT_MAJOR, "s3c_bt_cmd", &s3c_bt_fops)) {
  1756. printk("unable to get major S3C_BT_MAJOR\n");
  1757. }
  1758. }
  1759. //Qisda, Asaku Chen, 2009/08/20, for wifi power }
  1760. #endif
  1761. host = mmc_priv(mmc);
  1762. host->mmc = mmc;
  1763. host->plat_data = plat_data;
  1764. host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1765. if (!host->mem) {
  1766. printk("Failed to get io memory region resouce.\n");
  1767. ret = -ENOENT;
  1768. goto probe_free_host;
  1769. }
  1770. host->mem = request_mem_region(host->mem->start,
  1771. RESSIZE(host->mem), pdev->name);
  1772. if (!host->mem) {
  1773. printk("Failed to request io memory region.\n");
  1774. ret = -ENOENT;
  1775. goto probe_free_host;
  1776. }
  1777. host->base = ioremap(host->mem->start, (host->mem->end - host->mem->start)+1);
  1778. if (host->base == NULL) {
  1779. printk(KERN_ERR "Failed to remap register block\n");
  1780. return -ENOMEM;
  1781. }
  1782. host->irq = platform_get_irq(pdev, 0);
  1783. if (host->irq == 0) {
  1784. printk("Failed to get interrupt resouce.\n");
  1785. ret = -EINVAL;
  1786. goto untasklet;
  1787. }
  1788. DBG("platform_device(pdev): pdev(0x%p), name(%s)\n", pdev, pdev->name);
  1789. DBG("s3c_hsmmc_host(host): mem->start(0x%08x), base(0x%p), size(%d)\n", host->mem->start, host->base, RESSIZE(host->mem));
  1790. DBG("s3c_hsmmc_cfg(plat_data): enabled(%d) hwport(%d)\n", plat_data->enabled, plat_data->hwport);
  1791. /* To detect a card inserted on channel 0, an external interrupt is used. */
  1792. /* Qisda, howard hsu, 2010/01/21, SW_DEBOUNCE for sd card { */
  1793. #ifdef CONFIG_SD_SW_DEBOUNCE
  1794. if( plat_data->hwport == 0)
  1795. {
  1796. init_timer(&sd_detect_timer);
  1797. sd_detect_timer.function=sdcard_debounce_timer;
  1798. }
  1799. #endif /* CONFIG_SD_SW_DEBOUNCE */
  1800. /* } Qisda, howard hsu, 2010/01/21, SW_DEBOUNCE for sd card */
  1801. /* Qisda, howard hsu, 2010/01/21, fix start slot for SD card { */
  1802. if( plat_data->hwport == 0)
  1803. {
  1804. mmc->first_devidx = 1;
  1805. }
  1806. else
  1807. {
  1808. mmc->first_devidx = 0;
  1809. }
  1810. /* } Qisda, howard hsu, 2010/01/21, fix start slot for SD card */
  1811. if ((plat_data->enabled == 1) && (plat_data->hwport == 0)) {
  1812. host->irq_cd = platform_get_irq(pdev, 1);
  1813. if (host->irq_cd == 0) {
  1814. printk("Failed to get interrupt resouce.\n");
  1815. ret = -EINVAL;
  1816. goto untasklet;
  1817. }
  1818. #if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1819. set_irq_type(host->irq_cd, IRQT_BOTHEDGE);
  1820. #elif defined(CONFIG_CPU_S3C6410)
  1821. set_irq_type(host->irq_cd, IRQT_LOW);
  1822. #endif
  1823. }
  1824. host->flags |= S3C_HSMMC_USE_DMA;
  1825. #ifdef CONFIG_HSMMC_SCATTERGATHER
  1826. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
  1827. for (i=0; i<S3C_HSMMC_MAX_SUB_BUF; i++)
  1828. host->sub_block[i] = kmalloc(S3C_HSMMC_MALLOC_SIZE, GFP_KERNEL);
  1829. #endif
  1830. #endif
  1831. s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL);
  1832. /* register some clock sources if exist */
  1833. for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
  1834. host->clk[i] = clk_get(&pdev->dev, plat_data->clk_name[i]);
  1835. if (IS_ERR(host->clk[i])) {
  1836. ret = PTR_ERR(host->clk[i]);
  1837. host->clk[i] = ERR_PTR(-ENOENT);
  1838. }
  1839. if (clk_enable(host->clk[i])) {
  1840. host->clk[i] = ERR_PTR(-ENOENT);
  1841. }
  1842. if (!IS_ERR(host->clk[i])) {
  1843. DBG("MMC clock source[%d], %s is %ld Hz\n",i, plat_data->clk_name[i], clk_get_rate(host->clk[i]));
  1844. }
  1845. }
  1846. mmc->ops = &s3c_hsmmc_ops;
  1847. mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
  1848. mmc->f_min = 400 * 1000; /* at least 400kHz */
  1849. /* you must make sure that our hsmmc block can support
  1850. * up to 52MHz. by scsuh
  1851. */
  1852. //mmc->f_max = 100 * MHZ;
  1853. mmc->f_max = 25 * MHZ;
  1854. mmc->caps = plat_data->host_caps;
  1855. DBG("mmc->caps: %08lx\n", mmc->caps);
  1856. printk(KERN_INFO "mmc->caps: %08lx\n", mmc->caps);
  1857. spin_lock_init(&host->lock);
  1858. /*
  1859. * Maximum number of segments. Hardware cannot do scatter lists.
  1860. * XXX: must modify later. by scsuh
  1861. */
  1862. #ifdef CONFIG_HSMMC_SCATTERGATHER
  1863. mmc->max_hw_segs = CONFIG_S3C_HSMMC_MAX_HW_SEGS;
  1864. mmc->max_phys_segs = CONFIG_S3C_HSMMC_MAX_HW_SEGS;
  1865. #else
  1866. mmc->max_hw_segs = 1;
  1867. #endif
  1868. /*
  1869. * Maximum number of sectors in one transfer. Limited by DMA boundary
  1870. * size (512KiB), which means (512 KiB/512=) 1024 entries.
  1871. */
  1872. //mmc->max_sectors = 128; /* 65535/512=128 */
  1873. /*
  1874. * Maximum segment size. Could be one segment with the maximum number
  1875. * of sectors.
  1876. */
  1877. mmc->max_blk_size = 512;
  1878. mmc->max_seg_size = 128 * mmc->max_blk_size;
  1879. mmc->max_blk_count = 128;
  1880. mmc->max_req_size = mmc->max_seg_size;
  1881. init_timer(&host->timer);
  1882. host->timer.data = (unsigned long)host;
  1883. host->timer.function = s3c_hsmmc_check_status;
  1884. host->timer.expires = jiffies + HZ;
  1885. /*
  1886. * Init tasklets.
  1887. */
  1888. tasklet_init(&host->card_tasklet,
  1889. s3c_hsmmc_tasklet_card, (unsigned long)host);
  1890. #if 0
  1891. tasklet_init(&host->finish_tasklet,
  1892. s3c_hsmmc_tasklet_finish, (unsigned long)host);
  1893. #endif
  1894. ret = request_irq(host->irq, s3c_hsmmc_irq, 0, DRIVER_NAME, host);
  1895. if (ret)
  1896. goto untasklet;
  1897. #if defined(CONFIG_CPU_S3C6410) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1898. if ((plat_data->enabled == 1) && (plat_data->hwport == 0)) {
  1899. ret = request_irq(host->irq_cd, s3c_hsmmc_irq_cd, 0, DRIVER_NAME, host);
  1900. if (ret)
  1901. goto untasklet;
  1902. enable_irq_wake(host->irq_cd);
  1903. }
  1904. #endif
  1905. s3c_hsmmc_ios_init(host);
  1906. DBG("before mmc_add_host()\n");
  1907. mmc_add_host(mmc);
  1908. DBG("after mmc_add_host()\n");
  1909. #if defined(CONFIG_PM)
  1910. global_host[plat_data->hwport] = host;
  1911. #endif
  1912. printk(KERN_INFO "[s3c_hsmmc_probe]: %s.%d: at 0x%p with irq %d. clk src:",
  1913. pdev->name, pdev->id, host->base, host->irq);
  1914. for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
  1915. if (!IS_ERR(host->clk[i]))
  1916. printk(" %s", host->clk[i]->name);
  1917. }
  1918. printk("\n");
  1919. return 0;
  1920. untasklet:
  1921. tasklet_kill(&host->card_tasklet);
  1922. /* tasklet_kill(&host->finish_tasklet); */
  1923. for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
  1924. if (host->clk[i] != ERR_PTR(-ENOENT)) {
  1925. clk_disable(host->clk[i]);
  1926. clk_put(host->clk[i]);
  1927. }
  1928. }
  1929. probe_free_host:
  1930. mmc_free_host(mmc);
  1931. return ret;
  1932. }
  1933. static int s3c_hsmmc_remove(struct platform_device *dev)
  1934. {
  1935. struct mmc_host *mmc = platform_get_drvdata(dev);
  1936. struct s3c_hsmmc_host *host = mmc_priv(mmc);
  1937. int i;
  1938. mmc = host->mmc;
  1939. mmc_remove_host(mmc);
  1940. s3c_hsmmc_reset(host, S3C_HSMMC_RESET_ALL);
  1941. for (i=0; i<NUM_OF_HSMMC_CLKSOURCES; i++) {
  1942. clk_disable(host->clk[i]);
  1943. clk_put(host->clk[i]);
  1944. }
  1945. free_irq(host->irq, host);
  1946. del_timer_sync(&host->timer);
  1947. tasklet_kill(&host->card_tasklet);
  1948. /* tasklet_kill(&host->finish_tasklet); */
  1949. #ifdef CONFIG_HSMMC_SCATTERGATHER
  1950. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C2443)
  1951. kfree(host->sub_block);
  1952. #endif
  1953. #endif
  1954. mmc_free_host(mmc);
  1955. return 0;
  1956. }
  1957. #ifdef CONFIG_PM
  1958. static int s3c_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
  1959. {
  1960. // struct mmc_card *card;
  1961. struct s3c_hsmmc_host *s3c_host = global_host[pdev->id];
  1962. struct mmc_host *host = s3c_host->mmc;
  1963. #if 0
  1964. /*
  1965. * Fix me later by jsgood
  1966. */
  1967. list_for_each_entry(card, &host->cards, node) {
  1968. if (card->state & MMC_STATE_PRESENT)
  1969. card->state &= ~MMC_STATE_PRESENT;
  1970. }
  1971. #endif
  1972. //USB20_EN
  1973. //writel((readl(S3C2410_GPHCON) & ~(1<<29) | 1<<28), S3C2410_GPHCON);
  1974. //writel((readl(S3C2410_GPHDAT) &~(1<<14)), S3C2410_GPHDAT);
  1975. if(((readl(S3C2410_GPGDAT) &(1<<1))==0)&&((readl(S3C2410_GPHDAT) &(1<<11))==0))
  1976. {
  1977. //if((readl(S3C2410_GPHDAT) &(1<<11))==0)
  1978. {
  1979. printk("\nUSB_UDC_DEVICE_s3c_hsmmc_suspend: usb\n");
  1980. // writel((readl(S3C2410_GPHCON) & ~(1<<29) | (1<<28)), S3C2410_GPHCON);
  1981. s3c2410_gpio_pullup(S3C2443_GPH14,1);
  1982. s3c2410_gpio_cfgpin(S3C2443_GPH14, S3C2443_GPH14_OUTP);
  1983. s3c2410_gpio_setpin(S3C2443_GPH14, 0); /* usb power enbale */
  1984. s3c2410_gpio_pullup(S3C2410_GPD13,1);
  1985. s3c2410_gpio_cfgpin(S3C2410_GPD13, S3C2410_GPD13_INP);
  1986. }
  1987. }
  1988. if((readl(S3C2410_GPHDAT) &(1<<11))==0)
  1989. {
  1990. printk("\nUSB_UDC_DEVICE_s3c_hsmmc_suspend: 3g\n");
  1991. s3c2410_gpio_pullup(S3C2410_GPH11,1);
  1992. s3c2410_gpio_cfgpin(S3C2410_GPH11, S3C2410_GPH11_OUTP);
  1993. s3c2410_gpio_setpin(S3C2410_GPH11, 0); /* usb power enbale */
  1994. s3c2410_gpio_pullup(S3C2410_GPH8,1);
  1995. s3c2410_gpio_cfgpin(S3C2410_GPH8, S3C2410_GPH8_OUTP);
  1996. s3c2410_gpio_setpin(S3C2410_GPH8, 0); /* usb power enbale */
  1997. s3c2410_gpio_cfgpin(S3C2410_GPH8, S3C2410_GPH9_OUTP);
  1998. s3c2410_gpio_setpin(S3C2410_GPH9, 0); /* usb power enbale */
  1999. // s3c2410_gpio_pullup(S3C2410_GPG3,1);
  2000. // s3c2410_gpio_cfgpin(S3C2410_GPG3, S3C2410_GPG3_OUTP);
  2001. // s3c2410_gpio_setpin(S3C2410_GPG3, 0); /* usb power enbale */
  2002. }
  2003. mmc_suspend_host(host, state);
  2004. //mmc suspend GPIO config
  2005. s3c_hsmmc_power_switch(s3c_host->plat_data->hwport, 0);
  2006. /* Qisda, Howard, 2009/12/22, fix resume card-detect { */
  2007. if(s3c_host->plat_data->hwport==0)
  2008. {
  2009. inResume = 1;
  2010. card_detect2 = 2;
  2011. }
  2012. /* } Qisda, Howard, 2009/12/22, fix resume card-detect */
  2013. return 0;
  2014. }
  2015. static int s3c_hsmmc_resume(struct platform_device *pdev)
  2016. {
  2017. struct s3c_hsmmc_host *s3c_host = global_host[pdev->id];
  2018. struct mmc_host *host = s3c_host->mmc;
  2019. int read_pin;
  2020. //USB20_EN
  2021. //writel((readl(S3C2410_GPHCON) & ~(1<<29) | 1<<28), S3C2410_GPHCON);
  2022. //writel((readl(S3C2410_GPHDAT) |(1<<14)), S3C2410_GPHDAT);
  2023. if((readl(S3C2410_GPGDAT) &(1<<1))!=0)
  2024. {
  2025. printk("\nUSB_UDC_DEVICE_POWER_STATE: %d\n");
  2026. writel((readl(S3C2410_GPHCON) & ~(1<<29) | 1<<28), S3C2410_GPHCON);
  2027. s3c2410_gpio_pullup(S3C2443_GPH14,2);
  2028. s3c2410_gpio_cfgpin(S3C2443_GPH14,S3C2443_GPH14_OUTP);
  2029. s3c2410_gpio_setpin(S3C2443_GPH14,1); /* usb power enbale */
  2030. }
  2031. //PWREN_SD
  2032. if(s3c_host->plat_data->hwport==0){
  2033. read_pin = readl(S3C2410_GPFDAT) & (1<<1);
  2034. if(read_pin && !card_detect){
  2035. printk("\nNO CARD\n");
  2036. s3c_hsmmc_power_switch(0, 0);
  2037. /* Qisda, Howard Hsu, 2009/12/17, card detect by level-trigger { */
  2038. //set_irq_type(s3c_host->irq_cd, IRQT_FALLING);
  2039. set_irq_type(s3c_host->irq_cd, IRQT_LOW);
  2040. /* } Qisda, Howard Hsu, 2009/12/17, card detect by level-trigger */
  2041. card_detect2 = 3;
  2042. }
  2043. else{
  2044. if(read_pin){
  2045. printk("no card\n");
  2046. /* Qisda, Howard Hsu, 2009/12/17, card detect by level-trigger { */
  2047. //set_irq_type(s3c_host->irq_cd, IRQT_FALLING);
  2048. set_irq_type(s3c_host->irq_cd, IRQT_LOW);
  2049. /* } Qisda, Howard Hsu, 2009/12/17, card detect by level-trigger */
  2050. card_detect = 0;
  2051. //s3c_hsmmc_power_switch(0, 0);
  2052. }
  2053. else{
  2054. printk("card in\n");
  2055. /* Qisda, Howard Hsu, 2009/12/17, card detect by level-trigger { */
  2056. //set_irq_type(s3c_host->irq_cd, IRQT_RISING);
  2057. set_irq_type(s3c_host->irq_cd, IRQT_HIGH);
  2058. /* } Qisda, Howard Hsu, 2009/12/17, card detect by level-trigger */
  2059. card_detect = 1;
  2060. //s3c_hsmmc_power_switch(0, 1);
  2061. }
  2062. card_detect2 = 2;
  2063. s3c_hsmmc_power_switch(0, 1);
  2064. s3c_hsmmc_ios_init(s3c_host);
  2065. mmc_resume_host(host);
  2066. }
  2067. inResume = 0; //howard, 2009/12/22, fix resume card-detect
  2068. }
  2069. else if(s3c_host->plat_data->hwport==1){
  2070. s3c_hsmmc_power_switch(1, 1);
  2071. s3c_hsmmc_ios_init(s3c_host);
  2072. mmc_resume_host(host);
  2073. }
  2074. #if 0
  2075. /* Qisda, Daniel Lee, 2009/07/23, e600 { */
  2076. // For EVT0
  2077. // Set MMC insert/remove irq back.
  2078. if(card_detect)
  2079. set_irq_type(s3c_host->irq_cd, IRQT_RISING);
  2080. else
  2081. set_irq_type(s3c_host->irq_cd, IRQT_FALLING);
  2082. /* Qisda, Daniel Lee, 2009/07/23, e600 } */
  2083. #endif
  2084. /*}Qisda,2009/7/28,Leo SJ Yang*/
  2085. //s3c_hsmmc_ios_init(s3c_host);
  2086. //mmc_resume_host(host);
  2087. /*Qisda,2009/7/28,Leo SJ Yang {*/
  2088. /* Add SD Card,WIFI,USB power management*/
  2089. if(s3c_host->plat_data->hwport==0)
  2090. {
  2091. //card_detect=1;
  2092. }
  2093. /*}Qisda,2009/7/28,Leo SJ Yang*/
  2094. return 0;
  2095. }
  2096. #else
  2097. #define s3c_hsmmc_suspend NULL
  2098. #define s3c_hsmmc_resume NULL
  2099. #endif
  2100. static struct platform_driver s3c_hsmmc_driver =
  2101. {
  2102. .probe = s3c_hsmmc_probe,
  2103. .remove = s3c_hsmmc_remove,
  2104. .suspend = s3c_hsmmc_suspend,
  2105. .resume = s3c_hsmmc_resume,
  2106. .driver = {
  2107. .name = "s3c-hsmmc",
  2108. .owner = THIS_MODULE,
  2109. },
  2110. };
  2111. static int __init s3c_hsmmc_drv_init(void)
  2112. {
  2113. //Disable SD power
  2114. s3c_hsmmc_power_switch(0, 0);
  2115. /*Qisda,2009/7/28,Leo SJ Yang{*/
  2116. //s3c2410_gpio_cfgpin(S3C2410_GPF1,S3C2410_GPF1_EINT1);
  2117. s3c2410_gpio_cfgpin(S3C2410_GPF1,S3C2410_GPF1_INP);
  2118. s3c2410_gpio_pullup(S3C2410_GPF1, 2);
  2119. /*}Qisda,2009/7/28,Leo SJ Yang*/
  2120. return platform_driver_register(&s3c_hsmmc_driver);
  2121. }
  2122. static void __exit s3c_hsmmc_drv_exit(void)
  2123. {
  2124. platform_driver_unregister(&s3c_hsmmc_driver);
  2125. }
  2126. void s3c_moviNAND_power_off(void)
  2127. {
  2128. struct s3c_hsmmc_host *host = global_host[1];
  2129. printk("s3c_moviNAND_power_off");
  2130. s3c_hsmmc_writeb(S3C_HSMMC_POWER_OFF, S3C_HSMMC_PWRCON);
  2131. }
  2132. module_init(s3c_hsmmc_drv_init);
  2133. module_exit(s3c_hsmmc_drv_exit);
  2134. MODULE_DESCRIPTION("S3C SD HOST I/F 1.0 and 2.0 Driver");
  2135. MODULE_LICENSE("GPL");