time.c 8.2 KB

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  1. /* linux/arch/arm/plat-s3c24xx/time.c
  2. *
  3. * Copyright (C) 2003-2005 Simtec Electronics
  4. * Ben Dooks, <ben@simtec.co.uk>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. */
  20. #include <linux/kernel.h>
  21. #include <linux/sched.h>
  22. #include <linux/init.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/irq.h>
  25. #include <linux/err.h>
  26. #include <linux/clk.h>
  27. #include <asm/system.h>
  28. #include <asm/leds.h>
  29. #include <asm/mach-types.h>
  30. #include <asm/io.h>
  31. #include <asm/irq.h>
  32. #include <asm/arch/map.h>
  33. #include <asm/arch/regs-timer.h>
  34. #include <asm/arch/regs-irq.h>
  35. #include <asm/mach/time.h>
  36. #include <asm/plat-s3c24xx/clock.h>
  37. #include <asm/plat-s3c24xx/cpu.h>
  38. #include <asm/plat-s3c24xx/s3c2450.h>
  39. #include <asm/arch/regs-gpio.h>
  40. static unsigned long timer_startval;
  41. static unsigned long timer_usec_ticks;
  42. static unsigned long max_buffer_cnt;
  43. #define TIMER_USEC_SHIFT 16
  44. #define OS_TIMER_Nr 4
  45. /* we use the shifted arithmetic to work out the ratio of timer ticks
  46. * to usecs, as often the peripheral clock is not a nice even multiple
  47. * of 1MHz.
  48. *
  49. * shift of 14 and 15 are too low for the 12MHz, 16 seems to be ok
  50. * for the current HZ value of 200 without producing overflows.
  51. *
  52. * Original patch by Dimitry Andric, updated by Ben Dooks
  53. */
  54. /* timer_mask_usec_ticks
  55. *
  56. * given a clock and divisor, make the value to pass into timer_ticks_to_usec
  57. * to scale the ticks into usecs
  58. */
  59. static inline unsigned long
  60. timer_mask_usec_ticks(unsigned long scaler, unsigned long pclk)
  61. {
  62. unsigned long den = pclk / 1000;
  63. return ((1000 << TIMER_USEC_SHIFT) * scaler + (den >> 1)) / den;
  64. }
  65. /* timer_ticks_to_usec
  66. *
  67. * convert timer ticks to usec.
  68. */
  69. static inline unsigned long timer_ticks_to_usec(unsigned long ticks)
  70. {
  71. unsigned long res;
  72. res = ticks * timer_usec_ticks;
  73. res += 1 << (TIMER_USEC_SHIFT - 4); /* round up slightly */
  74. return res >> TIMER_USEC_SHIFT;
  75. }
  76. /***
  77. * Returns microsecond since last clock interrupt. Note that interrupts
  78. * will have been disabled by do_gettimeoffset()
  79. * IRQs are disabled before entering here from do_gettimeofday()
  80. */
  81. #define SRCPND_TIMER4 (1<<(IRQ_TIMER4 - IRQ_EINT0))
  82. static unsigned long s3c2410_gettimeoffset (void)
  83. {
  84. unsigned long tdone;
  85. unsigned long irqpend;
  86. unsigned long tval;
  87. /* work out how many ticks have gone since last timer interrupt */
  88. tval = __raw_readl(S3C2410_TCNTO(4));
  89. tdone = timer_startval - tval;
  90. /* check to see if there is an interrupt pending */
  91. irqpend = __raw_readl(S3C2410_SRCPND);
  92. if (irqpend & SRCPND_TIMER4) {
  93. /* re-read the timer, and try and fix up for the missed
  94. * interrupt. Note, the interrupt may go off before the
  95. * timer has re-loaded from wrapping.
  96. */
  97. tval = __raw_readl(S3C2410_TCNTO(4));
  98. tdone = timer_startval - tval;
  99. if (tval != 0)
  100. tdone += timer_startval;
  101. }
  102. return timer_ticks_to_usec(tdone);
  103. }
  104. #ifdef CONFIG_NO_IDLE_HZ
  105. static unsigned long initial_match;
  106. static int match_posponed;
  107. #endif
  108. /*
  109. * IRQ handler for the timer
  110. */
  111. static irqreturn_t
  112. s3c2410_timer_interrupt(int irq, void *dev_id)
  113. {
  114. write_seqlock(&xtime_lock);
  115. #ifdef CONFIG_NO_IDLE_HZ
  116. if (match_posponed) {
  117. match_posponed = 0;
  118. __raw_writel(initial_match,S3C2410_TCNTB(OS_TIMER_Nr));
  119. }
  120. #endif
  121. timer_tick();
  122. write_sequnlock(&xtime_lock);
  123. return IRQ_HANDLED;
  124. }
  125. static struct irqaction s3c2410_timer_irq = {
  126. .name = "S3C2410 Timer Tick",
  127. .flags = IRQF_DISABLED | IRQF_TIMER,
  128. .handler = s3c2410_timer_interrupt,
  129. };
  130. #define use_tclk1_12() ( \
  131. machine_is_bast() || \
  132. machine_is_vr1000() || \
  133. machine_is_anubis() || \
  134. machine_is_osiris() )
  135. /*
  136. * Set up timer interrupt, and return the current time in seconds.
  137. *
  138. * Currently we only use timer4, as it is the only timer which has no
  139. * other function that can be exploited externally
  140. */
  141. static void s3c2410_timer_setup (void)
  142. {
  143. unsigned long tcon;
  144. unsigned long tcnt;
  145. unsigned long tcfg1;
  146. unsigned long tcfg0;
  147. tcnt = 0xffff; /* default value for tcnt */
  148. /* read the current timer configuration bits */
  149. tcon = __raw_readl(S3C2410_TCON);
  150. tcfg1 = __raw_readl(S3C2410_TCFG1);
  151. tcfg0 = __raw_readl(S3C2410_TCFG0);
  152. /* configure the system for whichever machine is in use */
  153. if (use_tclk1_12()) {
  154. /* timer is at 12MHz, scaler is 1 */
  155. timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
  156. tcnt = 12000000 / HZ;
  157. tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
  158. tcfg1 |= S3C2410_TCFG1_MUX4_TCLK1;
  159. } else {
  160. unsigned long pclk;
  161. struct clk *clk;
  162. /* for the h1940 (and others), we use the pclk from the core
  163. * to generate the timer values. since values around 50 to
  164. * 70MHz are not values we can directly generate the timer
  165. * value from, we need to pre-scale and divide before using it.
  166. *
  167. * for instance, using 50.7MHz and dividing by 6 gives 8.45MHz
  168. * (8.45 ticks per usec)
  169. */
  170. /* this is used as default if no other timer can be found */
  171. clk = clk_get(NULL, "timers");
  172. if (IS_ERR(clk))
  173. panic("failed to get clock for system timer");
  174. clk_enable(clk);
  175. pclk = clk_get_rate(clk);
  176. /* configure clock tick */
  177. timer_usec_ticks = timer_mask_usec_ticks(PRESCALE*MUX4_VAL, pclk);
  178. tcfg1 &= ~S3C2410_TCFG1_MUX4_MASK;
  179. tcfg1 |= MUX4_DIV;
  180. /* when 66MHz PCLK, */
  181. tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
  182. tcfg0 |= (PRESCALE - 1) << S3C2410_TCFG_PRESCALER1_SHIFT;
  183. tcnt = (pclk/PRESCALE/MUX4_VAL) / HZ;
  184. max_buffer_cnt = (unsigned long)(0xffff/LATCH) ;
  185. }
  186. /* timers reload after counting zero, so reduce the count by 1 */
  187. tcnt--;
  188. printk("timer tcon=%08lx, tcnt %04lx, tcfg %08lx,%08lx, usec %08lx\n",
  189. tcon, tcnt, tcfg0, tcfg1, timer_usec_ticks);
  190. /* check to see if timer is within 16bit range... */
  191. if (tcnt > 0xffff) {
  192. panic("setup_timer: HZ is too small, cannot configure timer!");
  193. return;
  194. }
  195. __raw_writel(tcfg1, S3C2410_TCFG1);
  196. __raw_writel(tcfg0, S3C2410_TCFG0);
  197. timer_startval = tcnt;
  198. __raw_writel(tcnt, S3C2410_TCNTB(4));
  199. /* ensure timer is stopped... */
  200. tcon &= ~(7<<20);
  201. tcon |= S3C2410_TCON_T4RELOAD;
  202. tcon |= S3C2410_TCON_T4MANUALUPD;
  203. __raw_writel(tcon, S3C2410_TCON);
  204. __raw_writel(tcnt, S3C2410_TCNTB(4));
  205. __raw_writel(tcnt, S3C2410_TCMPB(4));
  206. /* start the timer running */
  207. tcon |= S3C2410_TCON_T4START;
  208. tcon &= ~S3C2410_TCON_T4MANUALUPD;
  209. __raw_writel(tcon, S3C2410_TCON);
  210. }
  211. #ifdef CONFIG_NO_IDLE_HZ
  212. static int s3c2410_dyn_tick_enable_disable(void)
  213. {
  214. /* nothing to do */
  215. return 0;
  216. }
  217. static void s3c2410_dyn_tick_reprogram(unsigned long ticks)
  218. {
  219. unsigned long count_buffer_val;
  220. if (ticks > 1) {
  221. initial_match = __raw_readl(S3C2410_TCNTB(OS_TIMER_Nr));
  222. count_buffer_val = (initial_match + ticks * LATCH);
  223. /* S3C2443,s3c2450,2416 , Timer 4 count buffer register bit width is 16bit (0x0 ~ 0xffff)*/
  224. if(count_buffer_val &~0xffff)
  225. count_buffer_val = max_buffer_cnt;
  226. __raw_writel( count_buffer_val,S3C2410_TCNTB(OS_TIMER_Nr));
  227. match_posponed = 1;
  228. }
  229. }
  230. static irqreturn_t
  231. s3c2410_dyn_tick_handler(int irq, void *dev_id)
  232. {
  233. if (match_posponed) {
  234. match_posponed = 0;
  235. __raw_writel(initial_match,S3C2410_TCNTB(OS_TIMER_Nr));
  236. if ((signed long)(initial_match -__raw_readl(S3C2410_TCNTB(OS_TIMER_Nr))) <= 0)
  237. return s3c2410_timer_interrupt(irq, dev_id);
  238. }
  239. return IRQ_NONE;
  240. }
  241. static struct dyn_tick_timer s3c2410_dyn_tick = {
  242. .enable = s3c2410_dyn_tick_enable_disable,
  243. .disable = s3c2410_dyn_tick_enable_disable,
  244. .reprogram = s3c2410_dyn_tick_reprogram,
  245. .handler = s3c2410_dyn_tick_handler,
  246. };
  247. #endif
  248. static void __init s3c2410_timer_init (void)
  249. {
  250. s3c2410_timer_setup();
  251. setup_irq(IRQ_TIMER4, &s3c2410_timer_irq);
  252. }
  253. struct sys_timer s3c24xx_timer = {
  254. .init = s3c2410_timer_init,
  255. .offset = s3c2410_gettimeoffset,
  256. .resume = s3c2410_timer_setup,
  257. #ifdef CONFIG_NO_IDLE_HZ
  258. .dyn_tick = &s3c2410_dyn_tick,
  259. #endif
  260. };