irq.c 19 KB

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  1. /* linux/arch/arm/plat-s3c24xx/irq.c
  2. *
  3. * Copyright (c) 2003,2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. * Changelog:
  21. *
  22. * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
  23. * Fixed compile warnings
  24. *
  25. * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
  26. * Fixed s3c_extirq_type
  27. *
  28. * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
  29. * Addition of ADC/TC demux
  30. *
  31. * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
  32. * Fix for set_irq_type() on low EINT numbers
  33. *
  34. * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
  35. * Tidy up KF's patch and sort out new release
  36. *
  37. * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
  38. * Add support for power management controls
  39. *
  40. * 04-Nov-2004 Ben Dooks
  41. * Fix standard IRQ wake for EINT0..4 and RTC
  42. *
  43. * 22-Feb-2005 Ben Dooks
  44. * Fixed edge-triggering on ADC IRQ
  45. *
  46. * 28-Jun-2005 Ben Dooks
  47. * Mark IRQ_LCD valid
  48. *
  49. * 25-Jul-2005 Ben Dooks
  50. * Split the S3C2440 IRQ code to seperate file
  51. */
  52. #include <linux/init.h>
  53. #include <linux/module.h>
  54. #include <linux/interrupt.h>
  55. #include <linux/ioport.h>
  56. #include <linux/ptrace.h>
  57. #include <linux/sysdev.h>
  58. #include <asm/hardware.h>
  59. #include <asm/irq.h>
  60. #include <asm/io.h>
  61. #include <asm/mach/irq.h>
  62. #include <asm/arch/regs-irq.h>
  63. #include <asm/arch/regs-gpio.h>
  64. #include <asm/plat-s3c24xx/cpu.h>
  65. #include <asm/plat-s3c24xx/pm.h>
  66. #include <asm/plat-s3c24xx/irq.h>
  67. /* wakeup irq control */
  68. #ifdef CONFIG_PM
  69. /* state for IRQs over sleep */
  70. /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
  71. *
  72. * set bit to 1 in allow bitfield to enable the wakeup settings on it
  73. */
  74. unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
  75. unsigned long s3c_irqwake_intmask = 0xffffffffL;
  76. unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
  77. unsigned long s3c_irqwake_eintmask = 0xffffffffL;
  78. int
  79. s3c_irq_wake(unsigned int irqno, unsigned int state)
  80. {
  81. unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
  82. if (!(s3c_irqwake_intallow & irqbit))
  83. return -ENOENT;
  84. printk(KERN_INFO "wake %s for irq %d\n",
  85. state ? "enabled" : "disabled", irqno);
  86. if (!state)
  87. s3c_irqwake_intmask |= irqbit;
  88. else
  89. s3c_irqwake_intmask &= ~irqbit;
  90. return 0;
  91. }
  92. static int
  93. s3c_irqext_wake(unsigned int irqno, unsigned int state)
  94. {
  95. unsigned long bit = 1L << (irqno - EXTINT_OFF);
  96. if (!(s3c_irqwake_eintallow & bit))
  97. return -ENOENT;
  98. printk(KERN_INFO "wake %s for irq %d\n",
  99. state ? "enabled" : "disabled", irqno);
  100. if (!state)
  101. s3c_irqwake_eintmask |= bit;
  102. else
  103. s3c_irqwake_eintmask &= ~bit;
  104. return 0;
  105. }
  106. #else
  107. #define s3c_irqext_wake NULL
  108. #define s3c_irq_wake NULL
  109. #endif
  110. static void
  111. s3c_irq_mask(unsigned int irqno)
  112. {
  113. unsigned long mask;
  114. irqno -= IRQ_EINT0;
  115. mask = __raw_readl(S3C2410_INTMSK);
  116. mask |= 1UL << irqno;
  117. __raw_writel(mask, S3C2410_INTMSK);
  118. }
  119. static inline void
  120. s3c_irq_ack(unsigned int irqno)
  121. {
  122. unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
  123. __raw_writel(bitval, S3C2410_SRCPND);
  124. __raw_writel(bitval, S3C2410_INTPND);
  125. }
  126. static inline void
  127. s3c_irq_maskack(unsigned int irqno)
  128. {
  129. unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
  130. unsigned long mask;
  131. mask = __raw_readl(S3C2410_INTMSK);
  132. __raw_writel(mask|bitval, S3C2410_INTMSK);
  133. __raw_writel(bitval, S3C2410_SRCPND);
  134. __raw_writel(bitval, S3C2410_INTPND);
  135. }
  136. static void
  137. s3c_irq_unmask(unsigned int irqno)
  138. {
  139. unsigned long mask;
  140. if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
  141. irqdbf2("s3c_irq_unmask %d\n", irqno);
  142. irqno -= IRQ_EINT0;
  143. mask = __raw_readl(S3C2410_INTMSK);
  144. mask &= ~(1UL << irqno);
  145. __raw_writel(mask, S3C2410_INTMSK);
  146. }
  147. struct irq_chip s3c_irq_level_chip = {
  148. .name = "s3c-level",
  149. .ack = s3c_irq_maskack,
  150. .mask = s3c_irq_mask,
  151. .unmask = s3c_irq_unmask,
  152. .set_wake = s3c_irq_wake
  153. };
  154. static struct irq_chip s3c_irq_chip = {
  155. .name = "s3c",
  156. .ack = s3c_irq_ack,
  157. .mask = s3c_irq_mask,
  158. .unmask = s3c_irq_unmask,
  159. .set_wake = s3c_irq_wake
  160. };
  161. #if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  162. /*--- For additional interrupt sources on S3C2450/S3C2416 ----*/
  163. static void
  164. s3c2450_irq_mask(unsigned int irqno)
  165. {
  166. unsigned long mask;
  167. irqno -= IRQ_S3C2450_2D;
  168. mask = __raw_readl(S3C2450_INTMSK);
  169. mask |= 1UL << irqno;
  170. __raw_writel(mask, S3C2450_INTMSK);
  171. }
  172. static inline void
  173. s3c2450_irq_maskack(unsigned int irqno)
  174. {
  175. unsigned long bitval = 1UL << (irqno - IRQ_S3C2450_2D);
  176. unsigned long mask;
  177. mask = __raw_readl(S3C2450_INTMSK);
  178. __raw_writel(mask|bitval, S3C2450_INTMSK);
  179. __raw_writel(bitval, S3C2450_SRCPND);
  180. __raw_writel(bitval, S3C2450_INTPND);
  181. }
  182. static void
  183. s3c2450_irq_unmask(unsigned int irqno)
  184. {
  185. unsigned long mask;
  186. irqno -= IRQ_S3C2450_2D;
  187. mask = __raw_readl(S3C2450_INTMSK);
  188. mask &= ~(1UL << irqno);
  189. __raw_writel(mask, S3C2450_INTMSK);
  190. }
  191. struct irq_chip s3c2450_irq_level_chip = {
  192. .name = "s3c2450-level",
  193. .ack = s3c2450_irq_maskack,
  194. .mask = s3c2450_irq_mask,
  195. .unmask = s3c2450_irq_unmask,
  196. //.set_wake = s3c2450_irq_wake
  197. };
  198. /*--------------------------------------------------------------*/
  199. #endif
  200. static void
  201. s3c_irqext_mask(unsigned int irqno)
  202. {
  203. unsigned long mask;
  204. irqno -= EXTINT_OFF;
  205. mask = __raw_readl(S3C24XX_EINTMASK);
  206. mask |= ( 1UL << irqno);
  207. __raw_writel(mask, S3C24XX_EINTMASK);
  208. }
  209. static void
  210. s3c_irqext_ack(unsigned int irqno)
  211. {
  212. unsigned long req;
  213. unsigned long bit;
  214. unsigned long mask;
  215. bit = 1UL << (irqno - EXTINT_OFF);
  216. mask = __raw_readl(S3C24XX_EINTMASK);
  217. __raw_writel(bit, S3C24XX_EINTPEND);
  218. req = __raw_readl(S3C24XX_EINTPEND);
  219. req &= ~mask;
  220. /* not sure if we should be acking the parent irq... */
  221. if (irqno <= IRQ_EINT7 ) {
  222. if ((req & 0xf0) == 0)
  223. s3c_irq_ack(IRQ_EINT4t7);
  224. } else {
  225. if ((req >> 8) == 0)
  226. s3c_irq_ack(IRQ_EINT8t23);
  227. }
  228. }
  229. static void
  230. s3c_irqext_unmask(unsigned int irqno)
  231. {
  232. unsigned long mask;
  233. irqno -= EXTINT_OFF;
  234. mask = __raw_readl(S3C24XX_EINTMASK);
  235. mask &= ~( 1UL << irqno);
  236. __raw_writel(mask, S3C24XX_EINTMASK);
  237. }
  238. int
  239. s3c_irqext_type(unsigned int irq, unsigned int type)
  240. {
  241. void __iomem *extint_reg;
  242. void __iomem *gpcon_reg;
  243. unsigned long gpcon_offset, extint_offset;
  244. unsigned long newvalue = 0, value;
  245. if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
  246. {
  247. gpcon_reg = S3C2410_GPFCON;
  248. extint_reg = S3C24XX_EXTINT0;
  249. gpcon_offset = (irq - IRQ_EINT0) * 2;
  250. extint_offset = (irq - IRQ_EINT0) * 4;
  251. }
  252. else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
  253. {
  254. gpcon_reg = S3C2410_GPFCON;
  255. extint_reg = S3C24XX_EXTINT0;
  256. gpcon_offset = (irq - (EXTINT_OFF)) * 2;
  257. extint_offset = (irq - (EXTINT_OFF)) * 4;
  258. }
  259. else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
  260. {
  261. gpcon_reg = S3C2410_GPGCON;
  262. extint_reg = S3C24XX_EXTINT1;
  263. gpcon_offset = (irq - IRQ_EINT8) * 2;
  264. extint_offset = (irq - IRQ_EINT8) * 4;
  265. }
  266. else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
  267. {
  268. gpcon_reg = S3C2410_GPGCON;
  269. extint_reg = S3C24XX_EXTINT2;
  270. gpcon_offset = (irq - IRQ_EINT8) * 2;
  271. extint_offset = (irq - IRQ_EINT16) * 4;
  272. } else
  273. return -1;
  274. /* Set the GPIO to external interrupt mode */
  275. value = __raw_readl(gpcon_reg);
  276. value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
  277. __raw_writel(value, gpcon_reg);
  278. /* Set the external interrupt to pointed trigger type */
  279. switch (type)
  280. {
  281. case IRQT_NOEDGE:
  282. printk(KERN_WARNING "No edge setting!\n");
  283. break;
  284. case IRQT_RISING:
  285. newvalue = S3C2410_EXTINT_RISEEDGE;
  286. break;
  287. case IRQT_FALLING:
  288. newvalue = S3C2410_EXTINT_FALLEDGE;
  289. break;
  290. case IRQT_BOTHEDGE:
  291. newvalue = S3C2410_EXTINT_BOTHEDGE;
  292. break;
  293. case IRQT_LOW:
  294. newvalue = S3C2410_EXTINT_LOWLEV;
  295. break;
  296. case IRQT_HIGH:
  297. newvalue = S3C2410_EXTINT_HILEV;
  298. break;
  299. default:
  300. printk(KERN_ERR "No such irq type %d", type);
  301. return -1;
  302. }
  303. value = __raw_readl(extint_reg);
  304. value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
  305. __raw_writel(value, extint_reg);
  306. return 0;
  307. }
  308. static struct irq_chip s3c_irqext_chip = {
  309. .name = "s3c-ext",
  310. .mask = s3c_irqext_mask,
  311. .unmask = s3c_irqext_unmask,
  312. .ack = s3c_irqext_ack,
  313. .set_type = s3c_irqext_type,
  314. .set_wake = s3c_irqext_wake
  315. };
  316. static struct irq_chip s3c_irq_eint0t4 = {
  317. .name = "s3c-ext0",
  318. .ack = s3c_irq_ack,
  319. .mask = s3c_irq_mask,
  320. .unmask = s3c_irq_unmask,
  321. .set_wake = s3c_irq_wake,
  322. .set_type = s3c_irqext_type,
  323. };
  324. /* mask values for the parent registers for each of the interrupt types */
  325. #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
  326. #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
  327. #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
  328. #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
  329. /* UART0 */
  330. static void
  331. s3c_irq_uart0_mask(unsigned int irqno)
  332. {
  333. s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
  334. }
  335. static void
  336. s3c_irq_uart0_unmask(unsigned int irqno)
  337. {
  338. s3c_irqsub_unmask(irqno, INTMSK_UART0);
  339. }
  340. static void
  341. s3c_irq_uart0_ack(unsigned int irqno)
  342. {
  343. s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
  344. }
  345. static struct irq_chip s3c_irq_uart0 = {
  346. .name = "s3c-uart0",
  347. .mask = s3c_irq_uart0_mask,
  348. .unmask = s3c_irq_uart0_unmask,
  349. .ack = s3c_irq_uart0_ack,
  350. };
  351. /* UART1 */
  352. static void
  353. s3c_irq_uart1_mask(unsigned int irqno)
  354. {
  355. s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
  356. }
  357. static void
  358. s3c_irq_uart1_unmask(unsigned int irqno)
  359. {
  360. s3c_irqsub_unmask(irqno, INTMSK_UART1);
  361. }
  362. static void
  363. s3c_irq_uart1_ack(unsigned int irqno)
  364. {
  365. s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
  366. }
  367. static struct irq_chip s3c_irq_uart1 = {
  368. .name = "s3c-uart1",
  369. .mask = s3c_irq_uart1_mask,
  370. .unmask = s3c_irq_uart1_unmask,
  371. .ack = s3c_irq_uart1_ack,
  372. };
  373. /* UART2 */
  374. static void
  375. s3c_irq_uart2_mask(unsigned int irqno)
  376. {
  377. s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
  378. }
  379. static void
  380. s3c_irq_uart2_unmask(unsigned int irqno)
  381. {
  382. s3c_irqsub_unmask(irqno, INTMSK_UART2);
  383. }
  384. static void
  385. s3c_irq_uart2_ack(unsigned int irqno)
  386. {
  387. s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
  388. }
  389. static struct irq_chip s3c_irq_uart2 = {
  390. .name = "s3c-uart2",
  391. .mask = s3c_irq_uart2_mask,
  392. .unmask = s3c_irq_uart2_unmask,
  393. .ack = s3c_irq_uart2_ack,
  394. };
  395. /* ADC and Touchscreen */
  396. static void
  397. s3c_irq_adc_mask(unsigned int irqno)
  398. {
  399. s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
  400. }
  401. static void
  402. s3c_irq_adc_unmask(unsigned int irqno)
  403. {
  404. s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
  405. }
  406. static void
  407. s3c_irq_adc_ack(unsigned int irqno)
  408. {
  409. s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
  410. }
  411. static struct irq_chip s3c_irq_adc = {
  412. .name = "s3c-adc",
  413. .mask = s3c_irq_adc_mask,
  414. .unmask = s3c_irq_adc_unmask,
  415. .ack = s3c_irq_adc_ack,
  416. };
  417. /* irq demux for adc */
  418. static void s3c_irq_demux_adc(unsigned int irq,
  419. struct irq_desc *desc)
  420. {
  421. unsigned int subsrc, submsk;
  422. unsigned int offset = 9;
  423. struct irq_desc *mydesc;
  424. /* read the current pending interrupts, and the mask
  425. * for what it is available */
  426. subsrc = __raw_readl(S3C2410_SUBSRCPND);
  427. submsk = __raw_readl(S3C2410_INTSUBMSK);
  428. subsrc &= ~submsk;
  429. subsrc >>= offset;
  430. subsrc &= 3;
  431. if (subsrc != 0) {
  432. if (subsrc & 1) {
  433. mydesc = irq_desc + IRQ_TC;
  434. desc_handle_irq(IRQ_TC, mydesc);
  435. }
  436. if (subsrc & 2) {
  437. mydesc = irq_desc + IRQ_ADC;
  438. desc_handle_irq(IRQ_ADC, mydesc);
  439. }
  440. }
  441. }
  442. static void s3c_irq_demux_uart(unsigned int start)
  443. {
  444. unsigned int subsrc, submsk;
  445. unsigned int offset = start - IRQ_S3CUART_RX0;
  446. struct irq_desc *desc;
  447. /* read the current pending interrupts, and the mask
  448. * for what it is available */
  449. subsrc = __raw_readl(S3C2410_SUBSRCPND);
  450. submsk = __raw_readl(S3C2410_INTSUBMSK);
  451. irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
  452. start, offset, subsrc, submsk);
  453. subsrc &= ~submsk;
  454. subsrc >>= offset;
  455. subsrc &= 7;
  456. if (subsrc != 0) {
  457. desc = irq_desc + start;
  458. if (subsrc & 1)
  459. desc_handle_irq(start, desc);
  460. desc++;
  461. if (subsrc & 2)
  462. desc_handle_irq(start+1, desc);
  463. desc++;
  464. if (subsrc & 4)
  465. desc_handle_irq(start+2, desc);
  466. }
  467. }
  468. /* uart demux entry points */
  469. static void
  470. s3c_irq_demux_uart0(unsigned int irq,
  471. struct irq_desc *desc)
  472. {
  473. irq = irq;
  474. s3c_irq_demux_uart(IRQ_S3CUART_RX0);
  475. }
  476. static void
  477. s3c_irq_demux_uart1(unsigned int irq,
  478. struct irq_desc *desc)
  479. {
  480. irq = irq;
  481. s3c_irq_demux_uart(IRQ_S3CUART_RX1);
  482. }
  483. static void
  484. s3c_irq_demux_uart2(unsigned int irq,
  485. struct irq_desc *desc)
  486. {
  487. irq = irq;
  488. s3c_irq_demux_uart(IRQ_S3CUART_RX2);
  489. }
  490. static void
  491. s3c_irq_demux_extint8(unsigned int irq,
  492. struct irq_desc *desc)
  493. {
  494. unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
  495. unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
  496. eintpnd &= ~eintmsk;
  497. eintpnd &= ~0xff; /* ignore lower irqs */
  498. /* we may as well handle all the pending IRQs here */
  499. while (eintpnd) {
  500. irq = __ffs(eintpnd);
  501. eintpnd &= ~(1<<irq);
  502. irq += (IRQ_EINT4 - 4);
  503. desc_handle_irq(irq, irq_desc + irq);
  504. }
  505. }
  506. static void
  507. s3c_irq_demux_extint4t7(unsigned int irq,
  508. struct irq_desc *desc)
  509. {
  510. unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
  511. unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
  512. eintpnd &= ~eintmsk;
  513. eintpnd &= 0xff; /* only lower irqs */
  514. /* we may as well handle all the pending IRQs here */
  515. while (eintpnd) {
  516. irq = __ffs(eintpnd);
  517. eintpnd &= ~(1<<irq);
  518. irq += (IRQ_EINT4 - 4);
  519. desc_handle_irq(irq, irq_desc + irq);
  520. }
  521. }
  522. #ifdef CONFIG_PM
  523. static struct sleep_save irq_save[] = {
  524. SAVE_ITEM(S3C2410_INTMSK),
  525. SAVE_ITEM(S3C2410_INTSUBMSK),
  526. };
  527. /* the extint values move between the s3c2410/s3c2440 and the s3c2412
  528. * so we use an array to hold them, and to calculate the address of
  529. * the register at run-time
  530. */
  531. static unsigned long save_extint[3];
  532. static unsigned long save_eintflt[4];
  533. static unsigned long save_eintmask;
  534. int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
  535. {
  536. unsigned int i;
  537. for (i = 0; i < ARRAY_SIZE(save_extint); i++)
  538. save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4));
  539. for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
  540. save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4));
  541. s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
  542. save_eintmask = __raw_readl(S3C24XX_EINTMASK);
  543. return 0;
  544. }
  545. int s3c24xx_irq_resume(struct sys_device *dev)
  546. {
  547. unsigned int i;
  548. for (i = 0; i < ARRAY_SIZE(save_extint); i++)
  549. __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4));
  550. for (i = 0; i < ARRAY_SIZE(save_eintflt); i++)
  551. __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4));
  552. s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
  553. __raw_writel(save_eintmask, S3C24XX_EINTMASK);
  554. return 0;
  555. }
  556. #else
  557. #define s3c24xx_irq_suspend NULL
  558. #define s3c24xx_irq_resume NULL
  559. #endif
  560. /* s3c24xx_init_irq
  561. *
  562. * Initialise S3C2410 IRQ system
  563. */
  564. void __init s3c24xx_init_irq(void)
  565. {
  566. unsigned long pend;
  567. unsigned long last;
  568. int irqno;
  569. int i;
  570. irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
  571. /* first, clear all interrupts pending... */
  572. last = 0;
  573. for (i = 0; i < 4; i++) {
  574. pend = __raw_readl(S3C24XX_EINTPEND);
  575. if (pend == 0 || pend == last)
  576. break;
  577. __raw_writel(pend, S3C24XX_EINTPEND);
  578. printk("irq: clearing pending ext status %08x\n", (int)pend);
  579. last = pend;
  580. }
  581. last = 0;
  582. for (i = 0; i < 4; i++) {
  583. pend = __raw_readl(S3C2410_INTPND);
  584. if (pend == 0 || pend == last)
  585. break;
  586. __raw_writel(pend, S3C2410_SRCPND);
  587. __raw_writel(pend, S3C2410_INTPND);
  588. printk("irq: clearing pending status %08x\n", (int)pend);
  589. last = pend;
  590. }
  591. last = 0;
  592. for (i = 0; i < 4; i++) {
  593. pend = __raw_readl(S3C2410_SUBSRCPND);
  594. if (pend == 0 || pend == last)
  595. break;
  596. printk("irq: clearing subpending status %08x\n", (int)pend);
  597. __raw_writel(pend, S3C2410_SUBSRCPND);
  598. last = pend;
  599. }
  600. /* register the main interrupts */
  601. irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
  602. for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
  603. /* set all the s3c2410 internal irqs */
  604. switch (irqno) {
  605. /* deal with the special IRQs (cascaded) */
  606. case IRQ_EINT4t7:
  607. case IRQ_EINT8t23:
  608. case IRQ_UART0:
  609. case IRQ_UART1:
  610. case IRQ_UART2:
  611. case IRQ_ADCPARENT:
  612. set_irq_chip(irqno, &s3c_irq_level_chip);
  613. set_irq_handler(irqno, handle_level_irq);
  614. break;
  615. case IRQ_RESERVED6:
  616. case IRQ_RESERVED24:
  617. /* no IRQ here */
  618. break;
  619. default:
  620. //irqdbf("registering irq %d (s3c irq)\n", irqno);
  621. set_irq_chip(irqno, &s3c_irq_chip);
  622. set_irq_handler(irqno, handle_edge_irq);
  623. set_irq_flags(irqno, IRQF_VALID);
  624. }
  625. }
  626. /* setup the cascade irq handlers */
  627. set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
  628. set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
  629. set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
  630. set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
  631. set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
  632. set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
  633. /* external interrupts */
  634. for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
  635. irqdbf("registering irq %d (ext int)\n", irqno);
  636. set_irq_chip(irqno, &s3c_irq_eint0t4);
  637. set_irq_handler(irqno, handle_edge_irq);
  638. set_irq_flags(irqno, IRQF_VALID);
  639. }
  640. for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
  641. irqdbf("registering irq %d (extended s3c irq)\n", irqno);
  642. set_irq_chip(irqno, &s3c_irqext_chip);
  643. set_irq_handler(irqno, handle_edge_irq);
  644. set_irq_flags(irqno, IRQF_VALID);
  645. }
  646. /* register the uart interrupts */
  647. irqdbf("s3c2410: registering external interrupts\n");
  648. for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
  649. irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
  650. set_irq_chip(irqno, &s3c_irq_uart0);
  651. set_irq_handler(irqno, handle_level_irq);
  652. set_irq_flags(irqno, IRQF_VALID);
  653. }
  654. for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
  655. irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
  656. set_irq_chip(irqno, &s3c_irq_uart1);
  657. set_irq_handler(irqno, handle_level_irq);
  658. set_irq_flags(irqno, IRQF_VALID);
  659. }
  660. for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
  661. irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
  662. set_irq_chip(irqno, &s3c_irq_uart2);
  663. set_irq_handler(irqno, handle_level_irq);
  664. set_irq_flags(irqno, IRQF_VALID);
  665. }
  666. for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
  667. irqdbf("registering irq %d (s3c adc irq)\n", irqno);
  668. set_irq_chip(irqno, &s3c_irq_adc);
  669. set_irq_handler(irqno, handle_edge_irq);
  670. set_irq_flags(irqno, IRQF_VALID);
  671. }
  672. #if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  673. /* first, clear all interrupts pending... */
  674. last = 0;
  675. for (i = 0; i < 4; i++) {
  676. pend = __raw_readl(S3C2450_INTPND);
  677. if (pend == 0 || pend == last)
  678. break;
  679. __raw_writel(pend, S3C2450_SRCPND);
  680. __raw_writel(pend, S3C2450_INTPND);
  681. printk("irq: clearing pending status %08x\n", (int)pend);
  682. last = pend;
  683. }
  684. for (irqno = IRQ_S3C2450_2D; irqno <= IRQ_S3C2450_I2S1; irqno++) {
  685. irqdbf("registering irq %d (s3c gib irq)\n", irqno);
  686. set_irq_chip(irqno, &s3c2450_irq_level_chip);
  687. set_irq_handler(irqno, handle_level_irq);
  688. set_irq_flags(irqno, IRQF_VALID);
  689. }
  690. #endif
  691. irqdbf("s3c2410: registered interrupt handlers\n");
  692. }