gpio.c 8.8 KB

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  1. /* linux/arch/arm/plat-s3c24xx/gpio.c
  2. *
  3. * Copyright (c) 2004-2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C24XX GPIO support
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/ioport.h>
  27. #include <asm/hardware.h>
  28. #include <asm/irq.h>
  29. #include <asm/io.h>
  30. #include <asm/arch/regs-gpio.h>
  31. void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function)
  32. {
  33. void __iomem *base = S3C24XX_GPIO_BASE(pin);
  34. unsigned long mask;
  35. unsigned long con;
  36. unsigned long flags;
  37. if (pin < S3C2410_GPIO_BANKB) {
  38. mask = 1 << S3C2410_GPIO_OFFSET(pin);
  39. } else {
  40. mask = 3 << S3C2410_GPIO_OFFSET(pin)*2;
  41. }
  42. switch (function) {
  43. case S3C2410_GPIO_LEAVE:
  44. mask = 0;
  45. function = 0;
  46. break;
  47. case S3C2410_GPIO_INPUT:
  48. case S3C2410_GPIO_OUTPUT:
  49. case S3C2410_GPIO_SFN2:
  50. case S3C2410_GPIO_SFN3:
  51. if (pin < S3C2410_GPIO_BANKB) {
  52. function -= 1;
  53. function &= 1;
  54. function <<= S3C2410_GPIO_OFFSET(pin);
  55. } else {
  56. function &= 3;
  57. function <<= S3C2410_GPIO_OFFSET(pin)*2;
  58. }
  59. }
  60. /* modify the specified register wwith IRQs off */
  61. local_irq_save(flags);
  62. con = __raw_readl(base + 0x00);
  63. con &= ~mask;
  64. con |= function;
  65. __raw_writel(con, base + 0x00);
  66. local_irq_restore(flags);
  67. }
  68. EXPORT_SYMBOL(s3c2410_gpio_cfgpin);
  69. unsigned int s3c2410_gpio_getcfg(unsigned int pin)
  70. {
  71. void __iomem *base = S3C24XX_GPIO_BASE(pin);
  72. unsigned long val = __raw_readl(base);
  73. if (pin < S3C2410_GPIO_BANKB) {
  74. val >>= S3C2410_GPIO_OFFSET(pin);
  75. val &= 1;
  76. val += 1;
  77. } else {
  78. val >>= S3C2410_GPIO_OFFSET(pin)*2;
  79. val &= 3;
  80. }
  81. return val | S3C2410_GPIO_INPUT;
  82. }
  83. EXPORT_SYMBOL(s3c2410_gpio_getcfg);
  84. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  85. void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
  86. {
  87. void __iomem *base = S3C24XX_GPIO_BASE(pin);
  88. unsigned long offs = S3C2410_GPIO_OFFSET(pin)*2;
  89. unsigned long flags;
  90. unsigned long up;
  91. if (pin < S3C2410_GPIO_BANKB)
  92. return;
  93. local_irq_save(flags);
  94. up = __raw_readl(base + 0x08);
  95. up &= ~(0x3 << offs);
  96. up |= to << offs;
  97. __raw_writel(up, base + 0x08);
  98. local_irq_restore(flags);
  99. }
  100. #else
  101. void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
  102. {
  103. void __iomem *base = S3C24XX_GPIO_BASE(pin);
  104. unsigned long offs = S3C2410_GPIO_OFFSET(pin);
  105. unsigned long flags;
  106. unsigned long up;
  107. if (pin < S3C2410_GPIO_BANKB)
  108. return;
  109. local_irq_save(flags);
  110. up = __raw_readl(base + 0x08);
  111. up &= ~(1L << offs);
  112. up |= to << offs;
  113. __raw_writel(up, base + 0x08);
  114. local_irq_restore(flags);
  115. }
  116. #endif
  117. EXPORT_SYMBOL(s3c2410_gpio_pullup);
  118. void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
  119. {
  120. void __iomem *base = S3C24XX_GPIO_BASE(pin);
  121. unsigned long offs = S3C2410_GPIO_OFFSET(pin);
  122. unsigned long flags;
  123. unsigned long dat;
  124. local_irq_save(flags);
  125. dat = __raw_readl(base + 0x04);
  126. dat &= ~(1 << offs);
  127. dat |= to << offs;
  128. __raw_writel(dat, base + 0x04);
  129. local_irq_restore(flags);
  130. }
  131. EXPORT_SYMBOL(s3c2410_gpio_setpin);
  132. unsigned int s3c2410_gpio_getpin(unsigned int pin)
  133. {
  134. void __iomem *base = S3C24XX_GPIO_BASE(pin);
  135. unsigned long offs = S3C2410_GPIO_OFFSET(pin);
  136. return __raw_readl(base + 0x04) & (1<< offs);
  137. }
  138. EXPORT_SYMBOL(s3c2410_gpio_getpin);
  139. unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change)
  140. {
  141. unsigned long flags;
  142. unsigned long misccr;
  143. local_irq_save(flags);
  144. misccr = __raw_readl(S3C24XX_MISCCR);
  145. misccr &= ~clear;
  146. misccr ^= change;
  147. __raw_writel(misccr, S3C24XX_MISCCR);
  148. local_irq_restore(flags);
  149. return misccr;
  150. }
  151. EXPORT_SYMBOL(s3c2410_modify_misccr);
  152. int s3c2410_gpio_getirq(unsigned int pin)
  153. {
  154. if (pin < S3C2410_GPF0 || pin > S3C2410_GPG15)
  155. return -1; /* not valid interrupts */
  156. if (pin < S3C2410_GPG0 && pin > S3C2410_GPF7)
  157. return -1; /* not valid pin */
  158. if (pin < S3C2410_GPF4)
  159. return (pin - S3C2410_GPF0) + IRQ_EINT0;
  160. if (pin < S3C2410_GPG0)
  161. return (pin - S3C2410_GPF4) + IRQ_EINT4;
  162. return (pin - S3C2410_GPG0) + IRQ_EINT8;
  163. }
  164. EXPORT_SYMBOL(s3c2410_gpio_getirq);
  165. #if defined(CONFIG_PLAT_S3C64XX)
  166. /* --------------------------------------------------------------
  167. * Set up GPIOs
  168. *-------------------------------------------------------------*/
  169. static void __iomem *gpio_base_offset[]=
  170. {
  171. S3C24XX_VA_GPIO + 0x00, //GPA ,4bit
  172. S3C24XX_VA_GPIO + 0x20, //GPB ,4bit
  173. S3C24XX_VA_GPIO + 0x40, //GPC ,4bit
  174. S3C24XX_VA_GPIO + 0x60, //GPD ,4bit
  175. S3C24XX_VA_GPIO + 0x80, //GPE ,4bit
  176. S3C24XX_VA_GPIO + 0xA0, //GPF ,2bit
  177. S3C24XX_VA_GPIO + 0xC0, //GPG ,4bit
  178. S3C24XX_VA_GPIO + 0xE0, //GPH ,4bit
  179. S3C24XX_VA_GPIO + 0x100, //GPI ,2bit
  180. S3C24XX_VA_GPIO + 0x120, //GPJ ,2bit
  181. S3C24XX_VA_GPIO + 0x140, //GPO ,2bit
  182. S3C24XX_VA_GPIO + 0x160, //GPP ,2bit
  183. S3C24XX_VA_GPIO + 0x180, //GPQ ,2bit
  184. S3C24XX_VA_GPIO + 0x800, //GPK ,4bit
  185. S3C24XX_VA_GPIO + 0x810, //GPL ,4bit
  186. S3C24XX_VA_GPIO + 0x820, //GPM ,4bit
  187. S3C24XX_VA_GPIO + 0x830 //GPN ,2bit
  188. };
  189. void s3c_gpio_cfgpin(unsigned int pin, unsigned int function)
  190. {
  191. void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
  192. unsigned long mask;
  193. unsigned long con;
  194. unsigned long flags;
  195. unsigned long offs = S3C_GPIO_OFFSET(pin);
  196. if ((pin < S3C_GPIO_BANKF)||((pin >=S3C_GPIO_BANKG)&&\
  197. (pin<S3C_GPIO_BANKI))||((pin>=S3C_GPIO_BANKK)&&\
  198. (pin<S3C_GPIO_BANKN)))
  199. {
  200. offs = (offs) *4;
  201. if((pin == S3C_GPH8)||(pin==S3C_GPH9)||\
  202. (pin>=S3C_GPK8&&pin<=S3C_GPK15)||\
  203. (pin>=S3C_GPL8&&pin<=S3C_GPL14))
  204. {
  205. base = base + 0x04;
  206. /* only for con1:8~14 or 15 regiter configuratio nvalue change ...*/
  207. offs = offs - 32;
  208. }
  209. mask = 0xF << offs;
  210. }
  211. else
  212. {
  213. offs = offs*2;
  214. mask = 0x3 << offs;
  215. }
  216. local_irq_save(flags);
  217. con = __raw_readl(base + 0x00);
  218. con &= ~mask;
  219. con |= (function << offs);
  220. __raw_writel(con, base + 0x00);
  221. local_irq_restore(flags);
  222. }
  223. EXPORT_SYMBOL(s3c_gpio_cfgpin);
  224. unsigned int s3c_gpio_getcfg(unsigned int pin)
  225. {
  226. void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
  227. unsigned long mask;
  228. if ((pin < S3C_GPIO_BANKF)||((pin >=S3C_GPIO_BANKG)&&\
  229. (pin<S3C_GPIO_BANKI))||((pin>=S3C_GPIO_BANKK)&&\
  230. (pin<S3C_GPIO_BANKN)))
  231. {
  232. mask = 0xF << S3C_GPIO_OFFSET(pin)*4;
  233. if((pin == S3C_GPH8)||(pin==S3C_GPH9)||\
  234. (pin>=S3C_GPK8&&pin<=S3C_GPK15)||\
  235. (pin>=S3C_GPL8&&pin<=S3C_GPL14))
  236. {
  237. base = base + 0x04;
  238. mask = 0xF << (S3C_GPIO_OFFSET(pin)*4 -32);
  239. }
  240. }
  241. else
  242. {
  243. mask = 0x3 << S3C_GPIO_OFFSET(pin)*2;
  244. }
  245. return __raw_readl(base) & mask;
  246. }
  247. EXPORT_SYMBOL(s3c_gpio_getcfg);
  248. void s3c_gpio_pullup(unsigned int pin, unsigned int to)
  249. {
  250. void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
  251. unsigned long offs = S3C_GPIO_OFFSET(pin)*2;
  252. unsigned long flags;
  253. unsigned long up;
  254. unsigned long mask;
  255. mask = 0x3 << offs;
  256. if((pin>=S3C_GPH0 && pin<=S3C_GPH9)||\
  257. (pin>=S3C_GPK0 && pin<=S3C_GPK15)||\
  258. (pin>=S3C_GPL0 && pin<=S3C_GPL14))
  259. {
  260. base = base+0x04;
  261. }
  262. local_irq_save(flags);
  263. up = __raw_readl(base + 0x08);
  264. up &= ~mask;
  265. up |= to << offs;
  266. __raw_writel(up, base + 0x08);
  267. local_irq_restore(flags);
  268. }
  269. EXPORT_SYMBOL(s3c_gpio_pullup);
  270. void s3c_gpio_setpin(unsigned int pin, unsigned int to)
  271. {
  272. void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
  273. unsigned long offs = S3C_GPIO_OFFSET(pin);
  274. unsigned long flags;
  275. unsigned long dat;
  276. if((pin>=S3C_GPH0 && pin<=S3C_GPH9)||\
  277. (pin>=S3C_GPK0 && pin<=S3C_GPK15)||\
  278. (pin>=S3C_GPL0 && pin<=S3C_GPL14))
  279. {
  280. base = base+0x04;
  281. }
  282. local_irq_save(flags);
  283. dat = __raw_readl(base + 0x04);
  284. dat &= ~(1 << offs);
  285. dat |= to << offs;
  286. __raw_writel(dat, base + 0x04);
  287. local_irq_restore(flags);
  288. }
  289. EXPORT_SYMBOL(s3c_gpio_setpin);
  290. unsigned int s3c_gpio_getpin(unsigned int pin)
  291. {
  292. void __iomem *base = gpio_base_offset[S3C_GPIO_BASE(pin)];
  293. unsigned long offs = S3C_GPIO_OFFSET(pin);
  294. if((pin>=S3C_GPH0 && pin<=S3C_GPH9)||\
  295. (pin>=S3C_GPK0 && pin<=S3C_GPK15)||\
  296. (pin>=S3C_GPL0 && pin<=S3C_GPL14))
  297. {
  298. base = base+0x04;
  299. }
  300. return __raw_readl(base + 0x04) & (1<< offs);
  301. }
  302. EXPORT_SYMBOL(s3c_gpio_getpin);
  303. int s3c_gpio_getirq(unsigned int pin)
  304. {
  305. /* mandatory */
  306. /* Implement this function */
  307. return 0;
  308. }
  309. EXPORT_SYMBOL(s3c_gpio_getirq);
  310. int s3c_gpio_irqfilter(unsigned int pin, unsigned int on,
  311. unsigned int config)
  312. {
  313. return 0;
  314. }
  315. EXPORT_SYMBOL(s3c_gpio_irqfilter);
  316. #endif