dma.c 34 KB

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  1. /* linux/arch/arm/plat-s3c24xx/dma.c
  2. *
  3. * Copyright (c) 2003-2005,2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 DMA core
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #ifdef CONFIG_S3C2410_DMA_DEBUG
  15. #define DEBUG
  16. #endif
  17. #include <linux/module.h>
  18. #include <linux/init.h>
  19. #include <linux/sched.h>
  20. #include <linux/spinlock.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/sysdev.h>
  23. #include <linux/slab.h>
  24. #include <linux/errno.h>
  25. #include <linux/delay.h>
  26. #include <asm/system.h>
  27. #include <asm/irq.h>
  28. #include <asm/hardware.h>
  29. #include <asm/io.h>
  30. #include <asm/dma.h>
  31. #include <asm/mach/dma.h>
  32. #include <asm/arch/map.h>
  33. #include <asm/plat-s3c24xx/dma.h>
  34. /* io map for dma */
  35. static void __iomem *dma_base;
  36. static struct kmem_cache *dma_kmem;
  37. static int dma_channels;
  38. static struct s3c24xx_dma_selection dma_sel;
  39. /* dma channel state information */
  40. struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
  41. /* debugging functions */
  42. #define BUF_MAGIC (0xcafebabe)
  43. #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
  44. #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
  45. #if 1
  46. #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
  47. #else
  48. static inline void
  49. dma_wrreg(struct s3c2410_dma_chan *chan, int reg, unsigned long val)
  50. {
  51. pr_debug("writing %08x to register %08x\n",(unsigned int)val,reg);
  52. writel(val, dma_regaddr(chan, reg));
  53. }
  54. #endif
  55. #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
  56. /* captured register state for debug */
  57. struct s3c2410_dma_regstate {
  58. unsigned long dcsrc;
  59. unsigned long disrc;
  60. unsigned long dstat;
  61. unsigned long dcon;
  62. unsigned long dmsktrig;
  63. };
  64. #ifdef CONFIG_S3C2410_DMA_DEBUG
  65. /* dmadbg_showregs
  66. *
  67. * simple debug routine to print the current state of the dma registers
  68. */
  69. static void
  70. dmadbg_capture(struct s3c2410_dma_chan *chan, struct s3c2410_dma_regstate *regs)
  71. {
  72. regs->dcsrc = dma_rdreg(chan, S3C2410_DMA_DCSRC);
  73. regs->disrc = dma_rdreg(chan, S3C2410_DMA_DISRC);
  74. regs->dstat = dma_rdreg(chan, S3C2410_DMA_DSTAT);
  75. regs->dcon = dma_rdreg(chan, S3C2410_DMA_DCON);
  76. regs->dmsktrig = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
  77. }
  78. static void
  79. dmadbg_dumpregs(const char *fname, int line, struct s3c2410_dma_chan *chan,
  80. struct s3c2410_dma_regstate *regs)
  81. {
  82. printk(KERN_DEBUG "dma%d: %s:%d: DCSRC=%08lx, DISRC=%08lx, DSTAT=%08lx DMT=%02lx, DCON=%08lx\n",
  83. chan->number, fname, line,
  84. regs->dcsrc, regs->disrc, regs->dstat, regs->dmsktrig,
  85. regs->dcon);
  86. }
  87. static void
  88. dmadbg_showchan(const char *fname, int line, struct s3c2410_dma_chan *chan)
  89. {
  90. struct s3c2410_dma_regstate state;
  91. dmadbg_capture(chan, &state);
  92. printk(KERN_DEBUG "dma%d: %s:%d: ls=%d, cur=%p, %p %p\n",
  93. chan->number, fname, line, chan->load_state,
  94. chan->curr, chan->next, chan->end);
  95. dmadbg_dumpregs(fname, line, chan, &state);
  96. }
  97. static void
  98. dmadbg_showregs(const char *fname, int line, struct s3c2410_dma_chan *chan)
  99. {
  100. struct s3c2410_dma_regstate state;
  101. dmadbg_capture(chan, &state);
  102. dmadbg_dumpregs(fname, line, chan, &state);
  103. }
  104. #define dbg_showregs(chan) dmadbg_showregs(__FUNCTION__, __LINE__, (chan))
  105. #define dbg_showchan(chan) dmadbg_showchan(__FUNCTION__, __LINE__, (chan))
  106. #else
  107. #define dbg_showregs(chan) do { } while(0)
  108. #define dbg_showchan(chan) do { } while(0)
  109. #endif /* CONFIG_S3C2410_DMA_DEBUG */
  110. static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
  111. /* lookup_dma_channel
  112. *
  113. * change the dma channel number given into a real dma channel id
  114. */
  115. static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
  116. {
  117. if (channel & DMACH_LOW_LEVEL)
  118. return &s3c2410_chans[channel & ~DMACH_LOW_LEVEL];
  119. else
  120. return dma_chan_map[channel];
  121. }
  122. /* s3c2410_dma_stats_timeout
  123. *
  124. * Update DMA stats from timeout info
  125. */
  126. static void
  127. s3c2410_dma_stats_timeout(struct s3c2410_dma_stats *stats, int val)
  128. {
  129. if (stats == NULL)
  130. return;
  131. if (val > stats->timeout_longest)
  132. stats->timeout_longest = val;
  133. if (val < stats->timeout_shortest)
  134. stats->timeout_shortest = val;
  135. stats->timeout_avg += val;
  136. }
  137. /* s3c2410_dma_waitforload
  138. *
  139. * wait for the DMA engine to load a buffer, and update the state accordingly
  140. */
  141. static int
  142. s3c2410_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
  143. {
  144. int timeout = chan->load_timeout;
  145. int took;
  146. if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
  147. printk(KERN_ERR "dma%d: s3c2410_dma_waitforload() called in loadstate %d from line %d\n", chan->number, chan->load_state, line);
  148. return 0;
  149. }
  150. if (chan->stats != NULL)
  151. chan->stats->loads++;
  152. while (--timeout > 0) {
  153. if ((dma_rdreg(chan, S3C2410_DMA_DSTAT) << (32-20)) != 0) {
  154. took = chan->load_timeout - timeout;
  155. s3c2410_dma_stats_timeout(chan->stats, took);
  156. switch (chan->load_state) {
  157. case S3C2410_DMALOAD_1LOADED:
  158. chan->load_state = S3C2410_DMALOAD_1RUNNING;
  159. break;
  160. default:
  161. printk(KERN_ERR "dma%d: unknown load_state in s3c2410_dma_waitforload() %d\n", chan->number, chan->load_state);
  162. }
  163. return 1;
  164. }
  165. }
  166. if (chan->stats != NULL) {
  167. chan->stats->timeout_failed++;
  168. }
  169. return 0;
  170. }
  171. /* s3c2410_dma_loadbuffer
  172. *
  173. * load a buffer, and update the channel state
  174. */
  175. static inline int
  176. s3c2410_dma_loadbuffer(struct s3c2410_dma_chan *chan,
  177. struct s3c2410_dma_buf *buf)
  178. {
  179. unsigned long reload;
  180. if (buf == NULL) {
  181. dmawarn("buffer is NULL\n");
  182. return -EINVAL;
  183. }
  184. pr_debug("s3c2410_chan_loadbuffer: loading buff %p (0x%08lx,0x%06x)\n",
  185. buf, (unsigned long)buf->data, buf->size);
  186. /* check the state of the channel before we do anything */
  187. if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
  188. dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
  189. }
  190. if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
  191. dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
  192. }
  193. /* it would seem sensible if we are the last buffer to not bother
  194. * with the auto-reload bit, so that the DMA engine will not try
  195. * and load another transfer after this one has finished...
  196. */
  197. if (chan->load_state == S3C2410_DMALOAD_NONE) {
  198. pr_debug("load_state is none, checking for noreload (next=%p)\n",
  199. buf->next);
  200. reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
  201. } else {
  202. //pr_debug("load_state is %d => autoreload\n", chan->load_state);
  203. reload = S3C2410_DCON_AUTORELOAD;
  204. }
  205. if ((buf->data & 0xf0000000) != 0x30000000) {
  206. dmawarn("dmaload: buffer is %p\n", (void *)buf->data);
  207. }
  208. writel(buf->data, chan->addr_reg);
  209. dma_wrreg(chan, S3C2410_DMA_DCON,
  210. chan->dcon | reload | (buf->size/chan->xfer_unit));
  211. chan->next = buf->next;
  212. /* update the state of the channel */
  213. switch (chan->load_state) {
  214. case S3C2410_DMALOAD_NONE:
  215. chan->load_state = S3C2410_DMALOAD_1LOADED;
  216. break;
  217. case S3C2410_DMALOAD_1RUNNING:
  218. chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
  219. break;
  220. default:
  221. dmawarn("dmaload: unknown state %d in loadbuffer\n",
  222. chan->load_state);
  223. break;
  224. }
  225. return 0;
  226. }
  227. /* s3c2410_dma_call_op
  228. *
  229. * small routine to call the op routine with the given op if it has been
  230. * registered
  231. */
  232. static void
  233. s3c2410_dma_call_op(struct s3c2410_dma_chan *chan, enum s3c2410_chan_op op)
  234. {
  235. if (chan->op_fn != NULL) {
  236. (chan->op_fn)(chan, op);
  237. }
  238. }
  239. /* s3c2410_dma_buffdone
  240. *
  241. * small wrapper to check if callback routine needs to be called, and
  242. * if so, call it
  243. */
  244. static inline void
  245. s3c2410_dma_buffdone(struct s3c2410_dma_chan *chan, struct s3c2410_dma_buf *buf,
  246. enum s3c2410_dma_buffresult result)
  247. {
  248. #if 0
  249. pr_debug("callback_fn=%p, buf=%p, id=%p, size=%d, result=%d\n",
  250. chan->callback_fn, buf, buf->id, buf->size, result);
  251. #endif
  252. if (chan->callback_fn != NULL) {
  253. (chan->callback_fn)(chan, buf->id, buf->size, result);
  254. }
  255. }
  256. /* s3c2410_dma_start
  257. *
  258. * start a dma channel going
  259. */
  260. static int s3c2410_dma_start(struct s3c2410_dma_chan *chan)
  261. {
  262. unsigned long tmp;
  263. unsigned long flags;
  264. pr_debug("s3c2410_start_dma: channel=%d\n", chan->number);
  265. local_irq_save(flags);
  266. if (chan->state == S3C2410_DMA_RUNNING) {
  267. pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state);
  268. local_irq_restore(flags);
  269. return 0;
  270. }
  271. chan->state = S3C2410_DMA_RUNNING;
  272. /* check wether there is anything to load, and if not, see
  273. * if we can find anything to load
  274. */
  275. if (chan->load_state == S3C2410_DMALOAD_NONE) {
  276. if (chan->next == NULL) {
  277. printk(KERN_ERR "dma%d: channel has nothing loaded\n",
  278. chan->number);
  279. chan->state = S3C2410_DMA_IDLE;
  280. local_irq_restore(flags);
  281. return -EINVAL;
  282. }
  283. s3c2410_dma_loadbuffer(chan, chan->next);
  284. }
  285. dbg_showchan(chan);
  286. /* enable the channel */
  287. if (!chan->irq_enabled) {
  288. enable_irq(chan->irq);
  289. chan->irq_enabled = 1;
  290. }
  291. /* start the channel going */
  292. tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
  293. tmp &= ~S3C2410_DMASKTRIG_STOP;
  294. tmp |= S3C2410_DMASKTRIG_ON;
  295. dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
  296. pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp);
  297. #if 0
  298. /* the dma buffer loads should take care of clearing the AUTO
  299. * reloading feature */
  300. tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
  301. tmp &= ~S3C2410_DCON_NORELOAD;
  302. dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
  303. #endif
  304. s3c2410_dma_call_op(chan, S3C2410_DMAOP_START);
  305. dbg_showchan(chan);
  306. /* if we've only loaded one buffer onto the channel, then chec
  307. * to see if we have another, and if so, try and load it so when
  308. * the first buffer is finished, the new one will be loaded onto
  309. * the channel */
  310. if (chan->next != NULL) {
  311. if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
  312. if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
  313. pr_debug("%s: buff not yet loaded, no more todo\n",
  314. __FUNCTION__);
  315. } else {
  316. chan->load_state = S3C2410_DMALOAD_1RUNNING;
  317. s3c2410_dma_loadbuffer(chan, chan->next);
  318. }
  319. } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
  320. s3c2410_dma_loadbuffer(chan, chan->next);
  321. }
  322. }
  323. local_irq_restore(flags);
  324. return 0;
  325. }
  326. /* s3c2410_dma_canload
  327. *
  328. * work out if we can queue another buffer into the DMA engine
  329. */
  330. static int
  331. s3c2410_dma_canload(struct s3c2410_dma_chan *chan)
  332. {
  333. if (chan->load_state == S3C2410_DMALOAD_NONE ||
  334. chan->load_state == S3C2410_DMALOAD_1RUNNING)
  335. return 1;
  336. return 0;
  337. }
  338. /* s3c2410_dma_enqueue
  339. *
  340. * queue an given buffer for dma transfer.
  341. *
  342. * id the device driver's id information for this buffer
  343. * data the physical address of the buffer data
  344. * size the size of the buffer in bytes
  345. *
  346. * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
  347. * is checked, and if set, the channel is started. If this flag isn't set,
  348. * then an error will be returned.
  349. *
  350. * It is possible to queue more than one DMA buffer onto a channel at
  351. * once, and the code will deal with the re-loading of the next buffer
  352. * when necessary.
  353. */
  354. int s3c2410_dma_enqueue(unsigned int channel, void *id,
  355. dma_addr_t data, int size)
  356. {
  357. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  358. struct s3c2410_dma_buf *buf;
  359. unsigned long flags;
  360. if (chan == NULL)
  361. return -EINVAL;
  362. pr_debug("%s: id=%p, data=%08x, size=%d\n",
  363. __FUNCTION__, id, (unsigned int)data, size);
  364. buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
  365. if (buf == NULL) {
  366. pr_debug("%s: out of memory (%ld alloc)\n",
  367. __FUNCTION__, (long)sizeof(*buf));
  368. return -ENOMEM;
  369. }
  370. //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
  371. //dbg_showchan(chan);
  372. buf->next = NULL;
  373. buf->data = buf->ptr = data;
  374. buf->size = size;
  375. buf->id = id;
  376. buf->magic = BUF_MAGIC;
  377. local_irq_save(flags);
  378. if (chan->curr == NULL) {
  379. /* we've got nothing loaded... */
  380. pr_debug("%s: buffer %p queued onto empty channel\n",
  381. __FUNCTION__, buf);
  382. chan->curr = buf;
  383. chan->end = buf;
  384. chan->next = NULL;
  385. } else {
  386. pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
  387. chan->number, __FUNCTION__, buf);
  388. if (chan->end == NULL)
  389. pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
  390. chan->number, __FUNCTION__, chan);
  391. chan->end->next = buf;
  392. chan->end = buf;
  393. }
  394. /* if necessary, update the next buffer field */
  395. if (chan->next == NULL)
  396. chan->next = buf;
  397. /* check to see if we can load a buffer */
  398. if (chan->state == S3C2410_DMA_RUNNING) {
  399. if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
  400. if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
  401. printk(KERN_ERR "dma%d: loadbuffer:"
  402. "timeout loading buffer\n",
  403. chan->number);
  404. dbg_showchan(chan);
  405. local_irq_restore(flags);
  406. return -EINVAL;
  407. }
  408. }
  409. while (s3c2410_dma_canload(chan) && chan->next != NULL) {
  410. s3c2410_dma_loadbuffer(chan, chan->next);
  411. }
  412. } else if (chan->state == S3C2410_DMA_IDLE) {
  413. if (chan->flags & S3C2410_DMAF_AUTOSTART) {
  414. /* bug fix */
  415. /*s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START);*/
  416. s3c2410_dma_ctrl(channel, S3C2410_DMAOP_START);
  417. } else {
  418. printk(KERN_DEBUG "loading onto stopped channel\n");
  419. }
  420. }
  421. local_irq_restore(flags);
  422. return 0;
  423. }
  424. EXPORT_SYMBOL(s3c2410_dma_enqueue);
  425. static inline void
  426. s3c2410_dma_freebuf(struct s3c2410_dma_buf *buf)
  427. {
  428. int magicok = (buf->magic == BUF_MAGIC);
  429. buf->magic = -1;
  430. if (magicok) {
  431. kmem_cache_free(dma_kmem, buf);
  432. } else {
  433. printk("s3c2410_dma_freebuf: buff %p with bad magic\n", buf);
  434. }
  435. }
  436. /* s3c2410_dma_lastxfer
  437. *
  438. * called when the system is out of buffers, to ensure that the channel
  439. * is prepared for shutdown.
  440. */
  441. static inline void
  442. s3c2410_dma_lastxfer(struct s3c2410_dma_chan *chan)
  443. {
  444. #if 0
  445. pr_debug("dma%d: s3c2410_dma_lastxfer: load_state %d\n",
  446. chan->number, chan->load_state);
  447. #endif
  448. switch (chan->load_state) {
  449. case S3C2410_DMALOAD_NONE:
  450. break;
  451. case S3C2410_DMALOAD_1LOADED:
  452. if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
  453. /* flag error? */
  454. printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
  455. chan->number, __FUNCTION__);
  456. return;
  457. }
  458. break;
  459. case S3C2410_DMALOAD_1LOADED_1RUNNING:
  460. /* I belive in this case we do not have anything to do
  461. * until the next buffer comes along, and we turn off the
  462. * reload */
  463. return;
  464. default:
  465. pr_debug("dma%d: lastxfer: unhandled load_state %d with no next\n",
  466. chan->number, chan->load_state);
  467. return;
  468. }
  469. /* hopefully this'll shut the damned thing up after the transfer... */
  470. dma_wrreg(chan, S3C2410_DMA_DCON, chan->dcon | S3C2410_DCON_NORELOAD);
  471. }
  472. #define dmadbg2(x...)
  473. static irqreturn_t
  474. s3c2410_dma_irq(int irq, void *devpw)
  475. {
  476. struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw;
  477. struct s3c2410_dma_buf *buf;
  478. buf = chan->curr;
  479. dbg_showchan(chan);
  480. /* modify the channel state */
  481. switch (chan->load_state) {
  482. case S3C2410_DMALOAD_1RUNNING:
  483. /* TODO - if we are running only one buffer, we probably
  484. * want to reload here, and then worry about the buffer
  485. * callback */
  486. chan->load_state = S3C2410_DMALOAD_NONE;
  487. break;
  488. case S3C2410_DMALOAD_1LOADED:
  489. /* iirc, we should go back to NONE loaded here, we
  490. * had a buffer, and it was never verified as being
  491. * loaded.
  492. */
  493. chan->load_state = S3C2410_DMALOAD_NONE;
  494. break;
  495. case S3C2410_DMALOAD_1LOADED_1RUNNING:
  496. /* we'll worry about checking to see if another buffer is
  497. * ready after we've called back the owner. This should
  498. * ensure we do not wait around too long for the DMA
  499. * engine to start the next transfer
  500. */
  501. chan->load_state = S3C2410_DMALOAD_1LOADED;
  502. break;
  503. case S3C2410_DMALOAD_NONE:
  504. printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
  505. chan->number);
  506. break;
  507. default:
  508. printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
  509. chan->number, chan->load_state);
  510. break;
  511. }
  512. if (buf != NULL) {
  513. /* update the chain to make sure that if we load any more
  514. * buffers when we call the callback function, things should
  515. * work properly */
  516. chan->curr = buf->next;
  517. buf->next = NULL;
  518. if (buf->magic != BUF_MAGIC) {
  519. printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
  520. chan->number, __FUNCTION__, buf);
  521. return IRQ_HANDLED;
  522. }
  523. s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK);
  524. /* free resouces */
  525. s3c2410_dma_freebuf(buf);
  526. } else {
  527. }
  528. /* only reload if the channel is still running... our buffer done
  529. * routine may have altered the state by requesting the dma channel
  530. * to stop or shutdown... */
  531. /* todo: check that when the channel is shut-down from inside this
  532. * function, we cope with unsetting reload, etc */
  533. if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) {
  534. unsigned long flags;
  535. switch (chan->load_state) {
  536. case S3C2410_DMALOAD_1RUNNING:
  537. /* don't need to do anything for this state */
  538. break;
  539. case S3C2410_DMALOAD_NONE:
  540. /* can load buffer immediately */
  541. break;
  542. case S3C2410_DMALOAD_1LOADED:
  543. if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
  544. /* flag error? */
  545. printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n",
  546. chan->number, __FUNCTION__);
  547. return IRQ_HANDLED;
  548. }
  549. break;
  550. case S3C2410_DMALOAD_1LOADED_1RUNNING:
  551. goto no_load;
  552. default:
  553. printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
  554. chan->number, chan->load_state);
  555. return IRQ_HANDLED;
  556. }
  557. local_irq_save(flags);
  558. s3c2410_dma_loadbuffer(chan, chan->next);
  559. local_irq_restore(flags);
  560. } else {
  561. s3c2410_dma_lastxfer(chan);
  562. /* see if we can stop this channel.. */
  563. if (chan->load_state == S3C2410_DMALOAD_NONE) {
  564. pr_debug("dma%d: end of transfer, stopping channel (%ld)\n",
  565. chan->number, jiffies);
  566. s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL,
  567. S3C2410_DMAOP_STOP);
  568. }
  569. }
  570. no_load:
  571. return IRQ_HANDLED;
  572. }
  573. static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel);
  574. /* s3c2410_request_dma
  575. *
  576. * get control of an dma channel
  577. */
  578. int s3c2410_dma_request(unsigned int channel,
  579. struct s3c2410_dma_client *client,
  580. void *dev)
  581. {
  582. struct s3c2410_dma_chan *chan;
  583. unsigned long flags;
  584. int err;
  585. pr_debug("dma%d: %s: client=%s, dev=%p\n",
  586. channel,__FUNCTION__ ,client->name, dev);
  587. local_irq_save(flags);
  588. chan = s3c2410_dma_map_channel(channel);
  589. if (chan == NULL) {
  590. local_irq_restore(flags);
  591. return -EBUSY;
  592. }
  593. dbg_showchan(chan);
  594. chan->client = client;
  595. chan->in_use = 1;
  596. if (!chan->irq_claimed) {
  597. pr_debug("dma%d: %s : requesting irq %d\n",
  598. channel, __FUNCTION__, chan->irq);
  599. chan->irq_claimed = 1;
  600. local_irq_restore(flags);
  601. err = request_irq(chan->irq, s3c2410_dma_irq, IRQF_DISABLED,
  602. client->name, (void *)chan);
  603. local_irq_save(flags);
  604. if (err) {
  605. chan->in_use = 0;
  606. chan->irq_claimed = 0;
  607. local_irq_restore(flags);
  608. printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
  609. client->name, chan->irq, chan->number);
  610. return err;
  611. }
  612. chan->irq_enabled = 1;
  613. }
  614. local_irq_restore(flags);
  615. /* need to setup */
  616. pr_debug("%s: channel initialised, %p\n", __FUNCTION__, chan);
  617. return 0;
  618. }
  619. EXPORT_SYMBOL(s3c2410_dma_request);
  620. /* s3c2410_dma_free
  621. *
  622. * release the given channel back to the system, will stop and flush
  623. * any outstanding transfers, and ensure the channel is ready for the
  624. * next claimant.
  625. *
  626. * Note, although a warning is currently printed if the freeing client
  627. * info is not the same as the registrant's client info, the free is still
  628. * allowed to go through.
  629. */
  630. int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
  631. {
  632. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  633. unsigned long flags;
  634. if (chan == NULL)
  635. return -EINVAL;
  636. local_irq_save(flags);
  637. if (chan->client != client) {
  638. printk(KERN_WARNING "dma%d: possible free from different client (channel %p, passed %p)\n",
  639. channel, chan->client, client);
  640. }
  641. /* sort out stopping and freeing the channel */
  642. if (chan->state != S3C2410_DMA_IDLE) {
  643. pr_debug("%s: need to stop dma channel %p\n",
  644. __FUNCTION__, chan);
  645. /* possibly flush the channel */
  646. s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
  647. }
  648. chan->client = NULL;
  649. chan->in_use = 0;
  650. if (chan->irq_claimed)
  651. free_irq(chan->irq, (void *)chan);
  652. chan->irq_claimed = 0;
  653. if (!(channel & DMACH_LOW_LEVEL))
  654. dma_chan_map[channel] = NULL;
  655. local_irq_restore(flags);
  656. return 0;
  657. }
  658. EXPORT_SYMBOL(s3c2410_dma_free);
  659. static int s3c2410_dma_dostop(struct s3c2410_dma_chan *chan)
  660. {
  661. unsigned long flags;
  662. unsigned long tmp;
  663. pr_debug("%s:\n", __FUNCTION__);
  664. dbg_showchan(chan);
  665. local_irq_save(flags);
  666. s3c2410_dma_call_op(chan, S3C2410_DMAOP_STOP);
  667. tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
  668. tmp |= S3C2410_DMASKTRIG_STOP;
  669. //tmp &= ~S3C2410_DMASKTRIG_ON;
  670. dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp);
  671. #if 0
  672. /* should also clear interrupts, according to WinCE BSP */
  673. tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
  674. tmp |= S3C2410_DCON_NORELOAD;
  675. dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
  676. #endif
  677. /* should stop do this, or should we wait for flush? */
  678. chan->state = S3C2410_DMA_IDLE;
  679. chan->load_state = S3C2410_DMALOAD_NONE;
  680. local_irq_restore(flags);
  681. return 0;
  682. }
  683. static void s3c2410_dma_waitforstop(struct s3c2410_dma_chan *chan)
  684. {
  685. unsigned long tmp;
  686. unsigned int timeout = 0x10000;
  687. while (timeout-- > 0) {
  688. tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
  689. if (!(tmp & S3C2410_DMASKTRIG_ON))
  690. return;
  691. }
  692. pr_debug("dma%d: failed to stop?\n", chan->number);
  693. }
  694. /* s3c2410_dma_flush
  695. *
  696. * stop the channel, and remove all current and pending transfers
  697. */
  698. static int s3c2410_dma_flush(struct s3c2410_dma_chan *chan)
  699. {
  700. struct s3c2410_dma_buf *buf, *next;
  701. unsigned long flags;
  702. pr_debug("%s: chan %p (%d)\n", __FUNCTION__, chan, chan->number);
  703. dbg_showchan(chan);
  704. local_irq_save(flags);
  705. if (chan->state != S3C2410_DMA_IDLE) {
  706. pr_debug("%s: stopping channel...\n", __FUNCTION__ );
  707. s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
  708. }
  709. buf = chan->curr;
  710. if (buf == NULL)
  711. buf = chan->next;
  712. chan->curr = chan->next = chan->end = NULL;
  713. if (buf != NULL) {
  714. for ( ; buf != NULL; buf = next) {
  715. next = buf->next;
  716. pr_debug("%s: free buffer %p, next %p\n",
  717. __FUNCTION__, buf, buf->next);
  718. s3c2410_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
  719. s3c2410_dma_freebuf(buf);
  720. }
  721. }
  722. dbg_showregs(chan);
  723. s3c2410_dma_waitforstop(chan);
  724. #if 0
  725. /* should also clear interrupts, according to WinCE BSP */
  726. {
  727. unsigned long tmp;
  728. tmp = dma_rdreg(chan, S3C2410_DMA_DCON);
  729. tmp |= S3C2410_DCON_NORELOAD;
  730. dma_wrreg(chan, S3C2410_DMA_DCON, tmp);
  731. }
  732. #endif
  733. dbg_showregs(chan);
  734. local_irq_restore(flags);
  735. return 0;
  736. }
  737. static int s3c2410_dma_started(struct s3c2410_dma_chan *chan)
  738. {
  739. unsigned long flags;
  740. local_irq_save(flags);
  741. dbg_showchan(chan);
  742. /* if we've only loaded one buffer onto the channel, then chec
  743. * to see if we have another, and if so, try and load it so when
  744. * the first buffer is finished, the new one will be loaded onto
  745. * the channel */
  746. if (chan->next != NULL) {
  747. if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
  748. if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
  749. pr_debug("%s: buff not yet loaded, no more todo\n",
  750. __FUNCTION__);
  751. } else {
  752. chan->load_state = S3C2410_DMALOAD_1RUNNING;
  753. s3c2410_dma_loadbuffer(chan, chan->next);
  754. }
  755. } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
  756. s3c2410_dma_loadbuffer(chan, chan->next);
  757. }
  758. }
  759. local_irq_restore(flags);
  760. return 0;
  761. }
  762. int
  763. s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
  764. {
  765. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  766. if (chan == NULL)
  767. return -EINVAL;
  768. switch (op) {
  769. case S3C2410_DMAOP_START:
  770. return s3c2410_dma_start(chan);
  771. case S3C2410_DMAOP_STOP:
  772. return s3c2410_dma_dostop(chan);
  773. case S3C2410_DMAOP_PAUSE:
  774. case S3C2410_DMAOP_RESUME:
  775. return -ENOENT;
  776. case S3C2410_DMAOP_FLUSH:
  777. return s3c2410_dma_flush(chan);
  778. case S3C2410_DMAOP_STARTED:
  779. return s3c2410_dma_started(chan);
  780. case S3C2410_DMAOP_TIMEOUT:
  781. return 0;
  782. }
  783. return -ENOENT; /* unknown, don't bother */
  784. }
  785. EXPORT_SYMBOL(s3c2410_dma_ctrl);
  786. /* DMA configuration for each channel
  787. *
  788. * DISRCC -> source of the DMA (AHB,APB)
  789. * DISRC -> source address of the DMA
  790. * DIDSTC -> destination of the DMA (AHB,APD)
  791. * DIDST -> destination address of the DMA
  792. */
  793. /* s3c2410_dma_config
  794. *
  795. * xfersize: size of unit in bytes (1,2,4)
  796. * dcon: base value of the DCONx register
  797. */
  798. int s3c2410_dma_config(dmach_t channel,
  799. int xferunit,
  800. int dcon)
  801. {
  802. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  803. pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
  804. __FUNCTION__, channel, xferunit, dcon);
  805. if (chan == NULL)
  806. return -EINVAL;
  807. pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon);
  808. dcon |= chan->dcon & dma_sel.dcon_mask;
  809. pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon);
  810. dcon &= ~S3C2410_DCON_DSZ_MASK;
  811. switch (xferunit) {
  812. case 1:
  813. dcon |= S3C2410_DCON_BYTE;
  814. break;
  815. case 2:
  816. dcon |= S3C2410_DCON_HALFWORD;
  817. break;
  818. case 4:
  819. dcon |= S3C2410_DCON_WORD;
  820. break;
  821. default:
  822. pr_debug("%s: bad transfer size %d\n", __FUNCTION__, xferunit);
  823. return -EINVAL;
  824. }
  825. dcon |= S3C2410_DCON_HWTRIG;
  826. dcon |= S3C2410_DCON_INTREQ;
  827. pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
  828. chan->dcon = dcon;
  829. chan->xfer_unit = xferunit;
  830. return 0;
  831. }
  832. EXPORT_SYMBOL(s3c2410_dma_config);
  833. int s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
  834. {
  835. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  836. if (chan == NULL)
  837. return -EINVAL;
  838. pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
  839. chan->flags = flags;
  840. return 0;
  841. }
  842. EXPORT_SYMBOL(s3c2410_dma_setflags);
  843. /* do we need to protect the settings of the fields from
  844. * irq?
  845. */
  846. int s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
  847. {
  848. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  849. if (chan == NULL)
  850. return -EINVAL;
  851. pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
  852. chan->op_fn = rtn;
  853. return 0;
  854. }
  855. EXPORT_SYMBOL(s3c2410_dma_set_opfn);
  856. int s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
  857. {
  858. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  859. if (chan == NULL)
  860. return -EINVAL;
  861. pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
  862. chan->callback_fn = rtn;
  863. return 0;
  864. }
  865. EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
  866. /* s3c2410_dma_devconfig
  867. *
  868. * configure the dma source/destination hardware type and address
  869. *
  870. * source: S3C2410_DMASRC_HW: source is hardware
  871. * S3C2410_DMASRC_MEM: source is memory
  872. *
  873. * hwcfg: the value for xxxSTCn register,
  874. * bit 0: 0=increment pointer, 1=leave pointer
  875. * bit 1: 0=source is AHB, 1=source is APB
  876. *
  877. * devaddr: physical address of the source
  878. */
  879. int s3c2410_dma_devconfig(int channel,
  880. enum s3c2410_dmasrc source,
  881. int hwcfg,
  882. unsigned long devaddr)
  883. {
  884. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  885. if (chan == NULL)
  886. return -EINVAL;
  887. pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
  888. __FUNCTION__, (int)source, hwcfg, devaddr);
  889. chan->source = source;
  890. chan->dev_addr = devaddr;
  891. switch (source) {
  892. case S3C2410_DMASRC_HW:
  893. /* source is hardware */
  894. pr_debug("%s: hw source, devaddr=%08lx, hwcfg=%d\n",
  895. __FUNCTION__, devaddr, hwcfg);
  896. dma_wrreg(chan, S3C2410_DMA_DISRCC, hwcfg & 3);
  897. dma_wrreg(chan, S3C2410_DMA_DISRC, devaddr);
  898. dma_wrreg(chan, S3C2410_DMA_DIDSTC, (0<<1) | (0<<0));
  899. chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DIDST);
  900. return 0;
  901. case S3C2410_DMASRC_MEM:
  902. /* source is memory */
  903. pr_debug( "%s: mem source, devaddr=%08lx, hwcfg=%d\n",
  904. __FUNCTION__, devaddr, hwcfg);
  905. dma_wrreg(chan, S3C2410_DMA_DISRCC, (0<<1) | (0<<0));
  906. dma_wrreg(chan, S3C2410_DMA_DIDST, devaddr);
  907. dma_wrreg(chan, S3C2410_DMA_DIDSTC, hwcfg & 3);
  908. chan->addr_reg = dma_regaddr(chan, S3C2410_DMA_DISRC);
  909. return 0;
  910. case S3C_DMA_MEM2MEM:
  911. case S3C_DMA_PER2PER:
  912. return 0;
  913. }
  914. printk(KERN_ERR "dma%d: invalid source type (%d)\n", channel, source);
  915. return -EINVAL;
  916. }
  917. EXPORT_SYMBOL(s3c2410_dma_devconfig);
  918. /* s3c2410_dma_getposition
  919. *
  920. * returns the current transfer points for the dma source and destination
  921. */
  922. int s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
  923. {
  924. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  925. if (chan == NULL)
  926. return -EINVAL;
  927. if (src != NULL)
  928. *src = dma_rdreg(chan, S3C2410_DMA_DCSRC);
  929. if (dst != NULL)
  930. *dst = dma_rdreg(chan, S3C2410_DMA_DCDST);
  931. return 0;
  932. }
  933. EXPORT_SYMBOL(s3c2410_dma_getposition);
  934. /* system device class */
  935. #ifdef CONFIG_PM
  936. static int s3c2410_dma_suspend(struct sys_device *dev, pm_message_t state)
  937. {
  938. struct s3c2410_dma_chan *cp = container_of(dev, struct s3c2410_dma_chan, dev);
  939. printk(KERN_DEBUG "suspending dma channel %d\n", cp->number);
  940. if (dma_rdreg(cp, S3C2410_DMA_DMASKTRIG) & S3C2410_DMASKTRIG_ON) {
  941. /* the dma channel is still working, which is probably
  942. * a bad thing to do over suspend/resume. We stop the
  943. * channel and assume that the client is either going to
  944. * retry after resume, or that it is broken.
  945. */
  946. printk(KERN_INFO "dma: stopping channel %d due to suspend\n",
  947. cp->number);
  948. s3c2410_dma_dostop(cp);
  949. }
  950. return 0;
  951. }
  952. static int s3c2410_dma_resume(struct sys_device *dev)
  953. {
  954. return 0;
  955. }
  956. #else
  957. #define s3c2410_dma_suspend NULL
  958. #define s3c2410_dma_resume NULL
  959. #endif /* CONFIG_PM */
  960. struct sysdev_class dma_sysclass = {
  961. set_kset_name("s3c24xx-dma"),
  962. .suspend = s3c2410_dma_suspend,
  963. .resume = s3c2410_dma_resume,
  964. };
  965. /* kmem cache implementation */
  966. static void s3c2410_dma_cache_ctor(void *p, struct kmem_cache *c, unsigned long f)
  967. {
  968. memset(p, 0, sizeof(struct s3c2410_dma_buf));
  969. }
  970. /* initialisation code */
  971. static int __init s3c24xx_dma_sysclass_init(void)
  972. {
  973. int ret = sysdev_class_register(&dma_sysclass);
  974. if (ret != 0)
  975. printk(KERN_ERR "dma sysclass registration failed\n");
  976. return ret;
  977. }
  978. core_initcall(s3c24xx_dma_sysclass_init);
  979. static int __init s3c24xx_dma_sysdev_register(void)
  980. {
  981. struct s3c2410_dma_chan *cp = s3c2410_chans;
  982. int channel, ret;
  983. for (channel = 0; channel < dma_channels; cp++, channel++) {
  984. cp->dev.cls = &dma_sysclass;
  985. cp->dev.id = channel;
  986. ret = sysdev_register(&cp->dev);
  987. if (ret) {
  988. printk(KERN_ERR "error registering dev for dma %d\n",
  989. channel);
  990. return ret;
  991. }
  992. }
  993. return 0;
  994. }
  995. late_initcall(s3c24xx_dma_sysdev_register);
  996. int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
  997. unsigned int stride)
  998. {
  999. struct s3c2410_dma_chan *cp;
  1000. int channel;
  1001. int ret;
  1002. printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n");
  1003. dma_channels = channels;
  1004. dma_base = ioremap(S3C24XX_PA_DMA, stride * channels);
  1005. if (dma_base == NULL) {
  1006. printk(KERN_ERR "dma failed to remap register block\n");
  1007. return -ENOMEM;
  1008. }
  1009. dma_kmem = kmem_cache_create("dma_desc",
  1010. sizeof(struct s3c2410_dma_buf), 0,
  1011. SLAB_HWCACHE_ALIGN,
  1012. s3c2410_dma_cache_ctor, NULL);
  1013. if (dma_kmem == NULL) {
  1014. printk(KERN_ERR "dma failed to make kmem cache\n");
  1015. ret = -ENOMEM;
  1016. goto err;
  1017. }
  1018. for (channel = 0; channel < channels; channel++) {
  1019. cp = &s3c2410_chans[channel];
  1020. memset(cp, 0, sizeof(struct s3c2410_dma_chan));
  1021. /* dma channel irqs are in order.. */
  1022. cp->number = channel;
  1023. #if defined(CONFIG_CPU_S3C2450)|| defined(CONFIG_CPU_S3C2416)
  1024. if(channel == 6){
  1025. irq = irq + 5;
  1026. cp->irq = channel + irq;
  1027. }
  1028. else
  1029. cp->irq = channel + irq;
  1030. #else
  1031. cp->irq = channel + irq;
  1032. #endif
  1033. cp->regs = dma_base + (channel * stride);
  1034. /* point current stats somewhere */
  1035. cp->stats = &cp->stats_store;
  1036. cp->stats_store.timeout_shortest = LONG_MAX;
  1037. /* basic channel configuration */
  1038. cp->load_timeout = 1<<18;
  1039. printk("DMA channel %d at %p, irq %d\n",
  1040. cp->number, cp->regs, cp->irq);
  1041. }
  1042. return 0;
  1043. err:
  1044. kmem_cache_destroy(dma_kmem);
  1045. iounmap(dma_base);
  1046. dma_base = NULL;
  1047. return ret;
  1048. }
  1049. int s3c2410_dma_init(void)
  1050. {
  1051. return s3c24xx_dma_init(4, IRQ_DMA0, 0x40);
  1052. }
  1053. static inline int is_channel_valid(unsigned int channel)
  1054. {
  1055. return (channel & DMA_CH_VALID);
  1056. }
  1057. static struct s3c24xx_dma_order *dma_order;
  1058. /* s3c2410_dma_map_channel()
  1059. *
  1060. * turn the virtual channel number into a real, and un-used hardware
  1061. * channel.
  1062. *
  1063. * first, try the dma ordering given to us by either the relevant
  1064. * dma code, or the board. Then just find the first usable free
  1065. * channel
  1066. */
  1067. static struct s3c2410_dma_chan *s3c2410_dma_map_channel(int channel)
  1068. {
  1069. struct s3c24xx_dma_order_ch *ord = NULL;
  1070. struct s3c24xx_dma_map *ch_map;
  1071. struct s3c2410_dma_chan *dmach;
  1072. int ch;
  1073. if (dma_sel.map == NULL || channel > dma_sel.map_size)
  1074. return NULL;
  1075. ch_map = dma_sel.map + channel;
  1076. /* first, try the board mapping */
  1077. if (dma_order) {
  1078. ord = &dma_order->channels[channel];
  1079. for (ch = 0; ch < dma_channels; ch++) {
  1080. if (!is_channel_valid(ord->list[ch]))
  1081. continue;
  1082. if (s3c2410_chans[ord->list[ch]].in_use == 0) {
  1083. ch = ord->list[ch] & ~DMA_CH_VALID;
  1084. goto found;
  1085. }
  1086. }
  1087. if (ord->flags & DMA_CH_NEVER)
  1088. return NULL;
  1089. }
  1090. /* second, search the channel map for first free */
  1091. for (ch = 0; ch < dma_channels; ch++) {
  1092. if (!is_channel_valid(ch_map->channels[ch]))
  1093. continue;
  1094. if (s3c2410_chans[ch].in_use == 0) {
  1095. pr_debug("mapped channel %d to %d\n", channel, ch);
  1096. break;
  1097. }
  1098. }
  1099. if (ch >= dma_channels)
  1100. return NULL;
  1101. /* update our channel mapping */
  1102. found:
  1103. dmach = &s3c2410_chans[ch];
  1104. dma_chan_map[channel] = dmach;
  1105. /* select the channel */
  1106. (dma_sel.select)(dmach, ch_map);
  1107. return dmach;
  1108. }
  1109. static int s3c24xx_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
  1110. {
  1111. return 0;
  1112. }
  1113. int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
  1114. {
  1115. struct s3c24xx_dma_map *nmap;
  1116. size_t map_sz = sizeof(*nmap) * sel->map_size;
  1117. int ptr;
  1118. nmap = kmalloc(map_sz, GFP_KERNEL);
  1119. if (nmap == NULL)
  1120. return -ENOMEM;
  1121. memcpy(nmap, sel->map, map_sz);
  1122. memcpy(&dma_sel, sel, sizeof(*sel));
  1123. dma_sel.map = nmap;
  1124. for (ptr = 0; ptr < sel->map_size; ptr++)
  1125. s3c24xx_dma_check_entry(nmap+ptr, ptr);
  1126. return 0;
  1127. }
  1128. int __init s3c24xx_dma_order_set(struct s3c24xx_dma_order *ord)
  1129. {
  1130. struct s3c24xx_dma_order *nord = dma_order;
  1131. if (nord == NULL)
  1132. nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
  1133. if (nord == NULL) {
  1134. printk(KERN_ERR "no memory to store dma channel order\n");
  1135. return -ENOMEM;
  1136. }
  1137. dma_order = nord;
  1138. memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
  1139. return 0;
  1140. }