dma-pl080.c 39 KB

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  1. /* linux/arch/arm/plat-s3c24xx/dma-pl080.c
  2. *
  3. * Copyright (c) 2003-2005,2006 Samsung Electronics
  4. *
  5. * S3C6400 DMA core
  6. *
  7. * http://www.samsung.com/
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2 as
  11. * published by the Free Software Foundation.
  12. */
  13. #ifdef CONFIG_S3C_DMA_DEBUG
  14. #define DEBUG
  15. #endif
  16. #include <linux/module.h>
  17. #include <linux/init.h>
  18. #include <linux/sched.h>
  19. #include <linux/spinlock.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/sysdev.h>
  22. #include <linux/slab.h>
  23. #include <linux/errno.h>
  24. #include <linux/delay.h>
  25. #include <asm/system.h>
  26. #include <asm/irq.h>
  27. #include <asm/hardware.h>
  28. #include <asm/io.h>
  29. #include <asm/dma.h>
  30. #include <asm/arch/regs-s3c6400-clock.h>
  31. #include <asm/mach/dma.h>
  32. #include <asm/arch/map.h>
  33. #include <asm/plat-s3c24xx/dma.h>
  34. /* io map for dma */
  35. static void __iomem *dma_base;
  36. static struct kmem_cache *dma_kmem;
  37. static int dma_channels;
  38. struct s3c24xx_dma_selection dma_sel;
  39. static struct s3c2410_dma_chan *dma_chan_map[DMACH_MAX];
  40. /* dma channel state information */
  41. struct s3c2410_dma_chan s3c_dma_chans[S3C2410_DMA_CHANNELS];
  42. s3c_dma_controller_t s3c_dma_cntlrs[S3C_DMA_CONTROLLERS];
  43. #undef pr_debug
  44. //#define dma_dbg
  45. #ifdef dma_dbg
  46. #define sh_printk(fmt...) printk( fmt)
  47. #define pr_debug(fmt...) printk( fmt)
  48. #else
  49. #define sh_printk(fmt...)
  50. #define pr_debug(fmt...)
  51. #endif
  52. /* debugging functions */
  53. #define BUF_MAGIC (0xcafebabe)
  54. #define dmawarn(fmt...) printk(KERN_DEBUG fmt)
  55. #define dma_regaddr(chan, reg) ((chan)->regs + (reg))
  56. #define dma_wrreg(chan, reg, val) writel((val), (chan)->regs + (reg))
  57. #define dma_rdreg(chan, reg) readl((chan)->regs + (reg))
  58. #define dbg_showregs(chan) do { } while(0)
  59. #define dbg_showchan(chan) do { } while(0)
  60. void s3c_dma_dump(int dcon_num, int channel)
  61. {
  62. unsigned long tmp;
  63. s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
  64. tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_STATUS);
  65. printk("%d dcon_num %d subchnnel INT_STATUS %lx\n", dcon_num, channel, tmp);
  66. tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCSTATUS);
  67. printk("%d dcon_num %d subchnnel INT_TCSTATUS %lx\n", dcon_num, channel, tmp);
  68. tmp = dma_rdreg(dma_controller, S3C_DMAC_ENBLD_CHANNELS);
  69. printk("%d dcon_num %d subchnnel ENBLD_CHANNELS %lx\n", dcon_num, channel, tmp);
  70. tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
  71. printk("%d dcon_num %d subchnnel DMAC_CONFIGUARATION %lx\n", dcon_num, channel, tmp);
  72. tmp = dma_rdreg(dma_controller, S3C_DMAC_CSRCADDR(channel));
  73. printk("%d dcon_num %d subchnnel SRCADDRESS %lx\n", dcon_num, channel, tmp);
  74. tmp = dma_rdreg(dma_controller, S3C_DMAC_CDESTADDR(channel));
  75. printk("%d dcon_num %d subchnnel DESTADDRESS %lx\n", dcon_num, channel, tmp);
  76. tmp = dma_rdreg(dma_controller, S3C_DMAC_CLLI(channel));
  77. printk("%d dcon_num %d subchnnel LLI %lx\n", dcon_num, channel, tmp);
  78. tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL0(channel));
  79. printk("%d dcon_num %d subchnnel CCONTROL0 %lx\n", dcon_num, channel, tmp);
  80. tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL1(channel));
  81. printk("%d dcon_num %d subchnnel CCONTROL1 %lx\n", dcon_num, channel, tmp);
  82. tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel));
  83. printk("%d dcon_num %d subchnnel CH CONFIGUARATION %lx\n", dcon_num, channel, tmp);
  84. }
  85. /* lookup_dma_channel
  86. *
  87. * change the dma channel number given into a real dma channel id
  88. */
  89. static struct s3c2410_dma_chan *lookup_dma_channel(unsigned int channel)
  90. {
  91. if (channel & DMACH_LOW_LEVEL)
  92. return &s3c_dma_chans[channel & ~DMACH_LOW_LEVEL];
  93. else
  94. return dma_chan_map[channel];
  95. }
  96. /* s3c_dma_stats_timeout
  97. *
  98. * Update DMA stats from timeout info
  99. */
  100. static void
  101. s3c_dma_stats_timeout(struct s3c2410_dma_stats * stats, int val)
  102. {
  103. if (stats == NULL)
  104. return;
  105. if (val > stats->timeout_longest)
  106. stats->timeout_longest = val;
  107. if (val < stats->timeout_shortest)
  108. stats->timeout_shortest = val;
  109. stats->timeout_avg += val;
  110. }
  111. void
  112. s3c_enable_dmac(unsigned int dcon_num)
  113. {
  114. s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
  115. dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, S3C_DMA_CONTROLLER_ENABLE);
  116. }
  117. void
  118. s3c_disable_dmac(unsigned int dcon_num)
  119. {
  120. unsigned long tmp;
  121. s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
  122. tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
  123. tmp &= ~S3C_DMA_CONTROLLER_ENABLE;
  124. dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, tmp);
  125. }
  126. void
  127. s3c_clear_interrupts (int dcon_num, int channel)
  128. {
  129. unsigned long tmp;
  130. s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
  131. tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCCLEAR);
  132. tmp |= (1 << channel);
  133. dma_wrreg(dma_controller, S3C_DMAC_INT_TCCLEAR, tmp);
  134. tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_ERRORCLEAR);
  135. tmp |= (1 << channel);
  136. dma_wrreg(dma_controller, S3C_DMAC_INT_ERRORCLEAR, tmp);
  137. }
  138. /* s3c_dma_waitforload
  139. *
  140. * wait for the DMA engine to load a buffer, and update the state accordingly
  141. */
  142. static int
  143. s3c_dma_waitforload(struct s3c2410_dma_chan *chan, int line)
  144. {
  145. int timeout = chan->load_timeout;
  146. int took;
  147. pr_debug("%s channel number : %d\n", __FUNCTION__, chan->number);
  148. if (chan->load_state != S3C2410_DMALOAD_1LOADED) {
  149. printk(KERN_ERR
  150. "dma%d: s3c_dma_waitforload() called in loadstate %d from line %d\n",
  151. chan->number, chan->load_state, line);
  152. return 0;
  153. }
  154. if (chan->stats != NULL)
  155. chan->stats->loads++;
  156. while (--timeout > 0) {
  157. if ((dma_rdreg(chan->dma_con, S3C_DMAC_ENBLD_CHANNELS)) & (0x1 << chan->number)) {
  158. took = chan->load_timeout - timeout;
  159. s3c_dma_stats_timeout(chan->stats, took);
  160. switch (chan->load_state) {
  161. case S3C2410_DMALOAD_1LOADED:
  162. chan->load_state = S3C2410_DMALOAD_1RUNNING;
  163. break;
  164. default:
  165. printk(KERN_ERR
  166. "dma%d: unknown load_state in s3c_dma_waitforload() %d\n",
  167. chan->number, chan->load_state);
  168. }
  169. return 1;
  170. }
  171. }
  172. if (chan->stats != NULL) {
  173. chan->stats->timeout_failed++;
  174. }
  175. return 0;
  176. }
  177. /* s3c_dma_loadbuffer
  178. *
  179. * load a buffer, and update the channel state
  180. */
  181. static inline int
  182. s3c_dma_loadbuffer(struct s3c2410_dma_chan *chan,
  183. struct s3c2410_dma_buf *buf)
  184. {
  185. unsigned long reload;
  186. pr_debug("s3c_chan_loadbuffer: loading buffer %p (0x%08lx,0x%06x)\n",
  187. buf, (unsigned long) buf->data, buf->size);
  188. if (buf == NULL) {
  189. dmawarn("buffer is NULL\n");
  190. return -EINVAL;
  191. }
  192. /* check the state of the channel before we do anything */
  193. if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
  194. dmawarn("load_state is S3C2410_DMALOAD_1LOADED\n");
  195. reload = (buf->next == NULL) ? S3C2410_DCON_NORELOAD : 0;
  196. }
  197. if (chan->load_state == S3C2410_DMALOAD_1LOADED_1RUNNING) {
  198. dmawarn("state is S3C2410_DMALOAD_1LOADED_1RUNNING\n");
  199. reload = S3C2410_DCON_AUTORELOAD;
  200. }
  201. writel(buf->data, chan->addr_reg);
  202. pr_debug("%s: DMA control0 - %08x\n", __FUNCTION__, chan->dcon);
  203. pr_debug("%s: DMA control1 - %08x\n", __FUNCTION__, (buf->size / chan->xfer_unit));
  204. dma_wrreg(chan, S3C_DMAC_CxCONTROL0, chan->dcon);
  205. dma_wrreg(chan, S3C_DMAC_CxCONTROL1, (buf->size / chan->xfer_unit));
  206. chan->next = buf->next;
  207. /* update the state of the channel */
  208. switch (chan->load_state) {
  209. case S3C2410_DMALOAD_NONE:
  210. chan->load_state = S3C2410_DMALOAD_1LOADED;
  211. break;
  212. case S3C2410_DMALOAD_1RUNNING:
  213. chan->load_state = S3C2410_DMALOAD_1LOADED_1RUNNING;
  214. break;
  215. default:
  216. dmawarn("dmaload: unknown state %d in loadbuffer\n", chan->load_state);
  217. break;
  218. }
  219. return 0;
  220. }
  221. /* s3c_dma_call_op
  222. *
  223. * small routine to call the o routine with the given op if it has been
  224. * registered
  225. */
  226. static void
  227. s3c_dma_call_op (struct s3c2410_dma_chan * chan, enum s3c2410_chan_op op)
  228. {
  229. if (chan->op_fn != NULL) {
  230. (chan->op_fn) (chan, op);
  231. }
  232. }
  233. /* s3c_dma_buffdone
  234. *
  235. * small wrapper to check if callback routine needs to be called, and
  236. * if so, call it
  237. */
  238. static inline void
  239. s3c_dma_buffdone (struct s3c2410_dma_chan * chan, struct s3c2410_dma_buf * buf, enum s3c2410_dma_buffresult result)
  240. {
  241. pr_debug("callback_fn will be called=%p, buf=%p, id=%p, size=%d, result=%d\n",
  242. chan->callback_fn, buf, buf->id, buf->size, result);
  243. if (chan->callback_fn != NULL) {
  244. (chan->callback_fn) (chan, buf->id, buf->size, result);
  245. }
  246. }
  247. /* s3c_dma_start
  248. *
  249. * start a dma channel going
  250. */
  251. static int
  252. s3c_dma_start(struct s3c2410_dma_chan *chan)
  253. {
  254. unsigned long flags;
  255. pr_debug("s3c_start_dma: channel number=%d, index=%d\n", chan->number, chan->index);
  256. local_irq_save(flags);
  257. if (chan->state == S3C2410_DMA_RUNNING) {
  258. pr_debug("s3c_start_dma: already running (%d)\n", chan->state);
  259. local_irq_restore(flags);
  260. return 0;
  261. }
  262. chan->state = S3C2410_DMA_RUNNING;
  263. /* check wether there is anything to load, and if not, see
  264. * if we can find anything to load
  265. */
  266. if (chan->load_state == S3C2410_DMALOAD_NONE) {
  267. if (chan->next == NULL) {
  268. printk(KERN_ERR "dma%d: dcon_num has nothing loaded\n", chan->number);
  269. chan->state = S3C2410_DMA_IDLE;
  270. local_irq_restore(flags);
  271. return -EINVAL;
  272. }
  273. s3c_dma_loadbuffer(chan, chan->next);
  274. }
  275. dbg_showchan(chan);
  276. /* enable the channel */
  277. if (!chan->irq_enabled) {
  278. enable_irq(chan->irq);
  279. chan->irq_enabled = 1;
  280. }
  281. /* Get the DMA channel started ...*/
  282. dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, chan->config_flags);
  283. pr_debug("%s:wrote %08lx to S3C_DMAC_CxCONFIGURATION.\n",__FUNCTION__, chan->config_flags);
  284. /* Start the DMA operation on Peripheral */
  285. s3c_dma_call_op(chan, S3C2410_DMAOP_START);
  286. dbg_showchan(chan);
  287. /* if we've only loaded one buffer onto the channel, then chec
  288. * to see if we have another, and if so, try and load it so when
  289. * the first buffer is finished, the new one will be loaded onto
  290. * the channel */
  291. #if 0
  292. if (chan->next != NULL) {
  293. if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
  294. if (s3c2410_dma_waitforload(chan, __LINE__) == 0) {
  295. pr_debug("%s: buff not yet loaded, no more todo\n",
  296. __FUNCTION__);
  297. } else {
  298. chan->load_state = S3C2410_DMALOAD_1RUNNING;
  299. s3c2410_dma_loadbuffer(chan, chan->next);
  300. }
  301. } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
  302. s3c2410_dma_loadbuffer(chan, chan->next);
  303. }
  304. }
  305. #endif
  306. local_irq_restore(flags);
  307. return 0;
  308. }
  309. /* s3c_dma_canload
  310. *
  311. * work out if we can queue another buffer into the DMA engine
  312. */
  313. #if 0
  314. static int s3c_dma_canload(struct s3c2410_dma_chan * chan)
  315. {
  316. if (chan->load_state == S3C2410_DMALOAD_NONE || chan->load_state == S3C2410_DMALOAD_1RUNNING)
  317. return 1;
  318. return 0;
  319. }
  320. #endif
  321. /* s3c_dma_enqueue
  322. *
  323. * queue an given buffer for dma transfer.
  324. *
  325. * id the device driver's id information for this buffer
  326. * data the physical address of the buffer data
  327. * size the size of the buffer in bytes
  328. *
  329. * If the channel is not running, then the flag S3C2410_DMAF_AUTOSTART
  330. * is checked, and if set, the channel is started. If this flag isn't set,
  331. * then an error will be returned.
  332. *
  333. * It is possible to queue more than one DMA buffer onto a channel at
  334. * once, and the code will deal with the re-loading of the next buffer
  335. * when necessary.
  336. */
  337. int
  338. s3c2410_dma_enqueue(unsigned int channel, void *id,
  339. dma_addr_t data, int size)
  340. {
  341. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  342. struct s3c2410_dma_buf *buf;
  343. unsigned long flags;
  344. pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int) data, size);
  345. buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC);
  346. if (buf == NULL) {
  347. printk(KERN_ERR "dma<%d> no memory for buffer\n", channel);
  348. return -ENOMEM;
  349. }
  350. pr_debug("%s: new buffer %p\n", __FUNCTION__, buf);
  351. //dbg_showchan(chan);
  352. buf->next = NULL;
  353. buf->data = buf->ptr = data;
  354. buf->size = size;
  355. buf->id = id;
  356. buf->magic = BUF_MAGIC;
  357. local_irq_save(flags);
  358. if (chan->curr == NULL) {
  359. /* we've got nothing loaded... */
  360. pr_debug("%s: buffer %p queued onto empty channel\n", __FUNCTION__, buf);
  361. chan->curr = buf;
  362. chan->end = buf;
  363. chan->next = NULL;
  364. } else {
  365. pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n",
  366. chan->number, __FUNCTION__, buf);
  367. if (chan->end == NULL) /* In case of flushing */
  368. pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n",
  369. chan->number, __FUNCTION__, chan);
  370. else {
  371. chan->end->next = buf;
  372. chan->end = buf;
  373. }
  374. }
  375. /* if necessary, update the next buffer field */
  376. if (chan->next == NULL)
  377. chan->next = buf;
  378. /* check to see if we can load a buffer */
  379. if (chan->state == S3C2410_DMA_RUNNING) {
  380. if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) {
  381. if (s3c_dma_waitforload(chan, __LINE__) == 0) {
  382. printk(KERN_ERR "dma%d: loadbuffer:"
  383. "timeout loading buffer\n", chan->number);
  384. dbg_showchan(chan);
  385. local_irq_restore(flags);
  386. return -EINVAL;
  387. }
  388. }
  389. #if 0
  390. while (s3c_dma_canload(chan) && chan->next != NULL) {
  391. s3c_dma_loadbuffer(chan, chan->next);
  392. }
  393. #endif
  394. } else if (chan->state == S3C2410_DMA_IDLE) {
  395. if (chan->flags & S3C2410_DMAF_AUTOSTART) {
  396. s3c2410_dma_ctrl(channel, S3C2410_DMAOP_START);
  397. } else {
  398. pr_debug(KERN_DEBUG "loading onto stopped channel\n");
  399. }
  400. }
  401. local_irq_restore(flags);
  402. return 0;
  403. }
  404. EXPORT_SYMBOL(s3c2410_dma_enqueue);
  405. static inline void
  406. s3c_dma_freebuf (struct s3c2410_dma_buf * buf)
  407. {
  408. int magicok = (buf->magic == BUF_MAGIC);
  409. buf->magic = -1;
  410. if (magicok) {
  411. kmem_cache_free(dma_kmem, buf);
  412. } else {
  413. printk("s3c_dma_freebuf: buff %p with bad magic\n", buf);
  414. }
  415. }
  416. /* s3c_dma_lastxfer
  417. *
  418. * called when the system is out of buffers, to ensure that the channel
  419. * is prepared for shutdown.
  420. */
  421. static inline void
  422. s3c_dma_lastxfer(struct s3c2410_dma_chan *chan)
  423. {
  424. pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state %d\n", chan->number, chan->load_state);
  425. switch (chan->load_state) {
  426. case S3C2410_DMALOAD_NONE:
  427. pr_debug("DMA CH %d: s3c_dma_lastxfer: load_state : S3C2410_DMALOAD_NONE%d\n", chan->number);
  428. break;
  429. case S3C2410_DMALOAD_1LOADED:
  430. if (s3c_dma_waitforload(chan, __LINE__) == 0) {
  431. /* flag error? */
  432. printk(KERN_ERR "dma%d: timeout waiting for load\n", chan->number);
  433. return;
  434. }
  435. break;
  436. default:
  437. pr_debug("dma%d: lastxfer: unhandled load_state %d with no next",
  438. chan->number, chan->load_state);
  439. return;
  440. }
  441. /* hopefully this'll shut the damned thing up after the transfer... */
  442. //dma_wrreg(chan, S3C_DMA_DCON, chan->dcon | S3C_DCON_NORELOAD);
  443. }
  444. #define dmadbg2(x...)
  445. static irqreturn_t
  446. s3c_dma_irq (int irq, void *devpw)
  447. {
  448. unsigned int channel = 0, dcon_num, i;
  449. unsigned long tmp;
  450. s3c_dma_controller_t *dma_controller = (s3c_dma_controller_t *) devpw;
  451. struct s3c2410_dma_chan *chan=NULL;
  452. struct s3c2410_dma_buf *buf;
  453. dcon_num = dma_controller->number;
  454. tmp = dma_rdreg(dma_controller, S3C_DMAC_INT_TCSTATUS);
  455. pr_debug("# s3c_dma_irq: TC status : 0x%x\n", tmp);
  456. for (i = 0; i < S3C_CHANNELS_PER_DMA; i++) {
  457. if (tmp & 0x01) {
  458. pr_debug("# DMA Controller %d: requestor %d\n", dcon_num, i);
  459. channel = i;
  460. chan = &s3c_dma_chans[channel + dcon_num * S3C_CHANNELS_PER_DMA];
  461. pr_debug("# DMA channel number : %d, index : %d\n", chan->number, chan->index);
  462. buf = chan->curr;
  463. dbg_showchan(chan);
  464. /* modify the channel state */
  465. switch (chan->load_state) {
  466. case S3C2410_DMALOAD_1RUNNING:
  467. /* TODO - if we are running only one buffer, we probably
  468. * want to reload here, and then worry about the buffer
  469. * callback */
  470. chan->load_state = S3C2410_DMALOAD_NONE;
  471. break;
  472. case S3C2410_DMALOAD_1LOADED:
  473. /* iirc, we should go back to NONE loaded here, we
  474. * had a buffer, and it was never verified as being
  475. * loaded.
  476. */
  477. chan->load_state = S3C2410_DMALOAD_NONE;
  478. break;
  479. case S3C2410_DMALOAD_1LOADED_1RUNNING:
  480. /* we'll worry about checking to see if another buffer is
  481. * ready after we've called back the owner. This should
  482. * ensure we do not wait around too long for the DMA
  483. * engine to start the next transfer
  484. */
  485. chan->load_state = S3C2410_DMALOAD_1LOADED;
  486. break;
  487. case S3C2410_DMALOAD_NONE:
  488. printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n",
  489. chan->number);
  490. break;
  491. default:
  492. printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n",
  493. chan->number, chan->load_state);
  494. break;
  495. }
  496. if (buf != NULL) {
  497. /* update the chain to make sure that if we load any more
  498. * buffers when we call the callback function, things should
  499. * work properly */
  500. chan->curr = buf->next;
  501. buf->next = NULL;
  502. if (buf->magic != BUF_MAGIC) {
  503. printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n",
  504. chan->number, __FUNCTION__, buf);
  505. goto next_channel;
  506. }
  507. s3c_dma_buffdone(chan, buf, S3C2410_RES_OK);
  508. /* free resouces */
  509. s3c_dma_freebuf(buf);
  510. } else {
  511. }
  512. if (chan->next != NULL) {
  513. unsigned long flags;
  514. switch (chan->load_state) {
  515. case S3C2410_DMALOAD_1RUNNING:
  516. /* don't need to do anything for this state */
  517. break;
  518. case S3C2410_DMALOAD_NONE:
  519. /* can load buffer immediately */
  520. break;
  521. case S3C2410_DMALOAD_1LOADED:
  522. if (s3c_dma_waitforload(chan, __LINE__) == 0) {
  523. /* flag error? */
  524. printk(KERN_ERR "dma%d: timeout waiting for load\n",
  525. chan->number);
  526. goto next_channel;
  527. }
  528. break;
  529. case S3C2410_DMALOAD_1LOADED_1RUNNING:
  530. goto next_channel;
  531. default:
  532. printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n",
  533. chan->number, chan->load_state);
  534. goto next_channel;
  535. }
  536. local_irq_save(flags);
  537. s3c_dma_loadbuffer(chan, chan->next);
  538. //shaju added for dbg
  539. dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, chan->config_flags);
  540. local_irq_restore(flags);
  541. } else {
  542. s3c_dma_lastxfer(chan);
  543. /* see if we can stop this channel.. */
  544. if (chan->load_state == S3C2410_DMALOAD_NONE) {
  545. pr_debug("# DMA CH %d(index:%d): end of transfer, stopping channel (%ld)\n",
  546. chan->number, chan->index, jiffies);
  547. s3c2410_dma_ctrl(chan->index | DMACH_LOW_LEVEL, S3C2410_DMAOP_STOP);
  548. }
  549. }
  550. }
  551. next_channel:
  552. tmp >>= 1;
  553. }
  554. s3c_clear_interrupts(chan->dma_con->number, chan->number);
  555. return IRQ_HANDLED;
  556. }
  557. static struct s3c2410_dma_chan *s3c_dma_map_channel(int channel);
  558. /* s3c_request_dma
  559. *
  560. * get control of an dma channel
  561. */
  562. int
  563. s3c2410_dma_request(unsigned int channel,
  564. struct s3c2410_dma_client *client,
  565. void *dev)
  566. {
  567. struct s3c2410_dma_chan *chan;
  568. unsigned long flags;
  569. int err;
  570. pr_debug("DMA CH %d: s3c2410_request_dma: client=%s, dev=%p\n",
  571. channel, client->name, dev);
  572. local_irq_save(flags);
  573. chan = s3c_dma_map_channel(channel);
  574. if (chan == NULL) {
  575. local_irq_restore(flags);
  576. return -EBUSY;
  577. }
  578. dbg_showchan(chan);
  579. chan->client = client;
  580. chan->in_use = 1;
  581. chan->dma_con->in_use++;
  582. if (!chan->irq_claimed) {
  583. pr_debug("DMA CH %d: %s : requesting irq %d\n",
  584. channel, __FUNCTION__, chan->irq);
  585. chan->irq_claimed = 1;
  586. local_irq_restore(flags);
  587. err = request_irq(chan->irq, s3c_dma_irq, SA_INTERRUPT,
  588. client->name, (void *) chan->dma_con);
  589. local_irq_save(flags);
  590. if (err) {
  591. chan->in_use = 0;
  592. chan->irq_claimed = 0;
  593. chan->dma_con->in_use--;
  594. local_irq_restore(flags);
  595. printk(KERN_ERR "%s: cannot get IRQ %d for DMA %d\n",
  596. client->name, chan->irq, chan->number);
  597. return err;
  598. }
  599. chan->irq_enabled = 1;
  600. /* enable the main dma.. this can be disabled
  601. * when main channel use count is 0 */
  602. s3c_enable_dmac(chan->dma_con->number);
  603. }
  604. s3c_clear_interrupts(chan->dma_con->number, chan->number);
  605. local_irq_restore(flags);
  606. /* need to setup */
  607. pr_debug("%s: channel initialised, %p, number:%d, index:%d\n", __FUNCTION__, chan, chan->number, chan->index);
  608. return 0;
  609. }
  610. EXPORT_SYMBOL(s3c2410_dma_request);
  611. /* s3c_dma_free
  612. *
  613. * release the given channel back to the system, will stop and flush
  614. * any outstanding transfers, and ensure the channel is ready for the
  615. * next claimant.
  616. *
  617. * Note, although a warning is currently printed if the freeing client
  618. * info is not the same as the registrant's client info, the free is still
  619. * allowed to go through.
  620. */
  621. int
  622. s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *client)
  623. {
  624. unsigned long flags;
  625. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  626. pr_debug("%s: DMA channel %d will be stopped\n", __FUNCTION__, chan->number);
  627. if (chan == NULL)
  628. return -EINVAL;
  629. local_irq_save(flags);
  630. if (chan->client != client) {
  631. printk(KERN_WARNING
  632. "DMA CH %d: possible free from different client (channel %p, passed %p)\n",
  633. channel, chan->client, client);
  634. }
  635. /* sort out stopping and freeing the channel */
  636. if (chan->state != S3C2410_DMA_IDLE) {
  637. pr_debug("%s: need to stop dma channel %p\n", __FUNCTION__, chan);
  638. /* possibly flush the channel */
  639. s3c2410_dma_ctrl(channel, S3C2410_DMAOP_STOP);
  640. }
  641. chan->client = NULL;
  642. chan->in_use = 0;
  643. chan->dma_con->in_use--;
  644. if (chan->irq_claimed)
  645. free_irq(chan->irq, (void *)chan->dma_con);
  646. chan->irq_claimed = 0;
  647. if (!(channel & DMACH_LOW_LEVEL))
  648. dma_chan_map[channel] = NULL;
  649. local_irq_restore(flags);
  650. pr_debug("--------------------------------------------\n");
  651. return 0;
  652. }
  653. EXPORT_SYMBOL(s3c2410_dma_free);
  654. /*actively polling for the A bit can block the cpu*/
  655. void
  656. s3c_dma_flush_fifo (struct s3c2410_dma_chan *chan)
  657. {
  658. unsigned long tmp;
  659. tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
  660. tmp |= S3C_DMACONFIG_HALT;
  661. dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, tmp);
  662. tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
  663. /*this while loop can be very dangerous..may be put the process to sleep rather than waiting till fifo is drained */
  664. while (tmp & S3C_DMACONFIG_ACTIVE) {
  665. tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
  666. }
  667. }
  668. static int
  669. s3c_dma_dostop(struct s3c2410_dma_chan *chan)
  670. {
  671. unsigned long tmp;
  672. unsigned long flags;
  673. pr_debug("%s: DMA Channel No : %d\n", __FUNCTION__, chan->number);
  674. dbg_showchan(chan);
  675. local_irq_save(flags);
  676. /* Before we turn off PCM out channel dma(AC_GLBCTRL [13:12]),
  677. * main dma should be stopped first by JaeCheol Lee
  678. */
  679. s3c_dma_flush_fifo(chan);
  680. s3c_dma_call_op(chan, S3C2410_DMAOP_STOP);
  681. tmp = dma_rdreg(chan, S3C_DMAC_CxCONFIGURATION);
  682. tmp &= ~S3C_DMACONFIG_CHANNEL_ENABLE;
  683. dma_wrreg(chan, S3C_DMAC_CxCONFIGURATION, tmp);
  684. pr_debug("%s: S3C_DMAC_CxCONFIGURATION : %08x\n", __FUNCTION__, tmp);
  685. chan->state = S3C2410_DMA_IDLE;
  686. chan->load_state = S3C2410_DMALOAD_NONE;
  687. local_irq_restore(flags);
  688. return 0;
  689. }
  690. static void
  691. s3c_dma_showchan (struct s3c2410_dma_chan * chan)
  692. {
  693. #if 0
  694. printk(KERN_DEBUG "dma[%d]: st %d, lst %d, cli %p, dcon %08lx\n",
  695. chan->number, chan->state, chan->load_state, chan->client, chan->dcon);
  696. printk(KERN_DEBUG "dma[%d]: CSRC=%x, ISRC=%x, STAT=%x, CON=%x, MT=%x\n",
  697. chan->number,
  698. dma_rdreg(chan, S3C2410_DMA_DCSRC),
  699. dma_rdreg(chan, S3C2410_DMA_DISRC),
  700. dma_rdreg(chan, S3C2410_DMA_DSTAT),
  701. dma_rdreg(chan, S3C2410_DMA_DCON), dma_rdreg(chan, S3C2410_DMA_DMASKTRIG));
  702. #endif
  703. }
  704. /* s3c_dma_flush
  705. *
  706. * stop the channel, and remove all current and pending transfers
  707. */
  708. void s3c_waitforstop(struct s3c2410_dma_chan *chan)
  709. {
  710. #if 0
  711. unsigned long tmp;
  712. unsigned int timeout = 0x10000;
  713. while (timeout-- > 0) {
  714. tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG);
  715. if (!(tmp & S3C2410_DMASKTRIG_ON))
  716. return;
  717. }
  718. pr_debug("dma%d: failed to stop?\n", chan->number);
  719. #endif
  720. }
  721. static int s3c_dma_flush(struct s3c2410_dma_chan *chan)
  722. {
  723. struct s3c2410_dma_buf *buf, *next;
  724. unsigned long flags;
  725. pr_debug("%s:\n", __FUNCTION__);
  726. local_irq_save(flags);
  727. s3c_dma_showchan(chan);
  728. if (chan->state != S3C2410_DMA_IDLE) {
  729. pr_debug("%s: stopping channel...\n", __FUNCTION__);
  730. s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_STOP);
  731. }
  732. buf = chan->curr;
  733. if (buf == NULL)
  734. buf = chan->next;
  735. chan->curr = chan->next = chan->end = NULL;
  736. chan->load_state = S3C2410_DMALOAD_NONE;
  737. if (buf != NULL) {
  738. for (; buf != NULL; buf = next) {
  739. next = buf->next;
  740. pr_debug("%s: free buffer %p, next %p\n", __FUNCTION__, buf, buf->next);
  741. s3c_dma_buffdone(chan, buf, S3C2410_RES_ABORT);
  742. s3c_dma_freebuf(buf);
  743. }
  744. }
  745. //s3c_dma_waitforstop(chan);
  746. s3c_dma_showchan(chan);
  747. local_irq_restore(flags);
  748. return 0;
  749. }
  750. int
  751. s3c_dma_started(struct s3c2410_dma_chan *chan)
  752. {
  753. unsigned long flags;
  754. local_irq_save(flags);
  755. dbg_showchan(chan);
  756. /* if we've only loaded one buffer onto the channel, then chec
  757. * to see if we have another, and if so, try and load it so when
  758. * the first buffer is finished, the new one will be loaded onto
  759. * the channel */
  760. if (chan->next != NULL) {
  761. if (chan->load_state == S3C2410_DMALOAD_1LOADED) {
  762. if (s3c_dma_waitforload(chan, __LINE__) == 0) {
  763. pr_debug("%s: buff not yet loaded, no more todo\n",
  764. __FUNCTION__);
  765. } else {
  766. chan->load_state = S3C2410_DMALOAD_1RUNNING;
  767. s3c_dma_loadbuffer(chan, chan->next);
  768. }
  769. } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) {
  770. s3c_dma_loadbuffer(chan, chan->next);
  771. }
  772. }
  773. local_irq_restore(flags);
  774. return 0;
  775. }
  776. int
  777. s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op)
  778. {
  779. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  780. if (chan == NULL)
  781. return -EINVAL;
  782. switch (op) {
  783. case S3C2410_DMAOP_START:
  784. return s3c_dma_start(chan);
  785. case S3C2410_DMAOP_STOP:
  786. return s3c_dma_dostop(chan);
  787. case S3C2410_DMAOP_PAUSE:
  788. case S3C2410_DMAOP_RESUME:
  789. return -ENOENT;
  790. case S3C2410_DMAOP_FLUSH:
  791. return s3c_dma_flush(chan);
  792. case S3C2410_DMAOP_STARTED:
  793. return s3c_dma_started(chan);
  794. case S3C2410_DMAOP_TIMEOUT:
  795. return 0;
  796. }
  797. return -ENOENT; /* unknown, don't bother */
  798. }
  799. EXPORT_SYMBOL(s3c2410_dma_ctrl);
  800. /* s3c_dma_config
  801. *
  802. * xfersize: size of unit in bytes (1,2,4)
  803. * dcon: base value of the DCONx register
  804. */
  805. int
  806. s3c2410_dma_config(dmach_t channel,
  807. int xferunit,
  808. int dcon)
  809. {
  810. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  811. pr_debug("%s: chan=%d, xfer_unit=%d, dcon=%08x\n",
  812. __FUNCTION__, channel, xferunit, dcon);
  813. if (chan == NULL)
  814. return -EINVAL;
  815. pr_debug("%s: Initial dcon is %08x\n", __FUNCTION__, dcon);
  816. dcon |= chan->dcon & dma_sel.dcon_mask;
  817. pr_debug("%s: New dcon is %08x\n", __FUNCTION__, dcon);
  818. switch (xferunit) {
  819. case 1:
  820. dcon |= S3C_DMACONTROL_SRC_WIDTH_BYTE;
  821. dcon |= S3C_DMACONTROL_DEST_WIDTH_BYTE;
  822. break;
  823. case 2:
  824. dcon |= S3C_DMACONTROL_SRC_WIDTH_HWORD;
  825. dcon |= S3C_DMACONTROL_DEST_WIDTH_HWORD;
  826. break;
  827. case 4:
  828. dcon |= S3C_DMACONTROL_SRC_WIDTH_WORD;
  829. dcon |= S3C_DMACONTROL_DEST_WIDTH_WORD;
  830. break;
  831. default:
  832. pr_debug("%s: Bad transfer size %d\n", __FUNCTION__, xferunit);
  833. return -EINVAL;
  834. }
  835. pr_debug("%s: DMA Channel control : %08x\n", __FUNCTION__, dcon);
  836. dcon |= S3C_DMACONTROL_TC_INT_ENABLE;
  837. dcon |= chan->control_flags;
  838. pr_debug("%s: dcon now %08x\n", __FUNCTION__, dcon);
  839. /* For DMCCxControl 0 */
  840. chan->dcon = dcon;
  841. /* For DMACCxControl 1 : xferunit means transfer width.*/
  842. chan->xfer_unit = xferunit;
  843. return 0;
  844. }
  845. EXPORT_SYMBOL(s3c2410_dma_config);
  846. int
  847. s3c2410_dma_setflags(dmach_t channel, unsigned int flags)
  848. {
  849. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  850. if (chan == NULL)
  851. return -EINVAL;
  852. pr_debug("%s: chan=%p, flags=%08x\n", __FUNCTION__, chan, flags);
  853. chan->flags = flags;
  854. return 0;
  855. }
  856. EXPORT_SYMBOL(s3c2410_dma_setflags);
  857. /* do we need to protect the settings of the fields from
  858. * irq?
  859. */
  860. int
  861. s3c2410_dma_set_opfn(dmach_t channel, s3c2410_dma_opfn_t rtn)
  862. {
  863. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  864. if (chan == NULL)
  865. return -EINVAL;
  866. pr_debug("%s: chan=%p, op rtn=%p\n", __FUNCTION__, chan, rtn);
  867. chan->op_fn = rtn;
  868. return 0;
  869. }
  870. EXPORT_SYMBOL(s3c2410_dma_set_opfn);
  871. int
  872. s3c2410_dma_set_buffdone_fn(dmach_t channel, s3c2410_dma_cbfn_t rtn)
  873. {
  874. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  875. if (chan == NULL)
  876. return -EINVAL;
  877. pr_debug("%s: chan=%p, callback rtn=%p\n", __FUNCTION__, chan, rtn);
  878. chan->callback_fn = rtn;
  879. return 0;
  880. }
  881. EXPORT_SYMBOL(s3c2410_dma_set_buffdone_fn);
  882. /* s3c2410_dma_devconfig
  883. *
  884. * configure the dma source/destination hardware type and address
  885. *
  886. * flowctrl: direction of dma flow
  887. *
  888. * src_per dst_per: dma channel number of src and dst periphreal,
  889. *
  890. * devaddr: physical address of the source
  891. */
  892. int
  893. s3c2410_dma_devconfig(int channel,
  894. enum s3c2410_dmasrc source,
  895. int hwcfg,
  896. unsigned long devaddr)
  897. {
  898. unsigned long tmp;
  899. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  900. if (chan == NULL)
  901. return -EINVAL;
  902. pr_debug("%s: source=%d, hwcfg=%08x, devaddr=%08lx\n",
  903. __FUNCTION__, (int)source, hwcfg, devaddr);
  904. chan->source = source;
  905. chan->dev_addr = devaddr;
  906. switch (source) {
  907. case S3C2410_DMASRC_MEM:
  908. /* source is Memory : Mem-to-Peri ( Write into FIFO) */
  909. tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2PER | (chan->map->hw_addr.to) <<
  910. S3C_DEST_SHIFT | S3C_DMACONFIG_CHANNEL_ENABLE;
  911. chan->config_flags = tmp;
  912. /* TODO : Now, Scatter&Gather DMA NOT supported */
  913. dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
  914. /* devaddr : Periperal address (destination) */
  915. dma_wrreg(chan, S3C_DMAC_CxDESTADDR, devaddr);
  916. /* source address : memory(buffer) address */
  917. chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxSRCADDR);
  918. chan->control_flags = S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_AXI_PERI ;
  919. //chan->control_flags = hwcfg;
  920. return 0;
  921. case S3C2410_DMASRC_HW:
  922. /* source is peripheral : Peri-to-Mem ( Read from FIFO) */
  923. tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_PER2MEM | (chan->map->hw_addr.from) <<
  924. S3C_SRC_SHIFT | S3C_DMACONFIG_CHANNEL_ENABLE;
  925. chan->config_flags = tmp;
  926. /* TODO : Now, Scatter&Gather DMA NOT supported */
  927. dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
  928. /* devaddr : Periperal address (source) */
  929. dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
  930. /* destination address : memory(buffer) address */
  931. chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
  932. chan->control_flags = S3C_DMACONTROL_DEST_INC | S3C_DMACONTROL_SRC_AXI_PERI;
  933. //chan->control_flags = hwcfg;
  934. return 0;
  935. case S3C_DMA_MEM2MEM:
  936. /* source is memory : Memory-to-Mem ( Read/Write) */
  937. tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2MEM | S3C_DMACONFIG_CHANNEL_ENABLE;
  938. if(chan->map->hw_addr.from == S3C_DMA0_ONENAND_RX) {
  939. tmp |= S3C_DMACONFIG_ONENANDMODESRC;
  940. }
  941. chan->config_flags = tmp;
  942. /* TODO : Now, Scatter&Gather DMA NOT supported */
  943. dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
  944. /* devaddr : memory/onenand address (source) */
  945. dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
  946. /* destination address : memory(buffer) address */
  947. chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
  948. chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_INC
  949. | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4);
  950. //chan->control_flags = hwcfg;
  951. return 0;
  952. #if defined(CONFIG_G3D)
  953. case S3C_DMA_MEM2G3D:
  954. /* this is temporary for g3d */
  955. tmp = S3C_DMACONFIG_TCMASK | S3C_DMACONFIG_FLOWCTRL_MEM2MEM | S3C_DMACONFIG_CHANNEL_ENABLE;
  956. //if(chan->map->hw_addr.from == S3C_DMA0_ONENAND_RX) {
  957. // tmp |= S3C_DMACONFIG_ONENANDMODESRC;
  958. //}
  959. chan->config_flags = tmp;
  960. /* TODO : Now, Scatter&Gather DMA NOT supported */
  961. dma_wrreg(chan, S3C_DMAC_CxLLI, 0);
  962. /* devaddr : memory/onenand address (source) */
  963. dma_wrreg(chan, S3C_DMAC_CxSRCADDR, devaddr);
  964. /* destination address : memory(buffer) address */
  965. chan->addr_reg = dma_regaddr(chan, S3C_DMAC_CxDESTADDR);
  966. // chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_INC
  967. // | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4);
  968. chan->control_flags |= (S3C_DMACONTROL_SRC_INC | S3C_DMACONTROL_DEST_AXI_PERI
  969. | S3C_DMACONTROL_SBSIZE_4 | S3C_DMACONTROL_DBSIZE_4);
  970. //chan->control_flags = hwcfg;
  971. return 0;
  972. #endif
  973. case S3C_DMA_PER2PER:
  974. printk("Peripheral-to-Peripheral DMA NOT YET implemented !! \n");
  975. return -EINVAL;
  976. default:
  977. printk("unsupported dma configuration :please add this capability to dma driver \n");
  978. return -EINVAL;
  979. }
  980. printk(KERN_ERR "DMA CH:%d - invalid source type ()\n", channel);
  981. return -EINVAL;
  982. }
  983. EXPORT_SYMBOL(s3c2410_dma_devconfig);
  984. /* s3c_dma_getposition
  985. *
  986. * returns the current transfer points for the dma source and destination
  987. */
  988. int
  989. s3c2410_dma_getposition(dmach_t channel, dma_addr_t *src, dma_addr_t *dst)
  990. {
  991. struct s3c2410_dma_chan *chan = lookup_dma_channel(channel);
  992. if (chan == NULL)
  993. return -EINVAL;
  994. if (src != NULL)
  995. *src = dma_rdreg(chan, S3C_DMAC_CxSRCADDR);
  996. if (dst != NULL)
  997. *dst = dma_rdreg(chan, S3C_DMAC_CxDESTADDR);
  998. return 0;
  999. }
  1000. EXPORT_SYMBOL(s3c2410_dma_getposition);
  1001. /* system device class */
  1002. #ifdef CONFIG_PM
  1003. static int
  1004. s3c_dma_suspend (struct sys_device *dev, pm_message_t state)
  1005. {
  1006. return 0;
  1007. }
  1008. static int
  1009. s3c_dma_resume (struct sys_device *dev)
  1010. {
  1011. return 0;
  1012. }
  1013. #else
  1014. #define s3c_dma_suspend NULL
  1015. #define s3c_dma_resume NULL
  1016. #endif /* CONFIG_PM */
  1017. struct sysdev_class dma_sysclass = {
  1018. set_kset_name("s3c24xx-dma"),
  1019. .suspend = s3c_dma_suspend,
  1020. .resume = s3c_dma_resume,
  1021. };
  1022. /* kmem cache implementation */
  1023. static void
  1024. s3c_dma_cache_ctor (void *p, struct kmem_cache *c, unsigned long f)
  1025. {
  1026. memset(p, 0, sizeof(struct s3c2410_dma_buf));
  1027. }
  1028. void
  1029. dma_test (int dcon_num, int channel)
  1030. {
  1031. int tmp;
  1032. s3c_dma_controller_t *dma_controller = &s3c_dma_cntlrs[dcon_num];
  1033. #if 0
  1034. sh_printk("writing to channel %d subch %d \n", dcon_num, channel);
  1035. sh_printk("main channel %d irq %d regs_base %x\n", dma_controller->number, dma_controller->irq,
  1036. dma_controller->regs);
  1037. sh_printk("sub channel %d irq %d regs_base %x\n", chan->number, chan->irq,
  1038. chan->regs);
  1039. #endif
  1040. dma_wrreg(dma_controller, S3C_DMAC_CONFIGURATION, S3C_DMA_CONTROLLER_ENABLE);
  1041. tmp = dma_rdreg(dma_controller, S3C_DMAC_CONFIGURATION);
  1042. printk("reg val %d\n", tmp);
  1043. dma_wrreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel), 0x01);
  1044. tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONFIGURATION(channel));
  1045. printk("reg conf %x\n", tmp);
  1046. dma_wrreg(dma_controller, S3C_DMAC_CCONTROL0(channel), 0x8ff02064);
  1047. tmp = dma_rdreg(dma_controller, S3C_DMAC_CCONTROL0(channel));
  1048. printk("reg ctrl %x\n", tmp);
  1049. }
  1050. /* initialisation code */
  1051. int __init s3c24xx_dma_init(unsigned int channels, unsigned int irq,
  1052. unsigned int stride)
  1053. {
  1054. struct s3c2410_dma_chan *cp;
  1055. s3c_dma_controller_t *dconp;
  1056. int channel, controller;
  1057. int ret;
  1058. printk("S3C DMA-pl080 Controller Driver, (c) 2006-2007 Samsung Electronics\n");
  1059. dma_channels = channels;
  1060. printk("Total %d DMA channels will be initialized.\n", channels);
  1061. ret = sysdev_class_register(&dma_sysclass);
  1062. if (ret != 0) {
  1063. printk(KERN_ERR "dma sysclass registration failed.\n");
  1064. goto err;
  1065. }
  1066. dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0,
  1067. SLAB_HWCACHE_ALIGN, s3c_dma_cache_ctor, NULL);
  1068. if (dma_kmem == NULL) {
  1069. printk(KERN_ERR "DMA failed to make kmem cache\n");
  1070. ret = -ENOMEM;
  1071. goto err;
  1072. }
  1073. for (controller = 0; controller < S3C_DMA_CONTROLLERS; controller++) {
  1074. dconp = &s3c_dma_cntlrs[controller];
  1075. memset(dconp, 0, sizeof(s3c_dma_controller_t));
  1076. if(controller < 2) {
  1077. dma_base = ioremap((S3C24XX_PA_DMA + (controller * 0x100000)), 0x200);
  1078. if (dma_base == NULL) {
  1079. printk(KERN_ERR "DMA failed to ioremap register block\n");
  1080. return -ENOMEM;
  1081. }
  1082. /* dma controller's irqs are in order.. */
  1083. dconp->irq = controller + IRQ_DMA0;
  1084. }
  1085. else {
  1086. dma_base = ioremap(((S3C24XX_PA_DMA + 0x8B00000) + ((controller%2) * 0x100000)), 0x200);
  1087. if (dma_base == NULL) {
  1088. printk(KERN_ERR "SDMA failed to ioremap register block\n");
  1089. return -ENOMEM;
  1090. }
  1091. /* dma controller's irqs are in order.. */
  1092. dconp->irq = (controller%2) + IRQ_SDMA0;
  1093. }
  1094. dconp->number = controller;
  1095. dconp->regs = dma_base;
  1096. sh_printk("DMA controller : %d irq %d regs_base %x\n", dconp->number, dconp->irq,
  1097. dconp->regs);
  1098. }
  1099. for (channel = 0; channel < channels; channel++) {
  1100. controller = channel / S3C_CHANNELS_PER_DMA;
  1101. cp = &s3c_dma_chans[channel];
  1102. memset(cp, 0, sizeof(struct s3c2410_dma_chan));
  1103. cp->dma_con = &s3c_dma_cntlrs[controller];
  1104. /* dma channel irqs are in order.. */
  1105. cp->index = channel;
  1106. cp->number = channel%S3C_CHANNELS_PER_DMA;
  1107. cp->irq = s3c_dma_cntlrs[controller].irq;
  1108. cp->regs = s3c_dma_cntlrs[controller].regs + ((channel%S3C_CHANNELS_PER_DMA)*stride) + 0x100;
  1109. /* point current stats somewhere */
  1110. cp->stats = &cp->stats_store;
  1111. cp->stats_store.timeout_shortest = LONG_MAX;
  1112. /* basic channel configuration */
  1113. cp->load_timeout = 1 << 18;
  1114. /* register system device */
  1115. cp->dev.cls = &dma_sysclass;
  1116. cp->dev.id = channel;
  1117. //ret = sysdev_register(&cp->dev);
  1118. sh_printk("DMA channel %d at %p, irq %d\n", cp->number, cp->regs, cp->irq);
  1119. }
  1120. return 0;
  1121. err:
  1122. kmem_cache_destroy(dma_kmem);
  1123. iounmap(dma_base);
  1124. dma_base = NULL;
  1125. return ret;
  1126. }
  1127. static inline int is_channel_valid(unsigned int channel)
  1128. {
  1129. return (channel & DMA_CH_VALID);
  1130. }
  1131. static struct s3c24xx_dma_order *dma_order;
  1132. /* s3c_dma_map_channel()
  1133. *
  1134. * turn the virtual channel number into a real, and un-used hardware
  1135. * channel.
  1136. *
  1137. * first, try the dma ordering given to us by either the relevant
  1138. * dma code, or the board. Then just find the first usable free
  1139. * channel
  1140. */
  1141. struct s3c2410_dma_chan *s3c_dma_map_channel(int channel)
  1142. {
  1143. struct s3c24xx_dma_order_ch *ord = NULL;
  1144. struct s3c24xx_dma_map *ch_map;
  1145. struct s3c2410_dma_chan *dmach;
  1146. int ch;
  1147. if (dma_sel.map == NULL || channel > dma_sel.map_size)
  1148. return NULL;
  1149. ch_map = dma_sel.map + channel;
  1150. /* first, try the board mapping */
  1151. if (dma_order) {
  1152. ord = &dma_order->channels[channel];
  1153. for (ch = 0; ch < dma_channels; ch++) {
  1154. if (!is_channel_valid(ord->list[ch]))
  1155. continue;
  1156. if (s3c_dma_chans[ord->list[ch]].in_use == 0) {
  1157. ch = ord->list[ch] & ~DMA_CH_VALID;
  1158. goto found;
  1159. }
  1160. }
  1161. if (ord->flags & DMA_CH_NEVER)
  1162. return NULL;
  1163. }
  1164. /* second, search the channel map for first free */
  1165. for (ch = 0; ch < dma_channels; ch++) {
  1166. if (!is_channel_valid(ch_map->channels[ch]))
  1167. continue;
  1168. if (s3c_dma_chans[ch].in_use == 0) {
  1169. pr_debug("mapped channel %d to %d\n", channel, ch);
  1170. break;
  1171. }
  1172. }
  1173. if (ch >= dma_channels)
  1174. return NULL;
  1175. /* update our channel mapping */
  1176. found:
  1177. dmach = &s3c_dma_chans[ch];
  1178. dma_chan_map[channel] = dmach;
  1179. /* select the channel */
  1180. (dma_sel.select)(dmach, ch_map);
  1181. return dmach;
  1182. }
  1183. static int s3c_dma_check_entry(struct s3c24xx_dma_map *map, int ch)
  1184. {
  1185. unsigned long tmp = __raw_readl(S3C_SDMA_SEL);
  1186. tmp |= map->sdma_sel;
  1187. __raw_writel(tmp, S3C_SDMA_SEL);
  1188. return 0;
  1189. }
  1190. int __init s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel)
  1191. {
  1192. struct s3c24xx_dma_map *nmap;
  1193. size_t map_sz = sizeof(*nmap) * sel->map_size;
  1194. int ptr;
  1195. nmap = kmalloc(map_sz, GFP_KERNEL);
  1196. if (nmap == NULL)
  1197. return -ENOMEM;
  1198. memcpy(nmap, sel->map, map_sz);
  1199. memcpy(&dma_sel, sel, sizeof(*sel));
  1200. dma_sel.map = nmap;
  1201. for (ptr = 0; ptr < sel->map_size; ptr++)
  1202. s3c_dma_check_entry(nmap+ptr, ptr);
  1203. return 0;
  1204. }
  1205. int __init s3c_dma_order_set(struct s3c24xx_dma_order *ord)
  1206. {
  1207. struct s3c24xx_dma_order *nord = dma_order;
  1208. if (nord == NULL)
  1209. nord = kmalloc(sizeof(struct s3c24xx_dma_order), GFP_KERNEL);
  1210. if (nord == NULL) {
  1211. printk(KERN_ERR "no memory to store dma channel order\n");
  1212. return -ENOMEM;
  1213. }
  1214. dma_order = nord;
  1215. memcpy(nord, ord, sizeof(struct s3c24xx_dma_order));
  1216. return 0;
  1217. }