devs.c 31 KB

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  1. /* linux/arch/arm/plat-s3c24xx/devs.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Base S3C24XX platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <asm/mach/arch.h>
  22. #include <asm/mach/map.h>
  23. #include <asm/mach/irq.h>
  24. #include <asm/arch/fb.h>
  25. #include <asm/hardware.h>
  26. #include <asm/io.h>
  27. #include <asm/irq.h>
  28. #include <asm/arch/regs-serial.h>
  29. #include <asm/arch/udc.h>
  30. #include <asm/plat-s3c24xx/devs.h>
  31. #include <asm/plat-s3c24xx/cpu.h>
  32. //Qisda Tony 090324, add keypad [
  33. #include <asm/arch/regs-gpio.h>
  34. //Qisda Tony 090324, add keypad ]
  35. /* Serial port registrations */
  36. static struct resource s3c2410_uart0_resource[] = {
  37. [0] = {
  38. .start = S3C2410_PA_UART0,
  39. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  40. .end = S3C2410_PA_UART0 + 0x3fff,
  41. #else
  42. .end = S3C2410_PA_UART0 + 0x3ff,
  43. #endif
  44. .flags = IORESOURCE_MEM,
  45. },
  46. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  47. [1] = {
  48. .start = IRQ_S3CUART_RX0,
  49. .end = IRQ_S3CUART_ERR0,
  50. .flags = IORESOURCE_IRQ,
  51. }
  52. #else
  53. [1] = {
  54. .start = IRQ_UART0,
  55. .end = IRQ_UART0,
  56. .flags = IORESOURCE_IRQ,
  57. }
  58. #endif
  59. };
  60. static struct resource s3c2410_uart1_resource[] = {
  61. [0] = {
  62. .start = S3C2410_PA_UART1,
  63. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  64. .end = S3C2410_PA_UART1 + 0x3fff,
  65. #else
  66. .end = S3C2410_PA_UART1 + 0x3ff,
  67. #endif
  68. .flags = IORESOURCE_MEM,
  69. },
  70. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  71. [1] = {
  72. .start = IRQ_S3CUART_RX1,
  73. .end = IRQ_S3CUART_ERR1,
  74. .flags = IORESOURCE_IRQ,
  75. }
  76. #else
  77. [1] = {
  78. .start = IRQ_UART1,
  79. .end = IRQ_UART1,
  80. .flags = IORESOURCE_IRQ,
  81. }
  82. #endif
  83. };
  84. static struct resource s3c2410_uart2_resource[] = {
  85. [0] = {
  86. .start = S3C2410_PA_UART2,
  87. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  88. .end = S3C2410_PA_UART2 + 0x3fff,
  89. #else
  90. .end = S3C2410_PA_UART2 + 0x3ff,
  91. #endif
  92. .flags = IORESOURCE_MEM,
  93. },
  94. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  95. [1] = {
  96. .start = IRQ_S3CUART_RX2,
  97. .end = IRQ_S3CUART_ERR2,
  98. .flags = IORESOURCE_IRQ,
  99. }
  100. #else
  101. [1] = {
  102. .start = IRQ_UART2,
  103. .end = IRQ_UART2,
  104. .flags = IORESOURCE_IRQ,
  105. }
  106. #endif
  107. };
  108. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  109. static struct resource s3c_uart3_resource[] = {
  110. [0] = {
  111. .start = S3C2443_PA_UART3,
  112. .end = S3C2443_PA_UART3 + 0x3ff,
  113. .flags = IORESOURCE_MEM,
  114. },
  115. [1] = {
  116. .start = IRQ_UART3,
  117. .end = IRQ_UART3,
  118. .flags = IORESOURCE_IRQ,
  119. }
  120. };
  121. #endif
  122. struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
  123. [0] = {
  124. .resources = s3c2410_uart0_resource,
  125. .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
  126. },
  127. [1] = {
  128. .resources = s3c2410_uart1_resource,
  129. .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
  130. },
  131. [2] = {
  132. .resources = s3c2410_uart2_resource,
  133. .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
  134. },
  135. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  136. [3] = {
  137. .resources = s3c_uart3_resource,
  138. .nr_resources = ARRAY_SIZE(s3c_uart3_resource),
  139. },
  140. #endif
  141. };
  142. /* yart devices */
  143. static struct platform_device s3c24xx_uart_device0 = {
  144. .id = 0,
  145. };
  146. static struct platform_device s3c24xx_uart_device1 = {
  147. .id = 1,
  148. };
  149. static struct platform_device s3c24xx_uart_device2 = {
  150. .id = 2,
  151. };
  152. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  153. static struct platform_device s3c24xx_uart_device3 = {
  154. .id = 3,
  155. };
  156. #endif
  157. struct platform_device *s3c24xx_uart_src[] = {
  158. &s3c24xx_uart_device0,
  159. &s3c24xx_uart_device1,
  160. &s3c24xx_uart_device2,
  161. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  162. &s3c24xx_uart_device3,
  163. #endif
  164. };
  165. struct platform_device *s3c24xx_uart_devs[] = {
  166. };
  167. /* USB Host Controller */
  168. static struct resource s3c_usb_resource[] = {
  169. [0] = {
  170. .start = S3C24XX_PA_USBHOST,
  171. .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
  172. .flags = IORESOURCE_MEM,
  173. },
  174. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  175. [1] = {
  176. .start = IRQ_USBH,
  177. .end = IRQ_USBH,
  178. .flags = IORESOURCE_IRQ,
  179. }
  180. #else
  181. [1] = {
  182. .start = IRQ_UHOST,
  183. .end = IRQ_UHOST,
  184. .flags = IORESOURCE_IRQ,
  185. }
  186. #endif
  187. };
  188. static u64 s3c_device_usb_dmamask = 0xffffffffUL;
  189. struct platform_device s3c_device_usb = {
  190. .name = "s3c2410-ohci",
  191. .id = -1,
  192. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  193. .resource = s3c_usb_resource,
  194. .dev = {
  195. .dma_mask = &s3c_device_usb_dmamask,
  196. .coherent_dma_mask = 0xffffffffUL
  197. }
  198. };
  199. EXPORT_SYMBOL(s3c_device_usb);
  200. /* LCD Controller */
  201. static struct resource s3c_lcd_resource[] = {
  202. [0] = {
  203. .start = S3C24XX_PA_LCD,
  204. .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
  205. .flags = IORESOURCE_MEM,
  206. },
  207. [1] = {
  208. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  209. .start = IRQ_LCD_VSYNC ,
  210. .end = IRQ_LCD_SYSTEM,
  211. #else
  212. .start = IRQ_LCD,
  213. .end = IRQ_LCD,
  214. #endif
  215. .flags = IORESOURCE_IRQ,
  216. }
  217. };
  218. static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
  219. struct platform_device s3c_device_lcd = {
  220. .name = "s3c2410-lcd",
  221. .id = -1,
  222. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  223. .resource = s3c_lcd_resource,
  224. .dev = {
  225. .dma_mask = &s3c_device_lcd_dmamask,
  226. .coherent_dma_mask = 0xffffffffUL
  227. }
  228. };
  229. EXPORT_SYMBOL(s3c_device_lcd);
  230. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  231. {
  232. struct s3c2410fb_mach_info *npd;
  233. npd = kmalloc(sizeof(*npd), GFP_KERNEL);
  234. if (npd) {
  235. memcpy(npd, pd, sizeof(*npd));
  236. s3c_device_lcd.dev.platform_data = npd;
  237. } else {
  238. printk(KERN_ERR "no memory for LCD platform data\n");
  239. }
  240. }
  241. /* NAND Controller */
  242. static struct resource s3c_nand_resource[] = {
  243. [0] = {
  244. .start = S3C24XX_PA_NAND,
  245. .end = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
  246. .flags = IORESOURCE_MEM,
  247. }
  248. };
  249. struct platform_device s3c_device_nand = {
  250. .name = "s3c2410-nand",
  251. .id = -1,
  252. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  253. .resource = s3c_nand_resource,
  254. };
  255. EXPORT_SYMBOL(s3c_device_nand);
  256. /* OneNAND Controller */
  257. static struct resource s3c_onenand_resource[] = {
  258. [0] = {
  259. .start = S3C6400_PA_ONENAND,
  260. .end = S3C6400_PA_ONENAND + S3C_SZ_ONENAND - 1,
  261. .flags = IORESOURCE_MEM,
  262. }
  263. };
  264. struct platform_device s3c_device_onenand = {
  265. .name = "onenand",
  266. .id = -1,
  267. .dev = {
  268. .platform_data = &s3c_onenand_data,
  269. },
  270. .num_resources = ARRAY_SIZE(s3c_onenand_resource),
  271. .resource = s3c_onenand_resource,
  272. };
  273. EXPORT_SYMBOL(s3c_device_onenand);
  274. /* USB Device (Gadget)*/
  275. static struct resource s3c_usbgadget_resource[] = {
  276. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  277. [0] = {
  278. .start = S3C24XX_PA_USBDEV,
  279. .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
  280. .flags = IORESOURCE_MEM,
  281. },
  282. [1] = {
  283. .start = IRQ_USBD,
  284. .end = IRQ_USBD,
  285. .flags = IORESOURCE_IRQ,
  286. }
  287. #else
  288. [0] = {
  289. .start = S3C24XX_PA_OTG,
  290. .end = S3C24XX_PA_OTG+S3C24XX_SZ_OTG-1,
  291. .flags = IORESOURCE_MEM,
  292. },
  293. [1] = {
  294. .start = IRQ_OTG,
  295. .end = IRQ_OTG,
  296. .flags = IORESOURCE_IRQ,
  297. }
  298. #endif
  299. };
  300. struct platform_device s3c_device_usbgadget = {
  301. .name = "s3c2410-usbgadget",
  302. .id = -1,
  303. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  304. .resource = s3c_usbgadget_resource,
  305. };
  306. EXPORT_SYMBOL(s3c_device_usbgadget);
  307. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  308. {
  309. struct s3c2410_udc_mach_info *npd;
  310. npd = kmalloc(sizeof(*npd), GFP_KERNEL);
  311. if (npd) {
  312. memcpy(npd, pd, sizeof(*npd));
  313. s3c_device_usbgadget.dev.platform_data = npd;
  314. } else {
  315. printk(KERN_ERR "no memory for udc platform data\n");
  316. }
  317. }
  318. /* Watchdog */
  319. static struct resource s3c_wdt_resource[] = {
  320. [0] = {
  321. .start = S3C24XX_PA_WATCHDOG,
  322. .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
  323. .flags = IORESOURCE_MEM,
  324. },
  325. #if defined (CONFIG_CPU_S3C2443)|| defined (CONFIG_CPU_S3C2450) || defined (CONFIG_CPU_S3C2416)
  326. [1] = {
  327. .start = IRQ_S3C2443_WDT,
  328. .end = IRQ_S3C2443_WDT,
  329. .flags = IORESOURCE_IRQ,
  330. }
  331. #else
  332. [1] = {
  333. .start = IRQ_WDT,
  334. .end = IRQ_WDT,
  335. .flags = IORESOURCE_IRQ,
  336. }
  337. #endif
  338. };
  339. struct platform_device s3c_device_wdt = {
  340. .name = "s3c2410-wdt",
  341. .id = -1,
  342. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  343. .resource = s3c_wdt_resource,
  344. };
  345. EXPORT_SYMBOL(s3c_device_wdt);
  346. /* I2C */
  347. static struct resource s3c_i2c_resource[] = {
  348. [0] = {
  349. .start = S3C24XX_PA_IIC,
  350. .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
  351. .flags = IORESOURCE_MEM,
  352. },
  353. [1] = {
  354. .start = IRQ_IIC,
  355. .end = IRQ_IIC,
  356. .flags = IORESOURCE_IRQ,
  357. }
  358. };
  359. struct platform_device s3c_device_i2c = {
  360. .name = "s3c2410-i2c",
  361. .id = -1,
  362. .num_resources = ARRAY_SIZE(s3c_i2c_resource),
  363. .resource = s3c_i2c_resource,
  364. };
  365. EXPORT_SYMBOL(s3c_device_i2c);
  366. /* IIS */
  367. static struct resource s3c_iis_resource[] = {
  368. [0] = {
  369. .start = S3C24XX_PA_IIS,
  370. .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
  371. .flags = IORESOURCE_MEM,
  372. },
  373. #ifdef CONFIG_CPU_S3C6410
  374. [1] = {
  375. .start = IRQ_IIS,
  376. .end = IRQ_IIS,
  377. .flags = IORESOURCE_IRQ,
  378. }
  379. #endif
  380. };
  381. static u64 s3c_device_iis_dmamask = 0xffffffffUL;
  382. struct platform_device s3c_device_iis = {
  383. .name = "s3c2410-iis",
  384. .id = -1,
  385. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  386. .resource = s3c_iis_resource,
  387. .dev = {
  388. .dma_mask = &s3c_device_iis_dmamask,
  389. .coherent_dma_mask = 0xffffffffUL
  390. }
  391. };
  392. EXPORT_SYMBOL(s3c_device_iis);
  393. /* IIS v4.0 multi channel */
  394. static struct resource s3c_iis_v40_resource[] = {
  395. [0] = {
  396. .start = S3C6410_PA_IIS_V40,
  397. .end = S3C6410_PA_IIS_V40 + S3C24XX_SZ_IIS -1,
  398. .flags = IORESOURCE_MEM,
  399. },
  400. };
  401. static u64 s3c_device_iis_v40_dmamask = 0xffffffffUL;
  402. struct platform_device s3c_device_iis_v40 = {
  403. .name = "s3c-i2s-v40",
  404. .id = -1,
  405. .num_resources = ARRAY_SIZE(s3c_iis_v40_resource),
  406. .resource = s3c_iis_v40_resource,
  407. .dev = {
  408. .dma_mask = &s3c_device_iis_v40_dmamask,
  409. .coherent_dma_mask = 0xffffffffUL
  410. }
  411. };
  412. EXPORT_SYMBOL(s3c_device_iis_v40);
  413. /* AC97 */
  414. static struct resource s3c_ac97_resource[] = {
  415. [0] = {
  416. .start = S3C24XX_PA_AC97,
  417. .end = S3C24XX_PA_AC97 + S3C24XX_SZ_AC97 -1,
  418. .flags = IORESOURCE_MEM,
  419. }
  420. };
  421. static u64 s3c_device_ac97_dmamask = 0xffffffffUL;
  422. struct platform_device s3c_device_ac97 = {
  423. .name = "s3c-ac97",
  424. .id = -1,
  425. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  426. .resource = s3c_ac97_resource,
  427. .dev = {
  428. .dma_mask = &s3c_device_ac97_dmamask,
  429. .coherent_dma_mask = 0xffffffffUL
  430. }
  431. };
  432. EXPORT_SYMBOL(s3c_device_ac97);
  433. /* RTC */
  434. static struct resource s3c_rtc_resource[] = {
  435. [0] = {
  436. .start = S3C24XX_PA_RTC,
  437. .end = S3C24XX_PA_RTC + 0xff,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  441. [1] = {
  442. .start = IRQ_RTC,
  443. .end = IRQ_RTC,
  444. .flags = IORESOURCE_IRQ,
  445. },
  446. [2] = {
  447. .start = IRQ_TICK,
  448. .end = IRQ_TICK,
  449. .flags = IORESOURCE_IRQ
  450. }
  451. #else
  452. [1] = {
  453. .start = IRQ_RTC_ALARM,
  454. .end = IRQ_RTC_ALARM,
  455. .flags = IORESOURCE_IRQ,
  456. },
  457. [2] = {
  458. .start = IRQ_RTC_TIC,
  459. .end = IRQ_RTC_TIC,
  460. .flags = IORESOURCE_IRQ
  461. }
  462. #endif
  463. };
  464. struct platform_device s3c_device_rtc = {
  465. .name = "s3c2410-rtc",
  466. .id = -1,
  467. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  468. .resource = s3c_rtc_resource,
  469. };
  470. EXPORT_SYMBOL(s3c_device_rtc);
  471. /* ADC */
  472. static struct resource s3c_adc_resource[] = {
  473. [0] = {
  474. .start = S3C24XX_PA_ADC,
  475. .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
  476. .flags = IORESOURCE_MEM,
  477. },
  478. [1] = {
  479. .start = IRQ_TC,
  480. .end = IRQ_TC,
  481. .flags = IORESOURCE_IRQ,
  482. },
  483. [2] = {
  484. .start = IRQ_ADC,
  485. .end = IRQ_ADC,
  486. .flags = IORESOURCE_IRQ,
  487. }
  488. };
  489. struct platform_device s3c_device_adc = {
  490. .name = "s3c2410-adc",
  491. .id = -1,
  492. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  493. .resource = s3c_adc_resource,
  494. };
  495. /* SDI */
  496. static struct resource s3c_sdi_resource[] = {
  497. [0] = {
  498. .start = S3C2410_PA_SDI,
  499. .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
  500. .flags = IORESOURCE_MEM,
  501. },
  502. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  503. [1] = {
  504. .start = IRQ_SDI,
  505. .end = IRQ_SDI,
  506. .flags = IORESOURCE_IRQ,
  507. }
  508. #endif
  509. };
  510. struct platform_device s3c_device_sdi = {
  511. .name = "s3c2410-sdi",
  512. .id = -1,
  513. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  514. .resource = s3c_sdi_resource,
  515. };
  516. EXPORT_SYMBOL(s3c_device_sdi);
  517. /* SPI (0) */
  518. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  519. static struct resource s3c_spi0_resource[] = {
  520. [0] = {
  521. .start = S3C_PA_SPI_0,
  522. .end = S3C_PA_SPI_0 + S3C_SZ_SPI_0,
  523. .flags = IORESOURCE_MEM,
  524. },
  525. [1] = {
  526. .start = IRQ_SPI0,
  527. .end = IRQ_SPI0,
  528. .flags = IORESOURCE_IRQ,
  529. }
  530. };
  531. static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
  532. struct platform_device s3c_device_spi0 = {
  533. .name = "s3c2410-spi",
  534. .id = 0,
  535. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  536. .resource = s3c_spi0_resource,
  537. .dev = {
  538. .dma_mask = &s3c_device_spi0_dmamask,
  539. .coherent_dma_mask = 0xffffffffUL
  540. }
  541. };
  542. EXPORT_SYMBOL(s3c_device_spi0);
  543. static struct resource s3c_spi1_resource[] = {
  544. [0] = {
  545. .start = S3C_PA_SPI_0,
  546. .end = S3C_PA_SPI_0 + S3C_SZ_SPI_0,
  547. .flags = IORESOURCE_MEM,
  548. },
  549. [1] = {
  550. .start = IRQ_SPI1,
  551. .end = IRQ_SPI1,
  552. .flags = IORESOURCE_IRQ,
  553. }
  554. };
  555. struct platform_device s3c_device_spi1 = {
  556. .name = "s3c-spi",
  557. .id = 1,
  558. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  559. .resource = s3c_spi1_resource,
  560. };
  561. EXPORT_SYMBOL(s3c_device_spi1);
  562. #else
  563. static struct resource s3c_spi0_resource[] = {
  564. [0] = {
  565. .start = S3C24XX_PA_SPI,
  566. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  567. .end = S3C24XX_PA_SPI + 0x1f,
  568. #else
  569. .end = S3C24XX_PA_SPI + S3C24XX_SZ_SPI - 1,
  570. #endif
  571. .flags = IORESOURCE_MEM,
  572. },
  573. [1] = {
  574. .start = IRQ_SPI0,
  575. .end = IRQ_SPI0,
  576. .flags = IORESOURCE_IRQ,
  577. }
  578. };
  579. static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
  580. struct platform_device s3c_device_spi0 = {
  581. .name = "s3c2410-spi",
  582. .id = 0,
  583. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  584. .resource = s3c_spi0_resource,
  585. .dev = {
  586. .dma_mask = &s3c_device_spi0_dmamask,
  587. .coherent_dma_mask = 0xffffffffUL
  588. }
  589. };
  590. EXPORT_SYMBOL(s3c_device_spi0);
  591. /* SPI (1) */
  592. static struct resource s3c_spi1_resource[] = {
  593. [0] = {
  594. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  595. .start = S3C24XX_PA_SPI + 0x20,
  596. .end = S3C24XX_PA_SPI + 0x20 + 0x1f,
  597. #else
  598. .start = S3C24XX_PA_SPI + S3C24XX_SZ_SPI,
  599. .end = S3C24XX_PA_SPI + S3C24XX_SZ_SPI + 0xff,
  600. #endif
  601. .flags = IORESOURCE_MEM,
  602. },
  603. [1] = {
  604. .start = IRQ_SPI1,
  605. .end = IRQ_SPI1,
  606. .flags = IORESOURCE_IRQ,
  607. }
  608. };
  609. static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
  610. struct platform_device s3c_device_spi1 = {
  611. .name = "s3c2410-spi",
  612. .id = 1,
  613. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  614. .resource = s3c_spi1_resource,
  615. .dev = {
  616. .dma_mask = &s3c_device_spi1_dmamask,
  617. .coherent_dma_mask = 0xffffffffUL
  618. }
  619. };
  620. EXPORT_SYMBOL(s3c_device_spi1);
  621. #endif
  622. /* pwm timer blocks */
  623. static struct resource s3c_timer0_resource[] = {
  624. [0] = {
  625. .start = S3C24XX_PA_TIMER + 0x0C,
  626. .end = S3C24XX_PA_TIMER + 0x0C + 0xB,
  627. .flags = IORESOURCE_MEM,
  628. },
  629. [1] = {
  630. .start = IRQ_TIMER0,
  631. .end = IRQ_TIMER0,
  632. .flags = IORESOURCE_IRQ,
  633. }
  634. };
  635. struct platform_device s3c_device_timer0 = {
  636. .name = "s3c2410-timer",
  637. .id = 0,
  638. .num_resources = ARRAY_SIZE(s3c_timer0_resource),
  639. .resource = s3c_timer0_resource,
  640. };
  641. EXPORT_SYMBOL(s3c_device_timer0);
  642. /* timer 1 */
  643. static struct resource s3c_timer1_resource[] = {
  644. [0] = {
  645. .start = S3C24XX_PA_TIMER + 0x18,
  646. .end = S3C24XX_PA_TIMER + 0x23,
  647. .flags = IORESOURCE_MEM,
  648. },
  649. [1] = {
  650. .start = IRQ_TIMER1,
  651. .end = IRQ_TIMER1,
  652. .flags = IORESOURCE_IRQ,
  653. }
  654. };
  655. struct platform_device s3c_device_timer1 = {
  656. .name = "s3c2410-timer",
  657. .id = 1,
  658. .num_resources = ARRAY_SIZE(s3c_timer1_resource),
  659. .resource = s3c_timer1_resource,
  660. };
  661. EXPORT_SYMBOL(s3c_device_timer1);
  662. /* timer 2 */
  663. static struct resource s3c_timer2_resource[] = {
  664. [0] = {
  665. .start = S3C24XX_PA_TIMER + 0x24,
  666. .end = S3C24XX_PA_TIMER + 0x2F,
  667. .flags = IORESOURCE_MEM,
  668. },
  669. [1] = {
  670. .start = IRQ_TIMER2,
  671. .end = IRQ_TIMER2,
  672. .flags = IORESOURCE_IRQ,
  673. }
  674. };
  675. struct platform_device s3c_device_timer2 = {
  676. .name = "s3c2410-timer",
  677. .id = 2,
  678. .num_resources = ARRAY_SIZE(s3c_timer2_resource),
  679. .resource = s3c_timer2_resource,
  680. };
  681. EXPORT_SYMBOL(s3c_device_timer2);
  682. /* timer 3 */
  683. static struct resource s3c_timer3_resource[] = {
  684. [0] = {
  685. .start = S3C24XX_PA_TIMER + 0x30,
  686. .end = S3C24XX_PA_TIMER + 0x3B,
  687. .flags = IORESOURCE_MEM,
  688. },
  689. [1] = {
  690. .start = IRQ_TIMER3,
  691. .end = IRQ_TIMER3,
  692. .flags = IORESOURCE_IRQ,
  693. }
  694. };
  695. struct platform_device s3c_device_timer3 = {
  696. .name = "s3c2410-timer",
  697. .id = 3,
  698. .num_resources = ARRAY_SIZE(s3c_timer3_resource),
  699. .resource = s3c_timer3_resource,
  700. };
  701. EXPORT_SYMBOL(s3c_device_timer3);
  702. #if defined(CONFIG_CPU_S3C2440)
  703. /* Camif Controller */
  704. static struct resource s3c_camif_resource[] = {
  705. [0] = {
  706. .start = S3C2440_PA_CAMIF,
  707. .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
  708. .flags = IORESOURCE_MEM,
  709. },
  710. [1] = {
  711. .start = IRQ_CAM,
  712. .end = IRQ_CAM,
  713. .flags = IORESOURCE_IRQ,
  714. }
  715. };
  716. static u64 s3c_device_camif_dmamask = 0xffffffffUL;
  717. struct platform_device s3c_device_camif = {
  718. .name = "s3c2440-camif",
  719. .id = -1,
  720. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  721. .resource = s3c_camif_resource,
  722. .dev = {
  723. .dma_mask = &s3c_device_camif_dmamask,
  724. .coherent_dma_mask = 0xffffffffUL
  725. }
  726. };
  727. EXPORT_SYMBOL(s3c_device_camif);
  728. #endif // CONFIG_CPU_S32440
  729. #if !defined(CONFIG_CPU_S3C2440) && (defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416))
  730. /* Camif Controller */
  731. static struct resource s3c_camif_resource[] = {
  732. [0] = {
  733. .start = S3C2443_PA_CAMIF,
  734. .end = S3C2443_PA_CAMIF + S3C2443_SZ_CAMIF - 1,
  735. .flags = IORESOURCE_MEM,
  736. },
  737. [1] = {
  738. .start = IRQ_S3C2440_CAM_C,
  739. .end = IRQ_S3C2440_CAM_C,
  740. .flags = IORESOURCE_IRQ,
  741. },
  742. [2] = {
  743. .start = IRQ_S3C2440_CAM_P,
  744. .end = IRQ_S3C2440_CAM_P,
  745. .flags = IORESOURCE_IRQ,
  746. }
  747. };
  748. static u64 s3c_device_camif_dmamask = 0xffffffffUL;
  749. struct platform_device s3c_device_camif = {
  750. .name = "s3c-camif",
  751. .id = -1,
  752. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  753. .resource = s3c_camif_resource,
  754. .dev = {
  755. .dma_mask = &s3c_device_camif_dmamask,
  756. .coherent_dma_mask = 0xffffffffUL
  757. }
  758. };
  759. EXPORT_SYMBOL(s3c_device_camif);
  760. static struct resource s3c_ide_resource[] = {
  761. [0] = {
  762. .start = S3C_PA_CFATA,
  763. .end = S3C_PA_CFATA+ S3C_SZ_CFATA,
  764. .flags = IORESOURCE_MEM,
  765. },
  766. [1] = {
  767. .start = IRQ_CFCON,
  768. .end = IRQ_CFCON,
  769. .flags = IORESOURCE_IRQ,
  770. }
  771. };
  772. struct platform_device s3c_device_ide = {
  773. .name = "s3c-ide",
  774. .id = 0,
  775. .num_resources = ARRAY_SIZE(s3c_ide_resource),
  776. .resource = s3c_ide_resource,
  777. };
  778. EXPORT_SYMBOL(s3c_device_ide);
  779. #if defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  780. /* HS-MMC Controller */
  781. extern struct s3c_hsmmc_cfg s3c_hsmmc0_platform;
  782. extern struct s3c_hsmmc_cfg s3c_hsmmc1_platform;
  783. static struct resource s3c_hsmmc0_resource[] = {
  784. [0] = {
  785. .start = S3C_PA_HSMMC+0x400000,
  786. .end = S3C_PA_HSMMC+0x400000+S3C_SZ_HSMMC,
  787. .flags = IORESOURCE_MEM,
  788. },
  789. [1] = {
  790. .start = IRQ_SDI_0,
  791. .end = IRQ_SDI_0,
  792. .flags = IORESOURCE_IRQ,
  793. },
  794. /* To detect a card inserted, use an external interrupt */
  795. [2] = {
  796. .start = IRQ_EINT1,
  797. .end = IRQ_EINT1,
  798. .flags = IORESOURCE_IRQ,
  799. }
  800. };
  801. static struct resource s3c_hsmmc1_resource[] = {
  802. [0] = {
  803. .start = S3C_PA_HSMMC,
  804. .end = S3C_PA_HSMMC+S3C_SZ_HSMMC,
  805. .flags = IORESOURCE_MEM,
  806. },
  807. [1] = {
  808. .start = IRQ_SDI_1,
  809. .end = IRQ_SDI_1,
  810. .flags = IORESOURCE_IRQ,
  811. }
  812. };
  813. struct platform_device s3c_device_hsmmc0 = {
  814. .name = "s3c-hsmmc",
  815. .id = 0,
  816. .num_resources = ARRAY_SIZE(s3c_hsmmc0_resource),
  817. .resource = s3c_hsmmc0_resource,
  818. .dev = {
  819. .platform_data = &s3c_hsmmc0_platform,
  820. }
  821. };
  822. struct platform_device s3c_device_hsmmc1 = {
  823. .name = "s3c-hsmmc",
  824. .id = 1,
  825. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  826. .resource = s3c_hsmmc1_resource,
  827. .dev = {
  828. .platform_data = &s3c_hsmmc1_platform,
  829. }
  830. };
  831. EXPORT_SYMBOL(s3c_device_hsmmc0);
  832. EXPORT_SYMBOL(s3c_device_hsmmc1);
  833. //Qisda Tony 090324, add keypad [
  834. //#define IN_2416_EMU_BOARD
  835. static struct resource s3c_keypad_qisda_resource[] = {
  836. #ifdef IN_2416_EMU_BOARD
  837. [0] = {
  838. .start = S3C2410_GPFCON,
  839. .end = S3C2410_GPFCON,+0x10-1,
  840. .flags = IORESOURCE_MEM,
  841. },
  842. #else
  843. [0] = {
  844. .start = S3C2410_GPECON,
  845. .end = S3C2410_GPECON,+0x10-1,
  846. .flags = IORESOURCE_MEM,
  847. },
  848. #endif
  849. [1] = {
  850. .start = IRQ_EINT0,
  851. .end = IRQ_EINT0,
  852. .flags = IORESOURCE_IRQ,
  853. }
  854. };
  855. struct platform_device s3c_device_keypad_qisda = {
  856. .name = "s3c-keypad-qisda",
  857. .id = 0,
  858. .num_resources = ARRAY_SIZE(s3c_keypad_qisda_resource),
  859. .resource = s3c_keypad_qisda_resource,
  860. };
  861. EXPORT_SYMBOL(s3c_device_keypad_qisda);
  862. //Qisda Tony 090324, add keypad ]
  863. //Qisda Tony 090406, add Auo touch i2c driver [
  864. static struct resource s3c_ts_iic_resource[] = {
  865. [0] = {
  866. .start = S3C24XX_PA_GPIO+0x50,
  867. .end = S3C24XX_PA_GPIO +0x50 + S3C24XX_SZ_GPIO - 1,
  868. .flags = IORESOURCE_MEM,
  869. },
  870. [1] = {
  871. .start = IRQ_EINT3,
  872. .end = IRQ_EINT3,
  873. .flags = IORESOURCE_IRQ,
  874. }
  875. };
  876. struct platform_device s3c_device_ts_iic = {
  877. .name = "s3c2410-ts-iic",
  878. .id = -1,
  879. .num_resources = ARRAY_SIZE(s3c_ts_iic_resource),
  880. .resource = s3c_ts_iic_resource,
  881. };
  882. EXPORT_SYMBOL(s3c_device_ts_iic);
  883. //Qisda Tony 090406, add Auo touch i2c driver ]
  884. #else
  885. /* HS-MMC controller */
  886. extern struct s3c_hsmmc_cfg s3c_hsmmc_platform;
  887. static struct resource s3c_hsmmc_resource[] = {
  888. [0] = {
  889. .start = S3C_PA_HSMMC,
  890. .end = S3C_PA_HSMMC+ S3C_SZ_HSMMC,
  891. .flags = IORESOURCE_MEM,
  892. },
  893. [1] = {
  894. .start = IRQ_SDI_1,
  895. .end = IRQ_SDI_1,
  896. .flags = IORESOURCE_IRQ,
  897. }
  898. };
  899. struct platform_device s3c_device_hsmmc = {
  900. .name = "s3c-hsmmc",
  901. .id = 0,
  902. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  903. .resource = s3c_hsmmc_resource,
  904. .dev = {
  905. .platform_data = &s3c_hsmmc_platform,
  906. }
  907. };
  908. EXPORT_SYMBOL(s3c_device_hsmmc);
  909. #endif
  910. #endif // CONFIG_CPU_S32443
  911. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  912. /* For High speed MMC */
  913. extern struct s3c_hsmmc_cfg s3c_hsmmc0_platform;
  914. extern struct s3c_hsmmc_cfg s3c_hsmmc1_platform;
  915. extern struct s3c_hsmmc_cfg s3c_hsmmc2_platform;
  916. static struct resource s3c_hsmmc0_resource[] = {
  917. [0] = {
  918. .start = S3C_PA_HSMMC,
  919. .end = S3C_PA_HSMMC+S3C_SZ_HSMMC-1,
  920. .flags = IORESOURCE_MEM,
  921. },
  922. [1] = {
  923. .start = IRQ_HSMMC0,
  924. .end = IRQ_HSMMC0,
  925. .flags = IORESOURCE_IRQ,
  926. },
  927. /* To detect a card inserted, use an external interrupt */
  928. [2] = {
  929. .start = IRQ_EINT13,
  930. .end = IRQ_EINT13,
  931. .flags = IORESOURCE_IRQ,
  932. }
  933. };
  934. static struct resource s3c_hsmmc1_resource[] = {
  935. [0] = {
  936. .start = S3C_PA_HSMMC+0x100000,
  937. .end = S3C_PA_HSMMC+0x100000+S3C_SZ_HSMMC-1,
  938. .flags = IORESOURCE_MEM,
  939. },
  940. [1] = {
  941. .start = IRQ_HSMMC1,
  942. .end = IRQ_HSMMC1,
  943. .flags = IORESOURCE_IRQ,
  944. }
  945. };
  946. static struct resource s3c_hsmmc2_resource[] = {
  947. [0] = {
  948. .start = S3C_PA_HSMMC+0x200000,
  949. .end = S3C_PA_HSMMC+0x200000+S3C_SZ_HSMMC-1,
  950. .flags = IORESOURCE_MEM,
  951. },
  952. [1] = {
  953. .start = IRQ_HSMMC2,
  954. .end = IRQ_HSMMC2,
  955. .flags = IORESOURCE_IRQ,
  956. },
  957. [2] = {
  958. #if defined(CONFIG_MACH_SANJOSE2)
  959. .start = IRQ_EINT12,
  960. .end = IRQ_EINT12,
  961. #else
  962. .start = IRQ_EINT15,
  963. .end = IRQ_EINT15,
  964. #endif
  965. .flags = IORESOURCE_IRQ,
  966. }
  967. };
  968. struct platform_device s3c_device_hsmmc0 = {
  969. .name = "s3c-hsmmc",
  970. .id = 0,
  971. .num_resources = ARRAY_SIZE(s3c_hsmmc0_resource),
  972. .resource = s3c_hsmmc0_resource,
  973. .dev = {
  974. .platform_data = &s3c_hsmmc0_platform,
  975. }
  976. };
  977. struct platform_device s3c_device_hsmmc1 = {
  978. .name = "s3c-hsmmc",
  979. .id = 1,
  980. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  981. .resource = s3c_hsmmc1_resource,
  982. .dev = {
  983. .platform_data = &s3c_hsmmc1_platform,
  984. }
  985. };
  986. struct platform_device s3c_device_hsmmc2 = {
  987. .name = "s3c-hsmmc",
  988. .id = 2,
  989. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  990. .resource = s3c_hsmmc2_resource,
  991. .dev = {
  992. .platform_data = &s3c_hsmmc2_platform,
  993. }
  994. };
  995. EXPORT_SYMBOL(s3c_device_hsmmc0);
  996. EXPORT_SYMBOL(s3c_device_hsmmc1);
  997. EXPORT_SYMBOL(s3c_device_hsmmc2);
  998. /* 2D interface */
  999. static struct resource s3c_2d_resource[] = {
  1000. [0] = {
  1001. .start = S3C6400_PA_2D,
  1002. .end = S3C6400_PA_2D + S3C_SZ_2D - 1,
  1003. .flags = IORESOURCE_MEM,
  1004. },
  1005. [1] = {
  1006. .start = IRQ_2D,
  1007. .end = IRQ_2D,
  1008. .flags = IORESOURCE_IRQ,
  1009. }
  1010. };
  1011. struct platform_device s3c_device_2d = {
  1012. .name = "s3c-2d",
  1013. .id = -1,
  1014. .num_resources = ARRAY_SIZE(s3c_2d_resource),
  1015. .resource = s3c_2d_resource
  1016. };
  1017. EXPORT_SYMBOL(s3c_device_2d);
  1018. /* rotator interface */
  1019. static struct resource s3c_rotator_resource[] = {
  1020. [0] = {
  1021. .start = S3C6400_PA_ROTATOR,
  1022. .end = S3C6400_PA_ROTATOR + S3C_SZ_ROTATOR - 1,
  1023. .flags = IORESOURCE_MEM,
  1024. },
  1025. [1] = {
  1026. .start = IRQ_ROTATOR,
  1027. .end = IRQ_ROTATOR,
  1028. .flags = IORESOURCE_IRQ,
  1029. }
  1030. };
  1031. struct platform_device s3c_device_rotator = {
  1032. .name = "s3c-rotator",
  1033. .id = -1,
  1034. .num_resources = ARRAY_SIZE(s3c_rotator_resource),
  1035. .resource = s3c_rotator_resource
  1036. };
  1037. EXPORT_SYMBOL(s3c_device_rotator);
  1038. #if defined(CONFIG_CPU_S3C6410) && !defined(CONFIG_MACH_SMDK6430) /* SMDK6430 : 3D Masking */
  1039. /* 3D interface */
  1040. static struct resource s3c_g3d_resource[] = {
  1041. [0] = {
  1042. .start = S3C6410_PA_G3D,
  1043. .end = S3C6410_PA_G3D + S3C6410_SZ_G3D - 1,
  1044. .flags = IORESOURCE_MEM,
  1045. },
  1046. [1] = {
  1047. .start = IRQ_G3D,
  1048. .end = IRQ_G3D,
  1049. .flags = IORESOURCE_IRQ,
  1050. }
  1051. };
  1052. struct platform_device s3c_device_g3d = {
  1053. .name = "s3c-g3d",
  1054. .id = -1,
  1055. .num_resources = ARRAY_SIZE(s3c_g3d_resource),
  1056. .resource = s3c_g3d_resource
  1057. };
  1058. EXPORT_SYMBOL(s3c_device_g3d);
  1059. #endif
  1060. /* tv encoder */
  1061. static struct resource s3c_tvenc_resource[] = {
  1062. [0] = {
  1063. .start = S3C24XX_PA_TVENC,
  1064. .end = S3C24XX_PA_TVENC + S3C_SZ_TVENC - 1,
  1065. .flags = IORESOURCE_MEM,
  1066. },
  1067. [1] = {
  1068. .start = IRQ_TVENC,
  1069. .end = IRQ_TVENC,
  1070. .flags = IORESOURCE_IRQ,
  1071. }
  1072. };
  1073. struct platform_device s3c_device_tvenc = {
  1074. .name = "s3c6400-tvenc",
  1075. .id = -1,
  1076. .num_resources = ARRAY_SIZE(s3c_tvenc_resource),
  1077. .resource = s3c_tvenc_resource,
  1078. };
  1079. EXPORT_SYMBOL(s3c_device_tvenc);
  1080. /* timer 3 */
  1081. static struct resource s3c_tvscaler_resource[] = {
  1082. [0] = {
  1083. .start = S3C24XX_PA_TVSCALER,
  1084. .end = S3C24XX_PA_TVSCALER + S3C_SZ_TVSCALER - 1,
  1085. .flags = IORESOURCE_MEM,
  1086. },
  1087. [1] = {
  1088. .start = IRQ_SCALER,
  1089. .end = IRQ_SCALER,
  1090. .flags = IORESOURCE_IRQ,
  1091. }
  1092. };
  1093. struct platform_device s3c_device_tvscaler = {
  1094. .name = "s3c6400-tvscaler",
  1095. .id = -1,
  1096. .num_resources = ARRAY_SIZE(s3c_tvscaler_resource),
  1097. .resource = s3c_tvscaler_resource,
  1098. };
  1099. EXPORT_SYMBOL(s3c_device_tvscaler);
  1100. /* Camif Controller */
  1101. static struct resource s3c_camif_resource[] = {
  1102. [0] = {
  1103. .start = S3C6400_PA_CAMIF,
  1104. .end = S3C6400_PA_CAMIF + S3C24XX_SZ_CAMIF - 1,
  1105. .flags = IORESOURCE_MEM,
  1106. },
  1107. [1] = {
  1108. .start = IRQ_CAMIF_C,
  1109. .end = IRQ_CAMIF_C,
  1110. .flags = IORESOURCE_IRQ,
  1111. },
  1112. [2] = {
  1113. .start = IRQ_CAMIF_P,
  1114. .end = IRQ_CAMIF_P,
  1115. .flags = IORESOURCE_IRQ,
  1116. }
  1117. };
  1118. static u64 s3c_device_camif_dmamask = 0xffffffffUL;
  1119. struct platform_device s3c_device_camif = {
  1120. .name = "s3c-camif",
  1121. .id = -1,
  1122. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  1123. .resource = s3c_camif_resource,
  1124. .dev = {
  1125. .dma_mask = &s3c_device_camif_dmamask,
  1126. .coherent_dma_mask = 0xffffffffUL
  1127. }
  1128. };
  1129. EXPORT_SYMBOL(s3c_device_camif);
  1130. #if !defined(CONFIG_MACH_SMDK6430) /* SMDK6430 : MFC Masking */
  1131. static struct resource s3c_mfc_resource[] = {
  1132. [0] = {
  1133. .start = S3C6400_PA_MFC,
  1134. .end = S3C6400_PA_MFC + SZ_4K - 1,
  1135. .flags = IORESOURCE_MEM,
  1136. },
  1137. [1] = {
  1138. .start = IRQ_MFC,
  1139. .end = IRQ_MFC,
  1140. .flags = IORESOURCE_IRQ,
  1141. }
  1142. };
  1143. struct platform_device s3c_device_mfc = {
  1144. .name = "s3c-mfc",
  1145. .id = -1,
  1146. .num_resources = ARRAY_SIZE(s3c_mfc_resource),
  1147. .resource = s3c_mfc_resource
  1148. };
  1149. EXPORT_SYMBOL(s3c_device_mfc);
  1150. #endif
  1151. static struct resource s3c_jpeg_resource[] = {
  1152. [0] = {
  1153. .start = S3C6400_PA_JPEG,
  1154. .end = S3C6400_PA_JPEG + S3C_SZ_JPEG - 1,
  1155. .flags = IORESOURCE_MEM,
  1156. },
  1157. [1] = {
  1158. .start = IRQ_JPEG,
  1159. .end = IRQ_JPEG,
  1160. .flags = IORESOURCE_IRQ,
  1161. }
  1162. };
  1163. struct platform_device s3c_device_jpeg = {
  1164. .name = "s3c-jpeg",
  1165. .id = -1,
  1166. .num_resources = ARRAY_SIZE(s3c_jpeg_resource),
  1167. .resource = s3c_jpeg_resource,
  1168. };
  1169. EXPORT_SYMBOL(s3c_device_jpeg);
  1170. static struct resource s3c_vpp_resource[] = {
  1171. [0] = {
  1172. .start = S3C6400_PA_VPP,
  1173. .end = S3C6400_PA_VPP + S3C_SZ_VPP - 1,
  1174. .flags = IORESOURCE_MEM,
  1175. },
  1176. [1] = {
  1177. .start = IRQ_POST0,
  1178. .end = IRQ_POST0,
  1179. .flags = IORESOURCE_IRQ,
  1180. }
  1181. };
  1182. struct platform_device s3c_device_vpp = {
  1183. .name = "s3c-vpp",
  1184. .id = -1,
  1185. .num_resources = ARRAY_SIZE(s3c_vpp_resource),
  1186. .resource = s3c_vpp_resource,
  1187. };
  1188. EXPORT_SYMBOL(s3c_device_vpp);
  1189. static struct resource s3c_ide_resource[] = {
  1190. [0] = {
  1191. .start = S3C24XX_PA_CFATA,
  1192. .end = S3C24XX_PA_CFATA + S3C_SZ_CFATA - 1,
  1193. .flags = IORESOURCE_MEM,
  1194. },
  1195. [1] = {
  1196. .start = IRQ_CFCON,
  1197. .end = IRQ_CFCON,
  1198. .flags = IORESOURCE_IRQ,
  1199. }
  1200. };
  1201. struct platform_device s3c_device_ide = {
  1202. .name = "s3c-ide",
  1203. .id = 0,
  1204. .num_resources = ARRAY_SIZE(s3c_ide_resource),
  1205. .resource = s3c_ide_resource,
  1206. };
  1207. EXPORT_SYMBOL(s3c_device_ide);
  1208. /* Keypad Interface */
  1209. static struct resource s3c_keypad_resource[] = {
  1210. [0] = {
  1211. .start = S3C24XX_PA_KEYPAD,
  1212. .end = S3C24XX_PA_KEYPAD+ S3C24XX_SZ_KEYPAD - 1,
  1213. .flags = IORESOURCE_MEM,
  1214. },
  1215. [1] = {
  1216. .start = IRQ_KEYPAD,
  1217. .end = IRQ_KEYPAD,
  1218. .flags = IORESOURCE_IRQ,
  1219. }
  1220. };
  1221. struct platform_device s3c_device_keypad = {
  1222. .name = "s3c-keypad",
  1223. .id = -1,
  1224. .num_resources = ARRAY_SIZE(s3c_keypad_resource),
  1225. .resource = s3c_keypad_resource,
  1226. };
  1227. EXPORT_SYMBOL(s3c_device_keypad);
  1228. #endif // CONFIG_CPU_S3C6400
  1229. #if defined (CONFIG_CPU_S3C6410) || defined (CONFIG_CPU_S3C2450)
  1230. static struct resource s3c_smc911x_resources[] = {
  1231. [0] = {
  1232. .start = S3C_PA_SMC9115,
  1233. .end = S3C_PA_SMC9115 + 0x1fffffff,
  1234. .flags = IORESOURCE_MEM,
  1235. },
  1236. [1] = {
  1237. #if defined(CONFIG_CPU_S3C6410)
  1238. .start = IRQ_EINT10,
  1239. .end = IRQ_EINT10,
  1240. #elif defined(CONFIG_CPU_S3C2450)
  1241. .start = IRQ_EINT4,
  1242. .end = IRQ_EINT4,
  1243. #endif
  1244. .flags = IORESOURCE_IRQ,
  1245. },
  1246. };
  1247. struct platform_device s3c_device_smc911x = {
  1248. .name = "smc911x",
  1249. .id = -1,
  1250. .num_resources = ARRAY_SIZE(s3c_smc911x_resources),
  1251. .resource = s3c_smc911x_resources,
  1252. };
  1253. EXPORT_SYMBOL(s3c_device_smc911x);
  1254. #endif