cpu.c 12 KB

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  1. /* linux/arch/arm/plat-s3c24xx/cpu.c
  2. *
  3. * Copyright (c) 2004-2005 Simtec Electronics
  4. * http://www.simtec.co.uk/products/SWLINUX/
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * S3C24XX CPU Support
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/ioport.h>
  27. #include <linux/serial_core.h>
  28. #include <linux/platform_device.h>
  29. #include <asm/hardware.h>
  30. #include <asm/irq.h>
  31. #include <asm/io.h>
  32. #include <asm/delay.h>
  33. #include <asm/mach/arch.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/arch/regs-gpio.h>
  36. #include <asm/arch/regs-serial.h>
  37. #include <asm/plat-s3c24xx/cpu.h>
  38. #include <asm/plat-s3c24xx/devs.h>
  39. #include <asm/plat-s3c24xx/clock.h>
  40. #include <asm/plat-s3c24xx/s3c2400.h>
  41. #include <asm/plat-s3c24xx/s3c2410.h>
  42. #include <asm/plat-s3c24xx/s3c2412.h>
  43. #include "s3c244x.h"
  44. #include <asm/plat-s3c24xx/s3c2440.h>
  45. #include <asm/plat-s3c24xx/s3c2442.h>
  46. #include <asm/plat-s3c24xx/s3c2443.h>
  47. #include <asm/plat-s3c24xx/s3c2416.h>
  48. #include <asm/plat-s3c24xx/s3c2450.h>
  49. #include <asm/plat-s3c24xx/s3c6400.h>
  50. struct cpu_table {
  51. unsigned long idcode;
  52. unsigned long idmask;
  53. void (*map_io)(struct map_desc *mach_desc, int size);
  54. void (*init_uarts)(struct s3c2410_uartcfg *cfg, int no);
  55. void (*init_clocks)(int xtal);
  56. int (*init)(void);
  57. const char *name;
  58. };
  59. /* table of supported CPUs */
  60. static const char name_s3c2400[] = "S3C2400";
  61. static const char name_s3c2410[] = "S3C2410";
  62. static const char name_s3c2412[] = "S3C2412";
  63. static const char name_s3c2416a[] = "S3C2416 EVT2";
  64. static const char name_s3c2416b[] = "S3C2416 EVT3";
  65. static const char name_s3c2416[] = "S3C2416";
  66. static const char name_s3c2440[] = "S3C2440";
  67. static const char name_s3c2442[] = "S3C2442";
  68. static const char name_s3c2443[] = "S3C2443";
  69. static const char name_s3c2450[] = "S3C2450";
  70. static const char name_s3c2450a[] = "S3C2450 EVT2";
  71. static const char name_s3c2450b[] = "S3C2450 EVT3";
  72. static const char name_s3c2410a[] = "S3C2410A";
  73. static const char name_s3c2440a[] = "S3C2440A";
  74. static const char name_s3c6400[] = "S3C6400";
  75. static const char name_s3c6410[] = "S3C6410";
  76. static struct cpu_table cpu_ids[] __initdata = {
  77. {
  78. .idcode = 0x32410000,
  79. .idmask = 0xffffffff,
  80. .map_io = s3c2410_map_io,
  81. .init_clocks = s3c2410_init_clocks,
  82. .init_uarts = s3c2410_init_uarts,
  83. .init = s3c2410_init,
  84. .name = name_s3c2410
  85. },
  86. {
  87. .idcode = 0x32410002,
  88. .idmask = 0xffffffff,
  89. .map_io = s3c2410_map_io,
  90. .init_clocks = s3c2410_init_clocks,
  91. .init_uarts = s3c2410_init_uarts,
  92. .init = s3c2410_init,
  93. .name = name_s3c2410a
  94. },
  95. {
  96. .idcode = 0x32440000,
  97. .idmask = 0xffffffff,
  98. .map_io = s3c244x_map_io,
  99. .init_clocks = s3c244x_init_clocks,
  100. .init_uarts = s3c244x_init_uarts,
  101. .init = s3c2440_init,
  102. .name = name_s3c2440
  103. },
  104. {
  105. .idcode = 0x32440001,
  106. .idmask = 0xffffffff,
  107. .map_io = s3c244x_map_io,
  108. .init_clocks = s3c244x_init_clocks,
  109. .init_uarts = s3c244x_init_uarts,
  110. .init = s3c2440_init,
  111. .name = name_s3c2440a
  112. },
  113. {
  114. .idcode = 0x32440aaa,
  115. .idmask = 0xffffffff,
  116. .map_io = s3c244x_map_io,
  117. .init_clocks = s3c244x_init_clocks,
  118. .init_uarts = s3c244x_init_uarts,
  119. .init = s3c2442_init,
  120. .name = name_s3c2442
  121. },
  122. {
  123. .idcode = 0x32412001,
  124. .idmask = 0xffffffff,
  125. .map_io = s3c2412_map_io,
  126. .init_clocks = s3c2412_init_clocks,
  127. .init_uarts = s3c2412_init_uarts,
  128. .init = s3c2412_init,
  129. .name = name_s3c2412,
  130. },
  131. { /* a newer version of the s3c2412 */
  132. .idcode = 0x32412003,
  133. .idmask = 0xffffffff,
  134. .map_io = s3c2412_map_io,
  135. .init_clocks = s3c2412_init_clocks,
  136. .init_uarts = s3c2412_init_uarts,
  137. .init = s3c2412_init,
  138. .name = name_s3c2412,
  139. },
  140. {
  141. .idcode = 0x32443001,
  142. .idmask = 0xffffffff,
  143. .map_io = s3c2443_map_io,
  144. .init_clocks = s3c2443_init_clocks,
  145. .init_uarts = s3c2443_init_uarts,
  146. .init = s3c2443_init,
  147. .name = name_s3c2443,
  148. },
  149. /* TODO */
  150. #if defined(CONFIG_CPU_S3C2416)
  151. { /* same with s3c2450 */
  152. .idcode = 0x32450001,
  153. .idmask = 0xffffffff,
  154. .map_io = s3c2416_map_io,
  155. .init_clocks = s3c2416_init_clocks,
  156. .init_uarts = s3c2416_init_uarts,
  157. .init = s3c2416_init,
  158. .name = name_s3c2416,
  159. },
  160. { /* Evt2 s3c2416 */
  161. .idcode = 0x32450002,
  162. .idmask = 0xffffffff,
  163. .map_io = s3c2416_map_io,
  164. .init_clocks = s3c2416_init_clocks,
  165. .init_uarts = s3c2416_init_uarts,
  166. .init = s3c2416_init,
  167. .name = name_s3c2416a,
  168. },
  169. { /* Evt3 s3c2416 */
  170. .idcode = 0x32450003,
  171. .idmask = 0xffffffff,
  172. .map_io = s3c2416_map_io,
  173. .init_clocks = s3c2416_init_clocks,
  174. .init_uarts = s3c2416_init_uarts,
  175. .init = s3c2416_init,
  176. .name = name_s3c2416b,
  177. },
  178. #elif defined(CONFIG_CPU_S3C2450)
  179. { /* almost same as s3c2443 */
  180. .idcode = 0x32450001,
  181. .idmask = 0xffffffff,
  182. .map_io = s3c2450_map_io,
  183. .init_clocks = s3c2450_init_clocks,
  184. .init_uarts = s3c2450_init_uarts,
  185. .init = s3c2450_init,
  186. .name = name_s3c2450,
  187. },
  188. { /* Evt2 s3c2450 */
  189. .idcode = 0x32450002,
  190. .idmask = 0xffffffff,
  191. .map_io = s3c2450_map_io,
  192. .init_clocks = s3c2450_init_clocks,
  193. .init_uarts = s3c2450_init_uarts,
  194. .init = s3c2450_init,
  195. .name = name_s3c2450a,
  196. },
  197. { /* Evt2 s3c2450 */
  198. .idcode = 0x32450003,
  199. .idmask = 0xffffffff,
  200. .map_io = s3c2450_map_io,
  201. .init_clocks = s3c2450_init_clocks,
  202. .init_uarts = s3c2450_init_uarts,
  203. .init = s3c2450_init,
  204. .name = name_s3c2450b,
  205. },
  206. { /* Evt3 s3c2450 */
  207. .idcode = 0x32450003,
  208. .idmask = 0xffffffff,
  209. .map_io = s3c2450_map_io,
  210. .init_clocks = s3c2450_init_clocks,
  211. .init_uarts = s3c2450_init_uarts,
  212. .init = s3c2450_init,
  213. .name = name_s3c2450b,
  214. },
  215. #endif
  216. {
  217. .idcode = 0x0, /* S3C2400 doesn't have an idcode */
  218. .idcode = 0x36400100,
  219. .map_io = s3c2400_map_io,
  220. .init_clocks = s3c2400_init_clocks,
  221. .init_uarts = s3c2400_init_uarts,
  222. .init = s3c2400_init,
  223. .name = name_s3c2400
  224. },
  225. {
  226. .idcode = 0x36400100,
  227. .idmask = 0xfffffff0,
  228. .map_io = s3c6400_map_io,
  229. .init_clocks = s3c6400_init_clocks,
  230. .init_uarts = s3c6400_init_uarts,
  231. .init = s3c6400_init,
  232. .name = name_s3c6400
  233. },
  234. {
  235. .idcode = 0x36410100,
  236. .idmask = 0xfffffff0,
  237. .map_io = s3c6400_map_io,
  238. .init_clocks = s3c6400_init_clocks,
  239. .init_uarts = s3c6400_init_uarts,
  240. .init = s3c6400_init,
  241. .name = name_s3c6410
  242. },
  243. };
  244. /* minimal IO mapping */
  245. static struct map_desc s3c_iodesc[] __initdata = {
  246. IODESC_ENT(GPIO),
  247. IODESC_ENT(IRQ),
  248. IODESC_ENT(UART),
  249. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  250. IODESC_ENT(MEMCTRL)
  251. #else
  252. IODESC_ENT(SROMC),
  253. IODESC_ENT(DMC0),
  254. IODESC_ENT(DMC1),
  255. IODESC_ENT(SYSCON)
  256. #endif
  257. };
  258. static struct cpu_table *
  259. s3c_lookup_cpu(unsigned long idcode)
  260. {
  261. struct cpu_table *tab;
  262. int count;
  263. tab = cpu_ids;
  264. for (count = 0; count < ARRAY_SIZE(cpu_ids); count++, tab++) {
  265. if ((idcode & tab->idmask) == tab->idcode)
  266. return tab;
  267. }
  268. return NULL;
  269. }
  270. /* board information */
  271. static struct s3c24xx_board *board;
  272. void s3c24xx_set_board(struct s3c24xx_board *b)
  273. {
  274. int i;
  275. board = b;
  276. if (b->clocks_count != 0) {
  277. struct clk **ptr = b->clocks;
  278. for (i = b->clocks_count; i > 0; i--, ptr++)
  279. if (s3c24xx_register_clock(*ptr) < 0)
  280. printk(KERN_ERR "failed to register clock.\n");
  281. }
  282. }
  283. /* cpu information */
  284. static struct cpu_table *cpu;
  285. /* For S3C6400 EVT1/S3C6410 */
  286. static unsigned long s3c64xx_read_idcode_v6(void)
  287. {
  288. #if !defined(CONFIG_CPU_S3C6400)
  289. return __raw_readl(S3C24XX_VA_SYSCON+0x118);
  290. #else
  291. return 0x36400100;
  292. #endif
  293. }
  294. static unsigned long s3c24xx_read_idcode_v5(void)
  295. {
  296. #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
  297. return __raw_readl(S3C2412_GSTATUS1);
  298. #elif defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  299. return __raw_readl(S3C2410_GSTATUS1);
  300. #else
  301. return 1UL; /* don't look like an 2400 */
  302. #endif
  303. }
  304. static unsigned long s3c24xx_read_idcode_v4(void)
  305. {
  306. #ifndef CONFIG_CPU_S3C2400
  307. return __raw_readl(S3C2410_GSTATUS1);
  308. #else
  309. return 0UL;
  310. #endif
  311. }
  312. void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
  313. {
  314. unsigned long idcode = 0x0;
  315. /* initialise the io descriptors we need for initialisation */
  316. iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
  317. if (cpu_architecture() >= CPU_ARCH_ARMv6) {
  318. idcode = s3c64xx_read_idcode_v6();
  319. } else if (cpu_architecture() >= CPU_ARCH_ARMv5) {
  320. idcode = s3c24xx_read_idcode_v5();
  321. } else if (cpu_architecture() >= CPU_ARCH_ARMv4) {
  322. idcode = s3c24xx_read_idcode_v4();
  323. } else {
  324. panic("Unknown CPU Architecture");
  325. idcode = 1UL; /* Unknown and error */
  326. }
  327. cpu = s3c_lookup_cpu(idcode);
  328. if (cpu == NULL) {
  329. printk(KERN_ERR "Unknown CPU type 0x%08lx\n", idcode);
  330. panic("Unknown S3C24XX CPU");
  331. }
  332. printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
  333. if (cpu->map_io == NULL || cpu->init == NULL) {
  334. printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
  335. panic("Unsupported S3C24XX CPU");
  336. }
  337. (cpu->map_io)(mach_desc, size);
  338. }
  339. /* s3c24xx_init_clocks
  340. *
  341. * Initialise the clock subsystem and associated information from the
  342. * given master crystal value.
  343. *
  344. * xtal = 0 -> use default PLL crystal value (normally 12MHz)
  345. * != 0 -> PLL crystal value in Hz
  346. */
  347. void __init s3c24xx_init_clocks(int xtal)
  348. {
  349. if (xtal == 0)
  350. xtal = 12*1000*1000;
  351. if (cpu == NULL)
  352. panic("s3c24xx_init_clocks: no cpu setup?\n");
  353. if (cpu->init_clocks == NULL)
  354. panic("s3c24xx_init_clocks: cpu has no clock init\n");
  355. else
  356. (cpu->init_clocks)(xtal);
  357. }
  358. /* uart management */
  359. static int nr_uarts __initdata = 0;
  360. static struct s3c2410_uartcfg uart_cfgs[4];
  361. /* s3c24xx_init_uartdevs
  362. *
  363. * copy the specified platform data and configuration into our central
  364. * set of devices, before the data is thrown away after the init process.
  365. *
  366. * This also fills in the array passed to the serial driver for the
  367. * early initialisation of the console.
  368. */
  369. void __init s3c24xx_init_uartdevs(char *name,
  370. struct s3c24xx_uart_resources *res,
  371. struct s3c2410_uartcfg *cfg, int no)
  372. {
  373. struct platform_device *platdev;
  374. struct s3c2410_uartcfg *cfgptr = uart_cfgs;
  375. struct s3c24xx_uart_resources *resp;
  376. int uart;
  377. memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
  378. for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
  379. platdev = s3c24xx_uart_src[cfgptr->hwport];
  380. resp = res + cfgptr->hwport;
  381. s3c24xx_uart_devs[uart] = platdev;
  382. platdev->name = name;
  383. platdev->resource = resp->resources;
  384. platdev->num_resources = resp->nr_resources;
  385. platdev->dev.platform_data = cfgptr;
  386. }
  387. nr_uarts = no;
  388. }
  389. void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  390. {
  391. if (cpu == NULL)
  392. return;
  393. if (cpu->init_uarts == NULL) {
  394. printk(KERN_ERR "s3c24xx_init_uarts: cpu has no uart init\n");
  395. } else
  396. (cpu->init_uarts)(cfg, no);
  397. }
  398. static int __init s3c_arch_init(void)
  399. {
  400. int ret;
  401. // do the correct init for cpu
  402. if (cpu == NULL)
  403. panic("s3c_arch_init: NULL cpu\n");
  404. ret = (cpu->init)();
  405. if (ret != 0)
  406. return ret;
  407. ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
  408. if (ret != 0)
  409. return ret;
  410. if (board != NULL) {
  411. struct platform_device **ptr = board->devices;
  412. int i;
  413. for (i = 0; i < board->devices_count; i++, ptr++) {
  414. ret = platform_device_register(*ptr);
  415. if (ret) {
  416. printk(KERN_ERR "s3c24xx: failed to add board device %s (%d) @%p\n", (*ptr)->name, ret, *ptr);
  417. }
  418. }
  419. /* mask any error, we may not need all these board
  420. * devices */
  421. ret = 0;
  422. }
  423. return ret;
  424. }
  425. arch_initcall(s3c_arch_init);