clock.c 10 KB

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  1. /* linux/arch/arm/plat-s3c24xx/clock.c
  2. *
  3. * Copyright (c) 2004-2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C24XX Core clock control support
  7. *
  8. * Based on, and code from linux/arch/arm/mach-versatile/clock.c
  9. **
  10. ** Copyright (C) 2004 ARM Limited.
  11. ** Written by Deep Blue Solutions Limited.
  12. *
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  27. */
  28. #include <linux/init.h>
  29. #include <linux/module.h>
  30. #include <linux/kernel.h>
  31. #include <linux/list.h>
  32. #include <linux/errno.h>
  33. #include <linux/err.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/sysdev.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/ioport.h>
  38. #include <linux/clk.h>
  39. #include <linux/mutex.h>
  40. #include <linux/delay.h>
  41. #include <asm/hardware.h>
  42. #include <asm/irq.h>
  43. #include <asm/io.h>
  44. #include <asm/arch/regs-clock.h>
  45. #include <asm/arch/regs-gpio.h>
  46. #include <asm/plat-s3c24xx/clock.h>
  47. #include <asm/plat-s3c24xx/cpu.h>
  48. /* clock information */
  49. static LIST_HEAD(clocks);
  50. DEFINE_MUTEX(clocks_mutex);
  51. /* enable and disable calls for use with the clk struct */
  52. static int clk_null_enable(struct clk *clk, int enable)
  53. {
  54. return 0;
  55. }
  56. /* Clock API calls */
  57. struct clk *clk_get(struct device *dev, const char *id)
  58. {
  59. struct clk *p;
  60. struct clk *clk = ERR_PTR(-ENOENT);
  61. int idno;
  62. if (dev == NULL || dev->bus != &platform_bus_type)
  63. idno = -1;
  64. else
  65. idno = to_platform_device(dev)->id;
  66. mutex_lock(&clocks_mutex);
  67. list_for_each_entry(p, &clocks, list) {
  68. if (p->id == idno &&
  69. strcmp(id, p->name) == 0 &&
  70. try_module_get(p->owner)) {
  71. clk = p;
  72. break;
  73. }
  74. }
  75. /* check for the case where a device was supplied, but the
  76. * clock that was being searched for is not device specific */
  77. if (IS_ERR(clk)) {
  78. list_for_each_entry(p, &clocks, list) {
  79. if (p->id == -1 && strcmp(id, p->name) == 0 &&
  80. try_module_get(p->owner)) {
  81. clk = p;
  82. break;
  83. }
  84. }
  85. }
  86. mutex_unlock(&clocks_mutex);
  87. return clk;
  88. }
  89. void clk_put(struct clk *clk)
  90. {
  91. module_put(clk->owner);
  92. }
  93. int clk_enable(struct clk *clk)
  94. {
  95. if (IS_ERR(clk) || clk == NULL)
  96. return -EINVAL;
  97. clk_enable(clk->parent);
  98. mutex_lock(&clocks_mutex);
  99. if ((clk->usage++) == 0)
  100. (clk->enable)(clk, 1);
  101. mutex_unlock(&clocks_mutex);
  102. return 0;
  103. }
  104. void clk_disable(struct clk *clk)
  105. {
  106. if (IS_ERR(clk) || clk == NULL)
  107. return;
  108. mutex_lock(&clocks_mutex);
  109. if ((--clk->usage) == 0)
  110. (clk->enable)(clk, 0);
  111. mutex_unlock(&clocks_mutex);
  112. clk_disable(clk->parent);
  113. }
  114. unsigned long clk_get_rate(struct clk *clk)
  115. {
  116. if (IS_ERR(clk))
  117. return 0;
  118. if (clk->rate != 0)
  119. return clk->rate;
  120. if (clk->get_rate != NULL)
  121. return (clk->get_rate)(clk);
  122. if (clk->parent != NULL)
  123. return clk_get_rate(clk->parent);
  124. return clk->rate;
  125. }
  126. long clk_round_rate(struct clk *clk, unsigned long rate)
  127. {
  128. if (!IS_ERR(clk) && clk->round_rate)
  129. return (clk->round_rate)(clk, rate);
  130. return rate;
  131. }
  132. int clk_set_rate(struct clk *clk, unsigned long rate)
  133. {
  134. int ret;
  135. if (IS_ERR(clk))
  136. return -EINVAL;
  137. mutex_lock(&clocks_mutex);
  138. ret = (clk->set_rate)(clk, rate);
  139. mutex_unlock(&clocks_mutex);
  140. return ret;
  141. }
  142. struct clk *clk_get_parent(struct clk *clk)
  143. {
  144. return clk->parent;
  145. }
  146. int clk_set_parent(struct clk *clk, struct clk *parent)
  147. {
  148. int ret = 0;
  149. if (IS_ERR(clk))
  150. return -EINVAL;
  151. mutex_lock(&clocks_mutex);
  152. if (clk->set_parent)
  153. ret = (clk->set_parent)(clk, parent);
  154. mutex_unlock(&clocks_mutex);
  155. return ret;
  156. }
  157. EXPORT_SYMBOL(clk_get);
  158. EXPORT_SYMBOL(clk_put);
  159. EXPORT_SYMBOL(clk_enable);
  160. EXPORT_SYMBOL(clk_disable);
  161. EXPORT_SYMBOL(clk_get_rate);
  162. EXPORT_SYMBOL(clk_round_rate);
  163. EXPORT_SYMBOL(clk_set_rate);
  164. EXPORT_SYMBOL(clk_get_parent);
  165. EXPORT_SYMBOL(clk_set_parent);
  166. /* base clocks */
  167. struct clk clk_xtal = {
  168. .name = "xtal",
  169. .id = -1,
  170. .rate = 0,
  171. .parent = NULL,
  172. .ctrlbit = 0,
  173. };
  174. struct clk clk_mpll = {
  175. .name = "mpll",
  176. .id = -1,
  177. };
  178. struct clk clk_upll = {
  179. .name = "upll",
  180. .id = -1,
  181. .parent = NULL,
  182. .ctrlbit = 0,
  183. };
  184. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  185. struct clk clk_epll = {
  186. .name = "epll",
  187. .id = -1,
  188. .rate = 0,
  189. .parent = NULL,
  190. .ctrlbit = 0,
  191. #if 0
  192. .enable =,
  193. .set_rate =,
  194. .get_rate =,
  195. #endif
  196. };
  197. #endif
  198. struct clk clk_f = {
  199. .name = "fclk",
  200. .id = -1,
  201. .rate = 0,
  202. .parent = &clk_mpll,
  203. .ctrlbit = 0,
  204. };
  205. struct clk clk_h = {
  206. .name = "hclk",
  207. .id = -1,
  208. .rate = 0,
  209. .parent = NULL,
  210. .ctrlbit = 0,
  211. };
  212. struct clk clk_p = {
  213. .name = "pclk",
  214. .id = -1,
  215. .rate = 0,
  216. .parent = NULL,
  217. .ctrlbit = 0,
  218. };
  219. struct clk clk_usb_bus = {
  220. .name = "usb-bus",
  221. .id = -1,
  222. .rate = 0,
  223. .parent = &clk_upll,
  224. };
  225. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  226. struct clk clk_hx2 = {
  227. .name = "hclkx2",
  228. .id = -1,
  229. .rate = 0,
  230. .parent = NULL,
  231. .ctrlbit = 0,
  232. };
  233. struct clk clk_s = {
  234. .name = "sclk",
  235. .id = -1,
  236. .rate = 0,
  237. .parent = NULL,
  238. .ctrlbit = 0,
  239. };
  240. struct clk clk_u = {
  241. .name = "uclk",
  242. .id = -1,
  243. .rate = 0,
  244. .parent = NULL,
  245. .ctrlbit = 0,
  246. };
  247. struct clk clk_48m = {
  248. .name = "clk48m",
  249. .id = -1,
  250. .rate = 48*1000*1000,
  251. .parent = NULL,
  252. .ctrlbit = 0,
  253. };
  254. struct clk clk_27m = {
  255. .name = "clk27m",
  256. .id = -1,
  257. .rate = 27*1000*1000,
  258. .parent = NULL,
  259. .ctrlbit = 0,
  260. };
  261. #endif
  262. /* clocks that could be registered by external code */
  263. static int s3c24xx_dclk_enable(struct clk *clk, int enable)
  264. {
  265. unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
  266. if (enable)
  267. dclkcon |= clk->ctrlbit;
  268. else
  269. dclkcon &= ~clk->ctrlbit;
  270. __raw_writel(dclkcon, S3C24XX_DCLKCON);
  271. return 0;
  272. }
  273. static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
  274. {
  275. unsigned long dclkcon;
  276. unsigned int uclk;
  277. if (parent == &clk_upll)
  278. uclk = 1;
  279. else if (parent == &clk_p)
  280. uclk = 0;
  281. else
  282. return -EINVAL;
  283. clk->parent = parent;
  284. dclkcon = __raw_readl(S3C24XX_DCLKCON);
  285. if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
  286. if (uclk)
  287. dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
  288. else
  289. dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
  290. } else {
  291. if (uclk)
  292. dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
  293. else
  294. dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
  295. }
  296. __raw_writel(dclkcon, S3C24XX_DCLKCON);
  297. return 0;
  298. }
  299. static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
  300. {
  301. unsigned long mask;
  302. unsigned long source;
  303. /* calculate the MISCCR setting for the clock */
  304. if (parent == &clk_xtal)
  305. source = S3C2410_MISCCR_CLK0_MPLL;
  306. else if (parent == &clk_upll)
  307. source = S3C2410_MISCCR_CLK0_UPLL;
  308. else if (parent == &clk_f)
  309. source = S3C2410_MISCCR_CLK0_FCLK;
  310. else if (parent == &clk_h)
  311. source = S3C2410_MISCCR_CLK0_HCLK;
  312. else if (parent == &clk_p)
  313. source = S3C2410_MISCCR_CLK0_PCLK;
  314. else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
  315. source = S3C2410_MISCCR_CLK0_DCLK0;
  316. else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
  317. source = S3C2410_MISCCR_CLK0_DCLK0;
  318. else
  319. return -EINVAL;
  320. clk->parent = parent;
  321. if (clk == &s3c24xx_dclk0)
  322. mask = S3C2410_MISCCR_CLK0_MASK;
  323. else {
  324. source <<= 4;
  325. mask = S3C2410_MISCCR_CLK1_MASK;
  326. }
  327. s3c2410_modify_misccr(mask, source);
  328. return 0;
  329. }
  330. /* external clock definitions */
  331. struct clk s3c24xx_dclk0 = {
  332. .name = "dclk0",
  333. .id = -1,
  334. .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
  335. .enable = s3c24xx_dclk_enable,
  336. .set_parent = s3c24xx_dclk_setparent,
  337. };
  338. struct clk s3c24xx_dclk1 = {
  339. .name = "dclk1",
  340. .id = -1,
  341. .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
  342. .enable = s3c24xx_dclk_enable,
  343. .set_parent = s3c24xx_dclk_setparent,
  344. };
  345. struct clk s3c24xx_clkout0 = {
  346. .name = "clkout0",
  347. .id = -1,
  348. .set_parent = s3c24xx_clkout_setparent,
  349. };
  350. struct clk s3c24xx_clkout1 = {
  351. .name = "clkout1",
  352. .id = -1,
  353. .set_parent = s3c24xx_clkout_setparent,
  354. };
  355. struct clk s3c24xx_uclk = {
  356. .name = "uclk",
  357. .id = -1,
  358. };
  359. /* initialise the clock system */
  360. int s3c24xx_register_clock(struct clk *clk)
  361. {
  362. clk->owner = THIS_MODULE;
  363. if (clk->enable == NULL)
  364. clk->enable = clk_null_enable;
  365. /* add to the list of available clocks */
  366. mutex_lock(&clocks_mutex);
  367. list_add(&clk->list, &clocks);
  368. mutex_unlock(&clocks_mutex);
  369. return 0;
  370. }
  371. /* initalise all the clocks */
  372. int __init s3c24xx_setup_clocks(unsigned long xtal,
  373. unsigned long fclk,
  374. unsigned long hclk,
  375. unsigned long pclk)
  376. {
  377. printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n");
  378. /* initialise the main system clocks */
  379. clk_xtal.rate = xtal;
  380. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  381. clk_upll.rate = s3c2410_get_pll(__raw_readl(S3C2410_UPLLCON), xtal);
  382. #endif
  383. clk_mpll.rate = fclk;
  384. clk_h.rate = hclk;
  385. clk_p.rate = pclk;
  386. clk_f.rate = fclk;
  387. /* assume uart clocks are correctly setup */
  388. /* register our clocks */
  389. if (s3c24xx_register_clock(&clk_xtal) < 0)
  390. printk(KERN_ERR "failed to register master xtal\n");
  391. if (s3c24xx_register_clock(&clk_mpll) < 0)
  392. printk(KERN_ERR "failed to register mpll clock\n");
  393. if (s3c24xx_register_clock(&clk_upll) < 0)
  394. printk(KERN_ERR "failed to register upll clock\n");
  395. if (s3c24xx_register_clock(&clk_f) < 0)
  396. printk(KERN_ERR "failed to register cpu fclk\n");
  397. if (s3c24xx_register_clock(&clk_h) < 0)
  398. printk(KERN_ERR "failed to register cpu hclk\n");
  399. if (s3c24xx_register_clock(&clk_p) < 0)
  400. printk(KERN_ERR "failed to register cpu pclk\n");
  401. #if defined (CONFIG_CPU_S3C6400) || defined (CONFIG_CPU_S3C6410)
  402. if (s3c24xx_register_clock(&clk_epll) < 0)
  403. printk(KERN_ERR "failed to register epll clock\n");
  404. /* register hclkx2 */
  405. if (s3c24xx_register_clock(&clk_hx2) < 0)
  406. printk(KERN_ERR "failed to register cpu hclkx2\n");
  407. if (s3c24xx_register_clock(&clk_s) < 0)
  408. printk(KERN_ERR "failed to register cpu pclk\n");
  409. if (s3c24xx_register_clock(&clk_u) < 0)
  410. printk(KERN_ERR "failed to register cpu uclk\n");
  411. if (s3c24xx_register_clock(&clk_48m) < 0)
  412. printk(KERN_ERR "failed to register cpu uclk\n");
  413. if (s3c24xx_register_clock(&clk_27m) < 0)
  414. printk(KERN_ERR "failed to register cpu uclk\n");
  415. #endif
  416. return 0;
  417. }