sa1100fb.c 42 KB

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  1. /*
  2. * linux/drivers/video/sa1100fb.c
  3. *
  4. * Copyright (C) 1999 Eric A. Thomas
  5. * Based on acornfb.c Copyright (C) Russell King.
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file COPYING in the main directory of this archive for
  9. * more details.
  10. *
  11. * StrongARM 1100 LCD Controller Frame Buffer Driver
  12. *
  13. * Please direct your questions and comments on this driver to the following
  14. * email address:
  15. *
  16. * linux-arm-kernel@lists.arm.linux.org.uk
  17. *
  18. * Clean patches should be sent to the ARM Linux Patch System. Please see the
  19. * following web page for more information:
  20. *
  21. * http://www.arm.linux.org.uk/developer/patches/info.shtml
  22. *
  23. * Thank you.
  24. *
  25. * Known problems:
  26. * - With the Neponset plugged into an Assabet, LCD powerdown
  27. * doesn't work (LCD stays powered up). Therefore we shouldn't
  28. * blank the screen.
  29. * - We don't limit the CPU clock rate nor the mode selection
  30. * according to the available SDRAM bandwidth.
  31. *
  32. * Other notes:
  33. * - Linear grayscale palettes and the kernel.
  34. * Such code does not belong in the kernel. The kernel frame buffer
  35. * drivers do not expect a linear colourmap, but a colourmap based on
  36. * the VT100 standard mapping.
  37. *
  38. * If your _userspace_ requires a linear colourmap, then the setup of
  39. * such a colourmap belongs _in userspace_, not in the kernel. Code
  40. * to set the colourmap correctly from user space has been sent to
  41. * David Neuer. It's around 8 lines of C code, plus another 4 to
  42. * detect if we are using grayscale.
  43. *
  44. * - The following must never be specified in a panel definition:
  45. * LCCR0_LtlEnd, LCCR3_PixClkDiv, LCCR3_VrtSnchL, LCCR3_HorSnchL
  46. *
  47. * - The following should be specified:
  48. * either LCCR0_Color or LCCR0_Mono
  49. * either LCCR0_Sngl or LCCR0_Dual
  50. * either LCCR0_Act or LCCR0_Pas
  51. * either LCCR3_OutEnH or LCCD3_OutEnL
  52. * either LCCR3_PixRsEdg or LCCR3_PixFlEdg
  53. * either LCCR3_ACBsDiv or LCCR3_ACBsCntOff
  54. *
  55. * Code Status:
  56. * 1999/04/01:
  57. * - Driver appears to be working for Brutus 320x200x8bpp mode. Other
  58. * resolutions are working, but only the 8bpp mode is supported.
  59. * Changes need to be made to the palette encode and decode routines
  60. * to support 4 and 16 bpp modes.
  61. * Driver is not designed to be a module. The FrameBuffer is statically
  62. * allocated since dynamic allocation of a 300k buffer cannot be
  63. * guaranteed.
  64. *
  65. * 1999/06/17:
  66. * - FrameBuffer memory is now allocated at run-time when the
  67. * driver is initialized.
  68. *
  69. * 2000/04/10: Nicolas Pitre <nico@cam.org>
  70. * - Big cleanup for dynamic selection of machine type at run time.
  71. *
  72. * 2000/07/19: Jamey Hicks <jamey@crl.dec.com>
  73. * - Support for Bitsy aka Compaq iPAQ H3600 added.
  74. *
  75. * 2000/08/07: Tak-Shing Chan <tchan.rd@idthk.com>
  76. * Jeff Sutherland <jsutherland@accelent.com>
  77. * - Resolved an issue caused by a change made to the Assabet's PLD
  78. * earlier this year which broke the framebuffer driver for newer
  79. * Phase 4 Assabets. Some other parameters were changed to optimize
  80. * for the Sharp display.
  81. *
  82. * 2000/08/09: Kunihiko IMAI <imai@vasara.co.jp>
  83. * - XP860 support added
  84. *
  85. * 2000/08/19: Mark Huang <mhuang@livetoy.com>
  86. * - Allows standard options to be passed on the kernel command line
  87. * for most common passive displays.
  88. *
  89. * 2000/08/29:
  90. * - s/save_flags_cli/local_irq_save/
  91. * - remove unneeded extra save_flags_cli in sa1100fb_enable_lcd_controller
  92. *
  93. * 2000/10/10: Erik Mouw <J.A.K.Mouw@its.tudelft.nl>
  94. * - Updated LART stuff. Fixed some minor bugs.
  95. *
  96. * 2000/10/30: Murphy Chen <murphy@mail.dialogue.com.tw>
  97. * - Pangolin support added
  98. *
  99. * 2000/10/31: Roman Jordan <jor@hoeft-wessel.de>
  100. * - Huw Webpanel support added
  101. *
  102. * 2000/11/23: Eric Peng <ericpeng@coventive.com>
  103. * - Freebird add
  104. *
  105. * 2001/02/07: Jamey Hicks <jamey.hicks@compaq.com>
  106. * Cliff Brake <cbrake@accelent.com>
  107. * - Added PM callback
  108. *
  109. * 2001/05/26: <rmk@arm.linux.org.uk>
  110. * - Fix 16bpp so that (a) we use the right colours rather than some
  111. * totally random colour depending on what was in page 0, and (b)
  112. * we don't de-reference a NULL pointer.
  113. * - remove duplicated implementation of consistent_alloc()
  114. * - convert dma address types to dma_addr_t
  115. * - remove unused 'montype' stuff
  116. * - remove redundant zero inits of init_var after the initial
  117. * memzero.
  118. * - remove allow_modeset (acornfb idea does not belong here)
  119. *
  120. * 2001/05/28: <rmk@arm.linux.org.uk>
  121. * - massive cleanup - move machine dependent data into structures
  122. * - I've left various #warnings in - if you see one, and know
  123. * the hardware concerned, please get in contact with me.
  124. *
  125. * 2001/05/31: <rmk@arm.linux.org.uk>
  126. * - Fix LCCR1 HSW value, fix all machine type specifications to
  127. * keep values in line. (Please check your machine type specs)
  128. *
  129. * 2001/06/10: <rmk@arm.linux.org.uk>
  130. * - Fiddle with the LCD controller from task context only; mainly
  131. * so that we can run with interrupts on, and sleep.
  132. * - Convert #warnings into #errors. No pain, no gain. ;)
  133. *
  134. * 2001/06/14: <rmk@arm.linux.org.uk>
  135. * - Make the palette BPS value for 12bpp come out correctly.
  136. * - Take notice of "greyscale" on any colour depth.
  137. * - Make truecolor visuals use the RGB channel encoding information.
  138. *
  139. * 2001/07/02: <rmk@arm.linux.org.uk>
  140. * - Fix colourmap problems.
  141. *
  142. * 2001/07/13: <abraham@2d3d.co.za>
  143. * - Added support for the ICP LCD-Kit01 on LART. This LCD is
  144. * manufactured by Prime View, model no V16C6448AB
  145. *
  146. * 2001/07/23: <rmk@arm.linux.org.uk>
  147. * - Hand merge version from handhelds.org CVS tree. See patch
  148. * notes for 595/1 for more information.
  149. * - Drop 12bpp (it's 16bpp with different colour register mappings).
  150. * - This hardware can not do direct colour. Therefore we don't
  151. * support it.
  152. *
  153. * 2001/07/27: <rmk@arm.linux.org.uk>
  154. * - Halve YRES on dual scan LCDs.
  155. *
  156. * 2001/08/22: <rmk@arm.linux.org.uk>
  157. * - Add b/w iPAQ pixclock value.
  158. *
  159. * 2001/10/12: <rmk@arm.linux.org.uk>
  160. * - Add patch 681/1 and clean up stork definitions.
  161. */
  162. #include <linux/module.h>
  163. #include <linux/kernel.h>
  164. #include <linux/sched.h>
  165. #include <linux/errno.h>
  166. #include <linux/string.h>
  167. #include <linux/interrupt.h>
  168. #include <linux/slab.h>
  169. #include <linux/fb.h>
  170. #include <linux/delay.h>
  171. #include <linux/init.h>
  172. #include <linux/ioport.h>
  173. #include <linux/cpufreq.h>
  174. #include <linux/platform_device.h>
  175. #include <linux/dma-mapping.h>
  176. #include <asm/hardware.h>
  177. #include <asm/io.h>
  178. #include <asm/mach-types.h>
  179. #include <asm/uaccess.h>
  180. #include <asm/arch/assabet.h>
  181. #include <asm/arch/shannon.h>
  182. /*
  183. * debugging?
  184. */
  185. #define DEBUG 0
  186. /*
  187. * Complain if VAR is out of range.
  188. */
  189. #define DEBUG_VAR 1
  190. #undef ASSABET_PAL_VIDEO
  191. #include "sa1100fb.h"
  192. extern void (*sa1100fb_backlight_power)(int on);
  193. extern void (*sa1100fb_lcd_power)(int on);
  194. /*
  195. * IMHO this looks wrong. In 8BPP, length should be 8.
  196. */
  197. static struct sa1100fb_rgb rgb_8 = {
  198. .red = { .offset = 0, .length = 4, },
  199. .green = { .offset = 0, .length = 4, },
  200. .blue = { .offset = 0, .length = 4, },
  201. .transp = { .offset = 0, .length = 0, },
  202. };
  203. static struct sa1100fb_rgb def_rgb_16 = {
  204. .red = { .offset = 11, .length = 5, },
  205. .green = { .offset = 5, .length = 6, },
  206. .blue = { .offset = 0, .length = 5, },
  207. .transp = { .offset = 0, .length = 0, },
  208. };
  209. #ifdef CONFIG_SA1100_ASSABET
  210. #ifndef ASSABET_PAL_VIDEO
  211. /*
  212. * The assabet uses a sharp LQ039Q2DS54 LCD module. It is actually
  213. * takes an RGB666 signal, but we provide it with an RGB565 signal
  214. * instead (def_rgb_16).
  215. */
  216. static struct sa1100fb_mach_info lq039q2ds54_info __initdata = {
  217. .pixclock = 171521, .bpp = 16,
  218. .xres = 320, .yres = 240,
  219. .hsync_len = 5, .vsync_len = 1,
  220. .left_margin = 61, .upper_margin = 3,
  221. .right_margin = 9, .lower_margin = 0,
  222. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  223. .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
  224. .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
  225. };
  226. #else
  227. static struct sa1100fb_mach_info pal_info __initdata = {
  228. .pixclock = 67797, .bpp = 16,
  229. .xres = 640, .yres = 512,
  230. .hsync_len = 64, .vsync_len = 6,
  231. .left_margin = 125, .upper_margin = 70,
  232. .right_margin = 115, .lower_margin = 36,
  233. .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
  234. .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
  235. };
  236. #endif
  237. #endif
  238. #ifdef CONFIG_SA1100_H3800
  239. static struct sa1100fb_mach_info h3800_info __initdata = {
  240. .pixclock = 174757, .bpp = 16,
  241. .xres = 320, .yres = 240,
  242. .hsync_len = 3, .vsync_len = 3,
  243. .left_margin = 12, .upper_margin = 10,
  244. .right_margin = 17, .lower_margin = 1,
  245. .cmap_static = 1,
  246. .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
  247. .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
  248. };
  249. #endif
  250. #ifdef CONFIG_SA1100_H3600
  251. static struct sa1100fb_mach_info h3600_info __initdata = {
  252. .pixclock = 174757, .bpp = 16,
  253. .xres = 320, .yres = 240,
  254. .hsync_len = 3, .vsync_len = 3,
  255. .left_margin = 12, .upper_margin = 10,
  256. .right_margin = 17, .lower_margin = 1,
  257. .cmap_static = 1,
  258. .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
  259. .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
  260. };
  261. static struct sa1100fb_rgb h3600_rgb_16 = {
  262. .red = { .offset = 12, .length = 4, },
  263. .green = { .offset = 7, .length = 4, },
  264. .blue = { .offset = 1, .length = 4, },
  265. .transp = { .offset = 0, .length = 0, },
  266. };
  267. #endif
  268. #ifdef CONFIG_SA1100_H3100
  269. static struct sa1100fb_mach_info h3100_info __initdata = {
  270. .pixclock = 406977, .bpp = 4,
  271. .xres = 320, .yres = 240,
  272. .hsync_len = 26, .vsync_len = 41,
  273. .left_margin = 4, .upper_margin = 0,
  274. .right_margin = 4, .lower_margin = 0,
  275. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  276. .cmap_greyscale = 1,
  277. .cmap_inverse = 1,
  278. .lccr0 = LCCR0_Mono | LCCR0_4PixMono | LCCR0_Sngl | LCCR0_Pas,
  279. .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
  280. };
  281. #endif
  282. #ifdef CONFIG_SA1100_COLLIE
  283. static struct sa1100fb_mach_info collie_info __initdata = {
  284. .pixclock = 171521, .bpp = 16,
  285. .xres = 320, .yres = 240,
  286. .hsync_len = 5, .vsync_len = 1,
  287. .left_margin = 11, .upper_margin = 2,
  288. .right_margin = 30, .lower_margin = 0,
  289. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  290. .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
  291. .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(2),
  292. };
  293. #endif
  294. #ifdef LART_GREY_LCD
  295. static struct sa1100fb_mach_info lart_grey_info __initdata = {
  296. .pixclock = 150000, .bpp = 4,
  297. .xres = 320, .yres = 240,
  298. .hsync_len = 1, .vsync_len = 1,
  299. .left_margin = 4, .upper_margin = 0,
  300. .right_margin = 2, .lower_margin = 0,
  301. .cmap_greyscale = 1,
  302. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  303. .lccr0 = LCCR0_Mono | LCCR0_Sngl | LCCR0_Pas | LCCR0_4PixMono,
  304. .lccr3 = LCCR3_OutEnH | LCCR3_PixRsEdg | LCCR3_ACBsDiv(512),
  305. };
  306. #endif
  307. #ifdef LART_COLOR_LCD
  308. static struct sa1100fb_mach_info lart_color_info __initdata = {
  309. .pixclock = 150000, .bpp = 16,
  310. .xres = 320, .yres = 240,
  311. .hsync_len = 2, .vsync_len = 3,
  312. .left_margin = 69, .upper_margin = 14,
  313. .right_margin = 8, .lower_margin = 4,
  314. .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
  315. .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
  316. };
  317. #endif
  318. #ifdef LART_VIDEO_OUT
  319. static struct sa1100fb_mach_info lart_video_info __initdata = {
  320. .pixclock = 39721, .bpp = 16,
  321. .xres = 640, .yres = 480,
  322. .hsync_len = 95, .vsync_len = 2,
  323. .left_margin = 40, .upper_margin = 32,
  324. .right_margin = 24, .lower_margin = 11,
  325. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  326. .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
  327. .lccr3 = LCCR3_OutEnL | LCCR3_PixFlEdg | LCCR3_ACBsDiv(512),
  328. };
  329. #endif
  330. #ifdef LART_KIT01_LCD
  331. static struct sa1100fb_mach_info lart_kit01_info __initdata = {
  332. .pixclock = 63291, .bpp = 16,
  333. .xres = 640, .yres = 480,
  334. .hsync_len = 64, .vsync_len = 3,
  335. .left_margin = 122, .upper_margin = 45,
  336. .right_margin = 10, .lower_margin = 10,
  337. .lccr0 = LCCR0_Color | LCCR0_Sngl | LCCR0_Act,
  338. .lccr3 = LCCR3_OutEnH | LCCR3_PixFlEdg
  339. };
  340. #endif
  341. #ifdef CONFIG_SA1100_SHANNON
  342. static struct sa1100fb_mach_info shannon_info __initdata = {
  343. .pixclock = 152500, .bpp = 8,
  344. .xres = 640, .yres = 480,
  345. .hsync_len = 4, .vsync_len = 3,
  346. .left_margin = 2, .upper_margin = 0,
  347. .right_margin = 1, .lower_margin = 0,
  348. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  349. .lccr0 = LCCR0_Color | LCCR0_Dual | LCCR0_Pas,
  350. .lccr3 = LCCR3_ACBsDiv(512),
  351. };
  352. #endif
  353. static struct sa1100fb_mach_info * __init
  354. sa1100fb_get_machine_info(struct sa1100fb_info *fbi)
  355. {
  356. struct sa1100fb_mach_info *inf = NULL;
  357. /*
  358. * R G B T
  359. * default {11,5}, { 5,6}, { 0,5}, { 0,0}
  360. * h3600 {12,4}, { 7,4}, { 1,4}, { 0,0}
  361. * freebird { 8,4}, { 4,4}, { 0,4}, {12,4}
  362. */
  363. #ifdef CONFIG_SA1100_ASSABET
  364. if (machine_is_assabet()) {
  365. #ifndef ASSABET_PAL_VIDEO
  366. inf = &lq039q2ds54_info;
  367. #else
  368. inf = &pal_info;
  369. #endif
  370. }
  371. #endif
  372. #ifdef CONFIG_SA1100_H3100
  373. if (machine_is_h3100()) {
  374. inf = &h3100_info;
  375. }
  376. #endif
  377. #ifdef CONFIG_SA1100_H3600
  378. if (machine_is_h3600()) {
  379. inf = &h3600_info;
  380. fbi->rgb[RGB_16] = &h3600_rgb_16;
  381. }
  382. #endif
  383. #ifdef CONFIG_SA1100_H3800
  384. if (machine_is_h3800()) {
  385. inf = &h3800_info;
  386. }
  387. #endif
  388. #ifdef CONFIG_SA1100_COLLIE
  389. if (machine_is_collie()) {
  390. inf = &collie_info;
  391. }
  392. #endif
  393. #ifdef CONFIG_SA1100_LART
  394. if (machine_is_lart()) {
  395. #ifdef LART_GREY_LCD
  396. inf = &lart_grey_info;
  397. #endif
  398. #ifdef LART_COLOR_LCD
  399. inf = &lart_color_info;
  400. #endif
  401. #ifdef LART_VIDEO_OUT
  402. inf = &lart_video_info;
  403. #endif
  404. #ifdef LART_KIT01_LCD
  405. inf = &lart_kit01_info;
  406. #endif
  407. }
  408. #endif
  409. #ifdef CONFIG_SA1100_SHANNON
  410. if (machine_is_shannon()) {
  411. inf = &shannon_info;
  412. }
  413. #endif
  414. return inf;
  415. }
  416. static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *);
  417. static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state);
  418. static inline void sa1100fb_schedule_work(struct sa1100fb_info *fbi, u_int state)
  419. {
  420. unsigned long flags;
  421. local_irq_save(flags);
  422. /*
  423. * We need to handle two requests being made at the same time.
  424. * There are two important cases:
  425. * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
  426. * We must perform the unblanking, which will do our REENABLE for us.
  427. * 2. When we are blanking, but immediately unblank before we have
  428. * blanked. We do the "REENABLE" thing here as well, just to be sure.
  429. */
  430. if (fbi->task_state == C_ENABLE && state == C_REENABLE)
  431. state = (u_int) -1;
  432. if (fbi->task_state == C_DISABLE && state == C_ENABLE)
  433. state = C_REENABLE;
  434. if (state != (u_int)-1) {
  435. fbi->task_state = state;
  436. schedule_work(&fbi->task);
  437. }
  438. local_irq_restore(flags);
  439. }
  440. static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
  441. {
  442. chan &= 0xffff;
  443. chan >>= 16 - bf->length;
  444. return chan << bf->offset;
  445. }
  446. /*
  447. * Convert bits-per-pixel to a hardware palette PBS value.
  448. */
  449. static inline u_int palette_pbs(struct fb_var_screeninfo *var)
  450. {
  451. int ret = 0;
  452. switch (var->bits_per_pixel) {
  453. case 4: ret = 0 << 12; break;
  454. case 8: ret = 1 << 12; break;
  455. case 16: ret = 2 << 12; break;
  456. }
  457. return ret;
  458. }
  459. static int
  460. sa1100fb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
  461. u_int trans, struct fb_info *info)
  462. {
  463. struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
  464. u_int val, ret = 1;
  465. if (regno < fbi->palette_size) {
  466. val = ((red >> 4) & 0xf00);
  467. val |= ((green >> 8) & 0x0f0);
  468. val |= ((blue >> 12) & 0x00f);
  469. if (regno == 0)
  470. val |= palette_pbs(&fbi->fb.var);
  471. fbi->palette_cpu[regno] = val;
  472. ret = 0;
  473. }
  474. return ret;
  475. }
  476. static int
  477. sa1100fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  478. u_int trans, struct fb_info *info)
  479. {
  480. struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
  481. unsigned int val;
  482. int ret = 1;
  483. /*
  484. * If inverse mode was selected, invert all the colours
  485. * rather than the register number. The register number
  486. * is what you poke into the framebuffer to produce the
  487. * colour you requested.
  488. */
  489. if (fbi->cmap_inverse) {
  490. red = 0xffff - red;
  491. green = 0xffff - green;
  492. blue = 0xffff - blue;
  493. }
  494. /*
  495. * If greyscale is true, then we convert the RGB value
  496. * to greyscale no mater what visual we are using.
  497. */
  498. if (fbi->fb.var.grayscale)
  499. red = green = blue = (19595 * red + 38470 * green +
  500. 7471 * blue) >> 16;
  501. switch (fbi->fb.fix.visual) {
  502. case FB_VISUAL_TRUECOLOR:
  503. /*
  504. * 12 or 16-bit True Colour. We encode the RGB value
  505. * according to the RGB bitfield information.
  506. */
  507. if (regno < 16) {
  508. u32 *pal = fbi->fb.pseudo_palette;
  509. val = chan_to_field(red, &fbi->fb.var.red);
  510. val |= chan_to_field(green, &fbi->fb.var.green);
  511. val |= chan_to_field(blue, &fbi->fb.var.blue);
  512. pal[regno] = val;
  513. ret = 0;
  514. }
  515. break;
  516. case FB_VISUAL_STATIC_PSEUDOCOLOR:
  517. case FB_VISUAL_PSEUDOCOLOR:
  518. ret = sa1100fb_setpalettereg(regno, red, green, blue, trans, info);
  519. break;
  520. }
  521. return ret;
  522. }
  523. #ifdef CONFIG_CPU_FREQ
  524. /*
  525. * sa1100fb_display_dma_period()
  526. * Calculate the minimum period (in picoseconds) between two DMA
  527. * requests for the LCD controller. If we hit this, it means we're
  528. * doing nothing but LCD DMA.
  529. */
  530. static inline unsigned int sa1100fb_display_dma_period(struct fb_var_screeninfo *var)
  531. {
  532. /*
  533. * Period = pixclock * bits_per_byte * bytes_per_transfer
  534. * / memory_bits_per_pixel;
  535. */
  536. return var->pixclock * 8 * 16 / var->bits_per_pixel;
  537. }
  538. #endif
  539. /*
  540. * sa1100fb_check_var():
  541. * Round up in the following order: bits_per_pixel, xres,
  542. * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
  543. * bitfields, horizontal timing, vertical timing.
  544. */
  545. static int
  546. sa1100fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  547. {
  548. struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
  549. int rgbidx;
  550. if (var->xres < MIN_XRES)
  551. var->xres = MIN_XRES;
  552. if (var->yres < MIN_YRES)
  553. var->yres = MIN_YRES;
  554. if (var->xres > fbi->max_xres)
  555. var->xres = fbi->max_xres;
  556. if (var->yres > fbi->max_yres)
  557. var->yres = fbi->max_yres;
  558. var->xres_virtual = max(var->xres_virtual, var->xres);
  559. var->yres_virtual = max(var->yres_virtual, var->yres);
  560. DPRINTK("var->bits_per_pixel=%d\n", var->bits_per_pixel);
  561. switch (var->bits_per_pixel) {
  562. case 4:
  563. rgbidx = RGB_8;
  564. break;
  565. case 8:
  566. rgbidx = RGB_8;
  567. break;
  568. case 16:
  569. rgbidx = RGB_16;
  570. break;
  571. default:
  572. return -EINVAL;
  573. }
  574. /*
  575. * Copy the RGB parameters for this display
  576. * from the machine specific parameters.
  577. */
  578. var->red = fbi->rgb[rgbidx]->red;
  579. var->green = fbi->rgb[rgbidx]->green;
  580. var->blue = fbi->rgb[rgbidx]->blue;
  581. var->transp = fbi->rgb[rgbidx]->transp;
  582. DPRINTK("RGBT length = %d:%d:%d:%d\n",
  583. var->red.length, var->green.length, var->blue.length,
  584. var->transp.length);
  585. DPRINTK("RGBT offset = %d:%d:%d:%d\n",
  586. var->red.offset, var->green.offset, var->blue.offset,
  587. var->transp.offset);
  588. #ifdef CONFIG_CPU_FREQ
  589. printk(KERN_DEBUG "dma period = %d ps, clock = %d kHz\n",
  590. sa1100fb_display_dma_period(var),
  591. cpufreq_get(smp_processor_id()));
  592. #endif
  593. return 0;
  594. }
  595. static inline void sa1100fb_set_truecolor(u_int is_true_color)
  596. {
  597. if (machine_is_assabet()) {
  598. #if 1 // phase 4 or newer Assabet's
  599. if (is_true_color)
  600. ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
  601. else
  602. ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
  603. #else
  604. // older Assabet's
  605. if (is_true_color)
  606. ASSABET_BCR_clear(ASSABET_BCR_LCD_12RGB);
  607. else
  608. ASSABET_BCR_set(ASSABET_BCR_LCD_12RGB);
  609. #endif
  610. }
  611. }
  612. /*
  613. * sa1100fb_set_par():
  614. * Set the user defined part of the display for the specified console
  615. */
  616. static int sa1100fb_set_par(struct fb_info *info)
  617. {
  618. struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
  619. struct fb_var_screeninfo *var = &info->var;
  620. unsigned long palette_mem_size;
  621. DPRINTK("set_par\n");
  622. if (var->bits_per_pixel == 16)
  623. fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
  624. else if (!fbi->cmap_static)
  625. fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
  626. else {
  627. /*
  628. * Some people have weird ideas about wanting static
  629. * pseudocolor maps. I suspect their user space
  630. * applications are broken.
  631. */
  632. fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
  633. }
  634. fbi->fb.fix.line_length = var->xres_virtual *
  635. var->bits_per_pixel / 8;
  636. fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16;
  637. palette_mem_size = fbi->palette_size * sizeof(u16);
  638. DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
  639. fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
  640. fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
  641. /*
  642. * Set (any) board control register to handle new color depth
  643. */
  644. sa1100fb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
  645. sa1100fb_activate_var(var, fbi);
  646. return 0;
  647. }
  648. #if 0
  649. static int
  650. sa1100fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
  651. struct fb_info *info)
  652. {
  653. struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
  654. /*
  655. * Make sure the user isn't doing something stupid.
  656. */
  657. if (!kspc && (fbi->fb.var.bits_per_pixel == 16 || fbi->cmap_static))
  658. return -EINVAL;
  659. return gen_set_cmap(cmap, kspc, con, info);
  660. }
  661. #endif
  662. /*
  663. * Formal definition of the VESA spec:
  664. * On
  665. * This refers to the state of the display when it is in full operation
  666. * Stand-By
  667. * This defines an optional operating state of minimal power reduction with
  668. * the shortest recovery time
  669. * Suspend
  670. * This refers to a level of power management in which substantial power
  671. * reduction is achieved by the display. The display can have a longer
  672. * recovery time from this state than from the Stand-by state
  673. * Off
  674. * This indicates that the display is consuming the lowest level of power
  675. * and is non-operational. Recovery from this state may optionally require
  676. * the user to manually power on the monitor
  677. *
  678. * Now, the fbdev driver adds an additional state, (blank), where they
  679. * turn off the video (maybe by colormap tricks), but don't mess with the
  680. * video itself: think of it semantically between on and Stand-By.
  681. *
  682. * So here's what we should do in our fbdev blank routine:
  683. *
  684. * VESA_NO_BLANKING (mode 0) Video on, front/back light on
  685. * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
  686. * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
  687. * VESA_POWERDOWN (mode 3) Video off, front/back light off
  688. *
  689. * This will match the matrox implementation.
  690. */
  691. /*
  692. * sa1100fb_blank():
  693. * Blank the display by setting all palette values to zero. Note, the
  694. * 12 and 16 bpp modes don't really use the palette, so this will not
  695. * blank the display in all modes.
  696. */
  697. static int sa1100fb_blank(int blank, struct fb_info *info)
  698. {
  699. struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
  700. int i;
  701. DPRINTK("sa1100fb_blank: blank=%d\n", blank);
  702. switch (blank) {
  703. case FB_BLANK_POWERDOWN:
  704. case FB_BLANK_VSYNC_SUSPEND:
  705. case FB_BLANK_HSYNC_SUSPEND:
  706. case FB_BLANK_NORMAL:
  707. if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
  708. fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
  709. for (i = 0; i < fbi->palette_size; i++)
  710. sa1100fb_setpalettereg(i, 0, 0, 0, 0, info);
  711. sa1100fb_schedule_work(fbi, C_DISABLE);
  712. break;
  713. case FB_BLANK_UNBLANK:
  714. if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
  715. fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
  716. fb_set_cmap(&fbi->fb.cmap, info);
  717. sa1100fb_schedule_work(fbi, C_ENABLE);
  718. }
  719. return 0;
  720. }
  721. static int sa1100fb_mmap(struct fb_info *info,
  722. struct vm_area_struct *vma)
  723. {
  724. struct sa1100fb_info *fbi = (struct sa1100fb_info *)info;
  725. unsigned long start, len, off = vma->vm_pgoff << PAGE_SHIFT;
  726. if (off < info->fix.smem_len) {
  727. vma->vm_pgoff += 1; /* skip over the palette */
  728. return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
  729. fbi->map_dma, fbi->map_size);
  730. }
  731. start = info->fix.mmio_start;
  732. len = PAGE_ALIGN((start & ~PAGE_MASK) + info->fix.mmio_len);
  733. if ((vma->vm_end - vma->vm_start + off) > len)
  734. return -EINVAL;
  735. off += start & PAGE_MASK;
  736. vma->vm_pgoff = off >> PAGE_SHIFT;
  737. vma->vm_flags |= VM_IO;
  738. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  739. return io_remap_pfn_range(vma, vma->vm_start, off >> PAGE_SHIFT,
  740. vma->vm_end - vma->vm_start,
  741. vma->vm_page_prot);
  742. }
  743. static struct fb_ops sa1100fb_ops = {
  744. .owner = THIS_MODULE,
  745. .fb_check_var = sa1100fb_check_var,
  746. .fb_set_par = sa1100fb_set_par,
  747. // .fb_set_cmap = sa1100fb_set_cmap,
  748. .fb_setcolreg = sa1100fb_setcolreg,
  749. .fb_fillrect = cfb_fillrect,
  750. .fb_copyarea = cfb_copyarea,
  751. .fb_imageblit = cfb_imageblit,
  752. .fb_blank = sa1100fb_blank,
  753. .fb_mmap = sa1100fb_mmap,
  754. };
  755. /*
  756. * Calculate the PCD value from the clock rate (in picoseconds).
  757. * We take account of the PPCR clock setting.
  758. */
  759. static inline unsigned int get_pcd(unsigned int pixclock, unsigned int cpuclock)
  760. {
  761. unsigned int pcd = cpuclock / 100;
  762. pcd *= pixclock;
  763. pcd /= 10000000;
  764. return pcd + 1; /* make up for integer math truncations */
  765. }
  766. /*
  767. * sa1100fb_activate_var():
  768. * Configures LCD Controller based on entries in var parameter. Settings are
  769. * only written to the controller if changes were made.
  770. */
  771. static int sa1100fb_activate_var(struct fb_var_screeninfo *var, struct sa1100fb_info *fbi)
  772. {
  773. struct sa1100fb_lcd_reg new_regs;
  774. u_int half_screen_size, yres, pcd;
  775. u_long flags;
  776. DPRINTK("Configuring SA1100 LCD\n");
  777. DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
  778. var->xres, var->hsync_len,
  779. var->left_margin, var->right_margin);
  780. DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
  781. var->yres, var->vsync_len,
  782. var->upper_margin, var->lower_margin);
  783. #if DEBUG_VAR
  784. if (var->xres < 16 || var->xres > 1024)
  785. printk(KERN_ERR "%s: invalid xres %d\n",
  786. fbi->fb.fix.id, var->xres);
  787. if (var->hsync_len < 1 || var->hsync_len > 64)
  788. printk(KERN_ERR "%s: invalid hsync_len %d\n",
  789. fbi->fb.fix.id, var->hsync_len);
  790. if (var->left_margin < 1 || var->left_margin > 255)
  791. printk(KERN_ERR "%s: invalid left_margin %d\n",
  792. fbi->fb.fix.id, var->left_margin);
  793. if (var->right_margin < 1 || var->right_margin > 255)
  794. printk(KERN_ERR "%s: invalid right_margin %d\n",
  795. fbi->fb.fix.id, var->right_margin);
  796. if (var->yres < 1 || var->yres > 1024)
  797. printk(KERN_ERR "%s: invalid yres %d\n",
  798. fbi->fb.fix.id, var->yres);
  799. if (var->vsync_len < 1 || var->vsync_len > 64)
  800. printk(KERN_ERR "%s: invalid vsync_len %d\n",
  801. fbi->fb.fix.id, var->vsync_len);
  802. if (var->upper_margin < 0 || var->upper_margin > 255)
  803. printk(KERN_ERR "%s: invalid upper_margin %d\n",
  804. fbi->fb.fix.id, var->upper_margin);
  805. if (var->lower_margin < 0 || var->lower_margin > 255)
  806. printk(KERN_ERR "%s: invalid lower_margin %d\n",
  807. fbi->fb.fix.id, var->lower_margin);
  808. #endif
  809. new_regs.lccr0 = fbi->lccr0 |
  810. LCCR0_LEN | LCCR0_LDM | LCCR0_BAM |
  811. LCCR0_ERM | LCCR0_LtlEnd | LCCR0_DMADel(0);
  812. new_regs.lccr1 =
  813. LCCR1_DisWdth(var->xres) +
  814. LCCR1_HorSnchWdth(var->hsync_len) +
  815. LCCR1_BegLnDel(var->left_margin) +
  816. LCCR1_EndLnDel(var->right_margin);
  817. /*
  818. * If we have a dual scan LCD, then we need to halve
  819. * the YRES parameter.
  820. */
  821. yres = var->yres;
  822. if (fbi->lccr0 & LCCR0_Dual)
  823. yres /= 2;
  824. new_regs.lccr2 =
  825. LCCR2_DisHght(yres) +
  826. LCCR2_VrtSnchWdth(var->vsync_len) +
  827. LCCR2_BegFrmDel(var->upper_margin) +
  828. LCCR2_EndFrmDel(var->lower_margin);
  829. pcd = get_pcd(var->pixclock, cpufreq_get(0));
  830. new_regs.lccr3 = LCCR3_PixClkDiv(pcd) | fbi->lccr3 |
  831. (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
  832. (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
  833. DPRINTK("nlccr0 = 0x%08lx\n", new_regs.lccr0);
  834. DPRINTK("nlccr1 = 0x%08lx\n", new_regs.lccr1);
  835. DPRINTK("nlccr2 = 0x%08lx\n", new_regs.lccr2);
  836. DPRINTK("nlccr3 = 0x%08lx\n", new_regs.lccr3);
  837. half_screen_size = var->bits_per_pixel;
  838. half_screen_size = half_screen_size * var->xres * var->yres / 16;
  839. /* Update shadow copy atomically */
  840. local_irq_save(flags);
  841. fbi->dbar1 = fbi->palette_dma;
  842. fbi->dbar2 = fbi->screen_dma + half_screen_size;
  843. fbi->reg_lccr0 = new_regs.lccr0;
  844. fbi->reg_lccr1 = new_regs.lccr1;
  845. fbi->reg_lccr2 = new_regs.lccr2;
  846. fbi->reg_lccr3 = new_regs.lccr3;
  847. local_irq_restore(flags);
  848. /*
  849. * Only update the registers if the controller is enabled
  850. * and something has changed.
  851. */
  852. if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
  853. (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
  854. (DBAR1 != fbi->dbar1) || (DBAR2 != fbi->dbar2))
  855. sa1100fb_schedule_work(fbi, C_REENABLE);
  856. return 0;
  857. }
  858. /*
  859. * NOTE! The following functions are purely helpers for set_ctrlr_state.
  860. * Do not call them directly; set_ctrlr_state does the correct serialisation
  861. * to ensure that things happen in the right way 100% of time time.
  862. * -- rmk
  863. */
  864. static inline void __sa1100fb_backlight_power(struct sa1100fb_info *fbi, int on)
  865. {
  866. DPRINTK("backlight o%s\n", on ? "n" : "ff");
  867. if (sa1100fb_backlight_power)
  868. sa1100fb_backlight_power(on);
  869. }
  870. static inline void __sa1100fb_lcd_power(struct sa1100fb_info *fbi, int on)
  871. {
  872. DPRINTK("LCD power o%s\n", on ? "n" : "ff");
  873. if (sa1100fb_lcd_power)
  874. sa1100fb_lcd_power(on);
  875. }
  876. static void sa1100fb_setup_gpio(struct sa1100fb_info *fbi)
  877. {
  878. u_int mask = 0;
  879. /*
  880. * Enable GPIO<9:2> for LCD use if:
  881. * 1. Active display, or
  882. * 2. Color Dual Passive display
  883. *
  884. * see table 11.8 on page 11-27 in the SA1100 manual
  885. * -- Erik.
  886. *
  887. * SA1110 spec update nr. 25 says we can and should
  888. * clear LDD15 to 12 for 4 or 8bpp modes with active
  889. * panels.
  890. */
  891. if ((fbi->reg_lccr0 & LCCR0_CMS) == LCCR0_Color &&
  892. (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) != 0) {
  893. mask = GPIO_LDD11 | GPIO_LDD10 | GPIO_LDD9 | GPIO_LDD8;
  894. if (fbi->fb.var.bits_per_pixel > 8 ||
  895. (fbi->reg_lccr0 & (LCCR0_Dual|LCCR0_Act)) == LCCR0_Dual)
  896. mask |= GPIO_LDD15 | GPIO_LDD14 | GPIO_LDD13 | GPIO_LDD12;
  897. }
  898. if (mask) {
  899. GPDR |= mask;
  900. GAFR |= mask;
  901. }
  902. }
  903. static void sa1100fb_enable_controller(struct sa1100fb_info *fbi)
  904. {
  905. DPRINTK("Enabling LCD controller\n");
  906. /*
  907. * Make sure the mode bits are present in the first palette entry
  908. */
  909. fbi->palette_cpu[0] &= 0xcfff;
  910. fbi->palette_cpu[0] |= palette_pbs(&fbi->fb.var);
  911. /* Sequence from 11.7.10 */
  912. LCCR3 = fbi->reg_lccr3;
  913. LCCR2 = fbi->reg_lccr2;
  914. LCCR1 = fbi->reg_lccr1;
  915. LCCR0 = fbi->reg_lccr0 & ~LCCR0_LEN;
  916. DBAR1 = fbi->dbar1;
  917. DBAR2 = fbi->dbar2;
  918. LCCR0 |= LCCR0_LEN;
  919. if (machine_is_shannon()) {
  920. GPDR |= SHANNON_GPIO_DISP_EN;
  921. GPSR |= SHANNON_GPIO_DISP_EN;
  922. }
  923. DPRINTK("DBAR1 = 0x%08x\n", DBAR1);
  924. DPRINTK("DBAR2 = 0x%08x\n", DBAR2);
  925. DPRINTK("LCCR0 = 0x%08x\n", LCCR0);
  926. DPRINTK("LCCR1 = 0x%08x\n", LCCR1);
  927. DPRINTK("LCCR2 = 0x%08x\n", LCCR2);
  928. DPRINTK("LCCR3 = 0x%08x\n", LCCR3);
  929. }
  930. static void sa1100fb_disable_controller(struct sa1100fb_info *fbi)
  931. {
  932. DECLARE_WAITQUEUE(wait, current);
  933. DPRINTK("Disabling LCD controller\n");
  934. if (machine_is_shannon()) {
  935. GPCR |= SHANNON_GPIO_DISP_EN;
  936. }
  937. set_current_state(TASK_UNINTERRUPTIBLE);
  938. add_wait_queue(&fbi->ctrlr_wait, &wait);
  939. LCSR = 0xffffffff; /* Clear LCD Status Register */
  940. LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
  941. LCCR0 &= ~LCCR0_LEN; /* Disable LCD Controller */
  942. schedule_timeout(20 * HZ / 1000);
  943. remove_wait_queue(&fbi->ctrlr_wait, &wait);
  944. }
  945. /*
  946. * sa1100fb_handle_irq: Handle 'LCD DONE' interrupts.
  947. */
  948. static irqreturn_t sa1100fb_handle_irq(int irq, void *dev_id)
  949. {
  950. struct sa1100fb_info *fbi = dev_id;
  951. unsigned int lcsr = LCSR;
  952. if (lcsr & LCSR_LDD) {
  953. LCCR0 |= LCCR0_LDM;
  954. wake_up(&fbi->ctrlr_wait);
  955. }
  956. LCSR = lcsr;
  957. return IRQ_HANDLED;
  958. }
  959. /*
  960. * This function must be called from task context only, since it will
  961. * sleep when disabling the LCD controller, or if we get two contending
  962. * processes trying to alter state.
  963. */
  964. static void set_ctrlr_state(struct sa1100fb_info *fbi, u_int state)
  965. {
  966. u_int old_state;
  967. down(&fbi->ctrlr_sem);
  968. old_state = fbi->state;
  969. /*
  970. * Hack around fbcon initialisation.
  971. */
  972. if (old_state == C_STARTUP && state == C_REENABLE)
  973. state = C_ENABLE;
  974. switch (state) {
  975. case C_DISABLE_CLKCHANGE:
  976. /*
  977. * Disable controller for clock change. If the
  978. * controller is already disabled, then do nothing.
  979. */
  980. if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
  981. fbi->state = state;
  982. sa1100fb_disable_controller(fbi);
  983. }
  984. break;
  985. case C_DISABLE_PM:
  986. case C_DISABLE:
  987. /*
  988. * Disable controller
  989. */
  990. if (old_state != C_DISABLE) {
  991. fbi->state = state;
  992. __sa1100fb_backlight_power(fbi, 0);
  993. if (old_state != C_DISABLE_CLKCHANGE)
  994. sa1100fb_disable_controller(fbi);
  995. __sa1100fb_lcd_power(fbi, 0);
  996. }
  997. break;
  998. case C_ENABLE_CLKCHANGE:
  999. /*
  1000. * Enable the controller after clock change. Only
  1001. * do this if we were disabled for the clock change.
  1002. */
  1003. if (old_state == C_DISABLE_CLKCHANGE) {
  1004. fbi->state = C_ENABLE;
  1005. sa1100fb_enable_controller(fbi);
  1006. }
  1007. break;
  1008. case C_REENABLE:
  1009. /*
  1010. * Re-enable the controller only if it was already
  1011. * enabled. This is so we reprogram the control
  1012. * registers.
  1013. */
  1014. if (old_state == C_ENABLE) {
  1015. sa1100fb_disable_controller(fbi);
  1016. sa1100fb_setup_gpio(fbi);
  1017. sa1100fb_enable_controller(fbi);
  1018. }
  1019. break;
  1020. case C_ENABLE_PM:
  1021. /*
  1022. * Re-enable the controller after PM. This is not
  1023. * perfect - think about the case where we were doing
  1024. * a clock change, and we suspended half-way through.
  1025. */
  1026. if (old_state != C_DISABLE_PM)
  1027. break;
  1028. /* fall through */
  1029. case C_ENABLE:
  1030. /*
  1031. * Power up the LCD screen, enable controller, and
  1032. * turn on the backlight.
  1033. */
  1034. if (old_state != C_ENABLE) {
  1035. fbi->state = C_ENABLE;
  1036. sa1100fb_setup_gpio(fbi);
  1037. __sa1100fb_lcd_power(fbi, 1);
  1038. sa1100fb_enable_controller(fbi);
  1039. __sa1100fb_backlight_power(fbi, 1);
  1040. }
  1041. break;
  1042. }
  1043. up(&fbi->ctrlr_sem);
  1044. }
  1045. /*
  1046. * Our LCD controller task (which is called when we blank or unblank)
  1047. * via keventd.
  1048. */
  1049. static void sa1100fb_task(struct work_struct *w)
  1050. {
  1051. struct sa1100fb_info *fbi = container_of(w, struct sa1100fb_info, task);
  1052. u_int state = xchg(&fbi->task_state, -1);
  1053. set_ctrlr_state(fbi, state);
  1054. }
  1055. #ifdef CONFIG_CPU_FREQ
  1056. /*
  1057. * Calculate the minimum DMA period over all displays that we own.
  1058. * This, together with the SDRAM bandwidth defines the slowest CPU
  1059. * frequency that can be selected.
  1060. */
  1061. static unsigned int sa1100fb_min_dma_period(struct sa1100fb_info *fbi)
  1062. {
  1063. #if 0
  1064. unsigned int min_period = (unsigned int)-1;
  1065. int i;
  1066. for (i = 0; i < MAX_NR_CONSOLES; i++) {
  1067. struct display *disp = &fb_display[i];
  1068. unsigned int period;
  1069. /*
  1070. * Do we own this display?
  1071. */
  1072. if (disp->fb_info != &fbi->fb)
  1073. continue;
  1074. /*
  1075. * Ok, calculate its DMA period
  1076. */
  1077. period = sa1100fb_display_dma_period(&disp->var);
  1078. if (period < min_period)
  1079. min_period = period;
  1080. }
  1081. return min_period;
  1082. #else
  1083. /*
  1084. * FIXME: we need to verify _all_ consoles.
  1085. */
  1086. return sa1100fb_display_dma_period(&fbi->fb.var);
  1087. #endif
  1088. }
  1089. /*
  1090. * CPU clock speed change handler. We need to adjust the LCD timing
  1091. * parameters when the CPU clock is adjusted by the power management
  1092. * subsystem.
  1093. */
  1094. static int
  1095. sa1100fb_freq_transition(struct notifier_block *nb, unsigned long val,
  1096. void *data)
  1097. {
  1098. struct sa1100fb_info *fbi = TO_INF(nb, freq_transition);
  1099. struct cpufreq_freqs *f = data;
  1100. u_int pcd;
  1101. switch (val) {
  1102. case CPUFREQ_PRECHANGE:
  1103. set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
  1104. break;
  1105. case CPUFREQ_POSTCHANGE:
  1106. pcd = get_pcd(fbi->fb.var.pixclock, f->new);
  1107. fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
  1108. set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
  1109. break;
  1110. }
  1111. return 0;
  1112. }
  1113. static int
  1114. sa1100fb_freq_policy(struct notifier_block *nb, unsigned long val,
  1115. void *data)
  1116. {
  1117. struct sa1100fb_info *fbi = TO_INF(nb, freq_policy);
  1118. struct cpufreq_policy *policy = data;
  1119. switch (val) {
  1120. case CPUFREQ_ADJUST:
  1121. case CPUFREQ_INCOMPATIBLE:
  1122. printk(KERN_DEBUG "min dma period: %d ps, "
  1123. "new clock %d kHz\n", sa1100fb_min_dma_period(fbi),
  1124. policy->max);
  1125. /* todo: fill in min/max values */
  1126. break;
  1127. case CPUFREQ_NOTIFY:
  1128. do {} while(0);
  1129. /* todo: panic if min/max values aren't fulfilled
  1130. * [can't really happen unless there's a bug in the
  1131. * CPU policy verififcation process *
  1132. */
  1133. break;
  1134. }
  1135. return 0;
  1136. }
  1137. #endif
  1138. #ifdef CONFIG_PM
  1139. /*
  1140. * Power management hooks. Note that we won't be called from IRQ context,
  1141. * unlike the blank functions above, so we may sleep.
  1142. */
  1143. static int sa1100fb_suspend(struct platform_device *dev, pm_message_t state)
  1144. {
  1145. struct sa1100fb_info *fbi = platform_get_drvdata(dev);
  1146. set_ctrlr_state(fbi, C_DISABLE_PM);
  1147. return 0;
  1148. }
  1149. static int sa1100fb_resume(struct platform_device *dev)
  1150. {
  1151. struct sa1100fb_info *fbi = platform_get_drvdata(dev);
  1152. set_ctrlr_state(fbi, C_ENABLE_PM);
  1153. return 0;
  1154. }
  1155. #else
  1156. #define sa1100fb_suspend NULL
  1157. #define sa1100fb_resume NULL
  1158. #endif
  1159. /*
  1160. * sa1100fb_map_video_memory():
  1161. * Allocates the DRAM memory for the frame buffer. This buffer is
  1162. * remapped into a non-cached, non-buffered, memory region to
  1163. * allow palette and pixel writes to occur without flushing the
  1164. * cache. Once this area is remapped, all virtual memory
  1165. * access to the video memory should occur at the new region.
  1166. */
  1167. static int __init sa1100fb_map_video_memory(struct sa1100fb_info *fbi)
  1168. {
  1169. /*
  1170. * We reserve one page for the palette, plus the size
  1171. * of the framebuffer.
  1172. */
  1173. fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
  1174. fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
  1175. &fbi->map_dma, GFP_KERNEL);
  1176. if (fbi->map_cpu) {
  1177. fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
  1178. fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
  1179. /*
  1180. * FIXME: this is actually the wrong thing to place in
  1181. * smem_start. But fbdev suffers from the problem that
  1182. * it needs an API which doesn't exist (in this case,
  1183. * dma_writecombine_mmap)
  1184. */
  1185. fbi->fb.fix.smem_start = fbi->screen_dma;
  1186. }
  1187. return fbi->map_cpu ? 0 : -ENOMEM;
  1188. }
  1189. /* Fake monspecs to fill in fbinfo structure */
  1190. static struct fb_monspecs monspecs __initdata = {
  1191. .hfmin = 30000,
  1192. .hfmax = 70000,
  1193. .vfmin = 50,
  1194. .vfmax = 65,
  1195. };
  1196. static struct sa1100fb_info * __init sa1100fb_init_fbinfo(struct device *dev)
  1197. {
  1198. struct sa1100fb_mach_info *inf;
  1199. struct sa1100fb_info *fbi;
  1200. fbi = kmalloc(sizeof(struct sa1100fb_info) + sizeof(u32) * 16,
  1201. GFP_KERNEL);
  1202. if (!fbi)
  1203. return NULL;
  1204. memset(fbi, 0, sizeof(struct sa1100fb_info));
  1205. fbi->dev = dev;
  1206. strcpy(fbi->fb.fix.id, SA1100_NAME);
  1207. fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
  1208. fbi->fb.fix.type_aux = 0;
  1209. fbi->fb.fix.xpanstep = 0;
  1210. fbi->fb.fix.ypanstep = 0;
  1211. fbi->fb.fix.ywrapstep = 0;
  1212. fbi->fb.fix.accel = FB_ACCEL_NONE;
  1213. fbi->fb.var.nonstd = 0;
  1214. fbi->fb.var.activate = FB_ACTIVATE_NOW;
  1215. fbi->fb.var.height = -1;
  1216. fbi->fb.var.width = -1;
  1217. fbi->fb.var.accel_flags = 0;
  1218. fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
  1219. fbi->fb.fbops = &sa1100fb_ops;
  1220. fbi->fb.flags = FBINFO_DEFAULT;
  1221. fbi->fb.monspecs = monspecs;
  1222. fbi->fb.pseudo_palette = (fbi + 1);
  1223. fbi->rgb[RGB_8] = &rgb_8;
  1224. fbi->rgb[RGB_16] = &def_rgb_16;
  1225. inf = sa1100fb_get_machine_info(fbi);
  1226. /*
  1227. * People just don't seem to get this. We don't support
  1228. * anything but correct entries now, so panic if someone
  1229. * does something stupid.
  1230. */
  1231. if (inf->lccr3 & (LCCR3_VrtSnchL|LCCR3_HorSnchL|0xff) ||
  1232. inf->pixclock == 0)
  1233. panic("sa1100fb error: invalid LCCR3 fields set or zero "
  1234. "pixclock.");
  1235. fbi->max_xres = inf->xres;
  1236. fbi->fb.var.xres = inf->xres;
  1237. fbi->fb.var.xres_virtual = inf->xres;
  1238. fbi->max_yres = inf->yres;
  1239. fbi->fb.var.yres = inf->yres;
  1240. fbi->fb.var.yres_virtual = inf->yres;
  1241. fbi->max_bpp = inf->bpp;
  1242. fbi->fb.var.bits_per_pixel = inf->bpp;
  1243. fbi->fb.var.pixclock = inf->pixclock;
  1244. fbi->fb.var.hsync_len = inf->hsync_len;
  1245. fbi->fb.var.left_margin = inf->left_margin;
  1246. fbi->fb.var.right_margin = inf->right_margin;
  1247. fbi->fb.var.vsync_len = inf->vsync_len;
  1248. fbi->fb.var.upper_margin = inf->upper_margin;
  1249. fbi->fb.var.lower_margin = inf->lower_margin;
  1250. fbi->fb.var.sync = inf->sync;
  1251. fbi->fb.var.grayscale = inf->cmap_greyscale;
  1252. fbi->cmap_inverse = inf->cmap_inverse;
  1253. fbi->cmap_static = inf->cmap_static;
  1254. fbi->lccr0 = inf->lccr0;
  1255. fbi->lccr3 = inf->lccr3;
  1256. fbi->state = C_STARTUP;
  1257. fbi->task_state = (u_char)-1;
  1258. fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
  1259. fbi->max_bpp / 8;
  1260. init_waitqueue_head(&fbi->ctrlr_wait);
  1261. INIT_WORK(&fbi->task, sa1100fb_task);
  1262. init_MUTEX(&fbi->ctrlr_sem);
  1263. return fbi;
  1264. }
  1265. static int __init sa1100fb_probe(struct platform_device *pdev)
  1266. {
  1267. struct sa1100fb_info *fbi;
  1268. int ret, irq;
  1269. irq = platform_get_irq(pdev, 0);
  1270. if (irq < 0)
  1271. return -EINVAL;
  1272. if (!request_mem_region(0xb0100000, 0x10000, "LCD"))
  1273. return -EBUSY;
  1274. fbi = sa1100fb_init_fbinfo(&pdev->dev);
  1275. ret = -ENOMEM;
  1276. if (!fbi)
  1277. goto failed;
  1278. /* Initialize video memory */
  1279. ret = sa1100fb_map_video_memory(fbi);
  1280. if (ret)
  1281. goto failed;
  1282. ret = request_irq(irq, sa1100fb_handle_irq, IRQF_DISABLED,
  1283. "LCD", fbi);
  1284. if (ret) {
  1285. printk(KERN_ERR "sa1100fb: request_irq failed: %d\n", ret);
  1286. goto failed;
  1287. }
  1288. #ifdef ASSABET_PAL_VIDEO
  1289. if (machine_is_assabet())
  1290. ASSABET_BCR_clear(ASSABET_BCR_LCD_ON);
  1291. #endif
  1292. /*
  1293. * This makes sure that our colour bitfield
  1294. * descriptors are correctly initialised.
  1295. */
  1296. sa1100fb_check_var(&fbi->fb.var, &fbi->fb);
  1297. platform_set_drvdata(pdev, fbi);
  1298. ret = register_framebuffer(&fbi->fb);
  1299. if (ret < 0)
  1300. goto err_free_irq;
  1301. #ifdef CONFIG_CPU_FREQ
  1302. fbi->freq_transition.notifier_call = sa1100fb_freq_transition;
  1303. fbi->freq_policy.notifier_call = sa1100fb_freq_policy;
  1304. cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
  1305. cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
  1306. #endif
  1307. /* This driver cannot be unloaded at the moment */
  1308. return 0;
  1309. err_free_irq:
  1310. free_irq(irq, fbi);
  1311. failed:
  1312. platform_set_drvdata(pdev, NULL);
  1313. kfree(fbi);
  1314. release_mem_region(0xb0100000, 0x10000);
  1315. return ret;
  1316. }
  1317. static struct platform_driver sa1100fb_driver = {
  1318. .probe = sa1100fb_probe,
  1319. .suspend = sa1100fb_suspend,
  1320. .resume = sa1100fb_resume,
  1321. .driver = {
  1322. .name = "sa11x0-fb",
  1323. },
  1324. };
  1325. int __init sa1100fb_init(void)
  1326. {
  1327. if (fb_get_options("sa1100fb", NULL))
  1328. return -ENODEV;
  1329. return platform_driver_register(&sa1100fb_driver);
  1330. }
  1331. int __init sa1100fb_setup(char *options)
  1332. {
  1333. #if 0
  1334. char *this_opt;
  1335. if (!options || !*options)
  1336. return 0;
  1337. while ((this_opt = strsep(&options, ",")) != NULL) {
  1338. if (!strncmp(this_opt, "bpp:", 4))
  1339. current_par.max_bpp =
  1340. simple_strtoul(this_opt + 4, NULL, 0);
  1341. if (!strncmp(this_opt, "lccr0:", 6))
  1342. lcd_shadow.lccr0 =
  1343. simple_strtoul(this_opt + 6, NULL, 0);
  1344. if (!strncmp(this_opt, "lccr1:", 6)) {
  1345. lcd_shadow.lccr1 =
  1346. simple_strtoul(this_opt + 6, NULL, 0);
  1347. current_par.max_xres =
  1348. (lcd_shadow.lccr1 & 0x3ff) + 16;
  1349. }
  1350. if (!strncmp(this_opt, "lccr2:", 6)) {
  1351. lcd_shadow.lccr2 =
  1352. simple_strtoul(this_opt + 6, NULL, 0);
  1353. current_par.max_yres =
  1354. (lcd_shadow.
  1355. lccr0 & LCCR0_SDS) ? ((lcd_shadow.
  1356. lccr2 & 0x3ff) +
  1357. 1) *
  1358. 2 : ((lcd_shadow.lccr2 & 0x3ff) + 1);
  1359. }
  1360. if (!strncmp(this_opt, "lccr3:", 6))
  1361. lcd_shadow.lccr3 =
  1362. simple_strtoul(this_opt + 6, NULL, 0);
  1363. }
  1364. #endif
  1365. return 0;
  1366. }
  1367. module_init(sa1100fb_init);
  1368. MODULE_DESCRIPTION("StrongARM-1100/1110 framebuffer driver");
  1369. MODULE_LICENSE("GPL");