cg6.c 21 KB

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  1. /* cg6.c: CGSIX (GX, GXplus, TGX) frame buffer driver
  2. *
  3. * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
  4. * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
  5. * Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
  6. * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
  7. *
  8. * Driver layout based loosely on tgafb.c, see that file for credits.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/errno.h>
  13. #include <linux/string.h>
  14. #include <linux/slab.h>
  15. #include <linux/delay.h>
  16. #include <linux/init.h>
  17. #include <linux/fb.h>
  18. #include <linux/mm.h>
  19. #include <asm/io.h>
  20. #include <asm/prom.h>
  21. #include <asm/of_device.h>
  22. #include <asm/fbio.h>
  23. #include "sbuslib.h"
  24. /*
  25. * Local functions.
  26. */
  27. static int cg6_setcolreg(unsigned, unsigned, unsigned, unsigned,
  28. unsigned, struct fb_info *);
  29. static int cg6_blank(int, struct fb_info *);
  30. static void cg6_imageblit(struct fb_info *, const struct fb_image *);
  31. static void cg6_fillrect(struct fb_info *, const struct fb_fillrect *);
  32. static int cg6_sync(struct fb_info *);
  33. static int cg6_mmap(struct fb_info *, struct vm_area_struct *);
  34. static int cg6_ioctl(struct fb_info *, unsigned int, unsigned long);
  35. /*
  36. * Frame buffer operations
  37. */
  38. static struct fb_ops cg6_ops = {
  39. .owner = THIS_MODULE,
  40. .fb_setcolreg = cg6_setcolreg,
  41. .fb_blank = cg6_blank,
  42. .fb_fillrect = cg6_fillrect,
  43. .fb_copyarea = cfb_copyarea,
  44. .fb_imageblit = cg6_imageblit,
  45. .fb_sync = cg6_sync,
  46. .fb_mmap = cg6_mmap,
  47. .fb_ioctl = cg6_ioctl,
  48. #ifdef CONFIG_COMPAT
  49. .fb_compat_ioctl = sbusfb_compat_ioctl,
  50. #endif
  51. };
  52. /* Offset of interesting structures in the OBIO space */
  53. /*
  54. * Brooktree is the video dac and is funny to program on the cg6.
  55. * (it's even funnier on the cg3)
  56. * The FBC could be the frame buffer control
  57. * The FHC could is the frame buffer hardware control.
  58. */
  59. #define CG6_ROM_OFFSET 0x0UL
  60. #define CG6_BROOKTREE_OFFSET 0x200000UL
  61. #define CG6_DHC_OFFSET 0x240000UL
  62. #define CG6_ALT_OFFSET 0x280000UL
  63. #define CG6_FHC_OFFSET 0x300000UL
  64. #define CG6_THC_OFFSET 0x301000UL
  65. #define CG6_FBC_OFFSET 0x700000UL
  66. #define CG6_TEC_OFFSET 0x701000UL
  67. #define CG6_RAM_OFFSET 0x800000UL
  68. /* FHC definitions */
  69. #define CG6_FHC_FBID_SHIFT 24
  70. #define CG6_FHC_FBID_MASK 255
  71. #define CG6_FHC_REV_SHIFT 20
  72. #define CG6_FHC_REV_MASK 15
  73. #define CG6_FHC_FROP_DISABLE (1 << 19)
  74. #define CG6_FHC_ROW_DISABLE (1 << 18)
  75. #define CG6_FHC_SRC_DISABLE (1 << 17)
  76. #define CG6_FHC_DST_DISABLE (1 << 16)
  77. #define CG6_FHC_RESET (1 << 15)
  78. #define CG6_FHC_LITTLE_ENDIAN (1 << 13)
  79. #define CG6_FHC_RES_MASK (3 << 11)
  80. #define CG6_FHC_1024 (0 << 11)
  81. #define CG6_FHC_1152 (1 << 11)
  82. #define CG6_FHC_1280 (2 << 11)
  83. #define CG6_FHC_1600 (3 << 11)
  84. #define CG6_FHC_CPU_MASK (3 << 9)
  85. #define CG6_FHC_CPU_SPARC (0 << 9)
  86. #define CG6_FHC_CPU_68020 (1 << 9)
  87. #define CG6_FHC_CPU_386 (2 << 9)
  88. #define CG6_FHC_TEST (1 << 8)
  89. #define CG6_FHC_TEST_X_SHIFT 4
  90. #define CG6_FHC_TEST_X_MASK 15
  91. #define CG6_FHC_TEST_Y_SHIFT 0
  92. #define CG6_FHC_TEST_Y_MASK 15
  93. /* FBC mode definitions */
  94. #define CG6_FBC_BLIT_IGNORE 0x00000000
  95. #define CG6_FBC_BLIT_NOSRC 0x00100000
  96. #define CG6_FBC_BLIT_SRC 0x00200000
  97. #define CG6_FBC_BLIT_ILLEGAL 0x00300000
  98. #define CG6_FBC_BLIT_MASK 0x00300000
  99. #define CG6_FBC_VBLANK 0x00080000
  100. #define CG6_FBC_MODE_IGNORE 0x00000000
  101. #define CG6_FBC_MODE_COLOR8 0x00020000
  102. #define CG6_FBC_MODE_COLOR1 0x00040000
  103. #define CG6_FBC_MODE_HRMONO 0x00060000
  104. #define CG6_FBC_MODE_MASK 0x00060000
  105. #define CG6_FBC_DRAW_IGNORE 0x00000000
  106. #define CG6_FBC_DRAW_RENDER 0x00008000
  107. #define CG6_FBC_DRAW_PICK 0x00010000
  108. #define CG6_FBC_DRAW_ILLEGAL 0x00018000
  109. #define CG6_FBC_DRAW_MASK 0x00018000
  110. #define CG6_FBC_BWRITE0_IGNORE 0x00000000
  111. #define CG6_FBC_BWRITE0_ENABLE 0x00002000
  112. #define CG6_FBC_BWRITE0_DISABLE 0x00004000
  113. #define CG6_FBC_BWRITE0_ILLEGAL 0x00006000
  114. #define CG6_FBC_BWRITE0_MASK 0x00006000
  115. #define CG6_FBC_BWRITE1_IGNORE 0x00000000
  116. #define CG6_FBC_BWRITE1_ENABLE 0x00000800
  117. #define CG6_FBC_BWRITE1_DISABLE 0x00001000
  118. #define CG6_FBC_BWRITE1_ILLEGAL 0x00001800
  119. #define CG6_FBC_BWRITE1_MASK 0x00001800
  120. #define CG6_FBC_BREAD_IGNORE 0x00000000
  121. #define CG6_FBC_BREAD_0 0x00000200
  122. #define CG6_FBC_BREAD_1 0x00000400
  123. #define CG6_FBC_BREAD_ILLEGAL 0x00000600
  124. #define CG6_FBC_BREAD_MASK 0x00000600
  125. #define CG6_FBC_BDISP_IGNORE 0x00000000
  126. #define CG6_FBC_BDISP_0 0x00000080
  127. #define CG6_FBC_BDISP_1 0x00000100
  128. #define CG6_FBC_BDISP_ILLEGAL 0x00000180
  129. #define CG6_FBC_BDISP_MASK 0x00000180
  130. #define CG6_FBC_INDEX_MOD 0x00000040
  131. #define CG6_FBC_INDEX_MASK 0x00000030
  132. /* THC definitions */
  133. #define CG6_THC_MISC_REV_SHIFT 16
  134. #define CG6_THC_MISC_REV_MASK 15
  135. #define CG6_THC_MISC_RESET (1 << 12)
  136. #define CG6_THC_MISC_VIDEO (1 << 10)
  137. #define CG6_THC_MISC_SYNC (1 << 9)
  138. #define CG6_THC_MISC_VSYNC (1 << 8)
  139. #define CG6_THC_MISC_SYNC_ENAB (1 << 7)
  140. #define CG6_THC_MISC_CURS_RES (1 << 6)
  141. #define CG6_THC_MISC_INT_ENAB (1 << 5)
  142. #define CG6_THC_MISC_INT (1 << 4)
  143. #define CG6_THC_MISC_INIT 0x9f
  144. /* The contents are unknown */
  145. struct cg6_tec {
  146. int tec_matrix;
  147. int tec_clip;
  148. int tec_vdc;
  149. };
  150. struct cg6_thc {
  151. u32 thc_pad0[512];
  152. u32 thc_hs; /* hsync timing */
  153. u32 thc_hsdvs;
  154. u32 thc_hd;
  155. u32 thc_vs; /* vsync timing */
  156. u32 thc_vd;
  157. u32 thc_refresh;
  158. u32 thc_misc;
  159. u32 thc_pad1[56];
  160. u32 thc_cursxy; /* cursor x,y position (16 bits each) */
  161. u32 thc_cursmask[32]; /* cursor mask bits */
  162. u32 thc_cursbits[32]; /* what to show where mask enabled */
  163. };
  164. struct cg6_fbc {
  165. u32 xxx0[1];
  166. u32 mode;
  167. u32 clip;
  168. u32 xxx1[1];
  169. u32 s;
  170. u32 draw;
  171. u32 blit;
  172. u32 font;
  173. u32 xxx2[24];
  174. u32 x0, y0, z0, color0;
  175. u32 x1, y1, z1, color1;
  176. u32 x2, y2, z2, color2;
  177. u32 x3, y3, z3, color3;
  178. u32 offx, offy;
  179. u32 xxx3[2];
  180. u32 incx, incy;
  181. u32 xxx4[2];
  182. u32 clipminx, clipminy;
  183. u32 xxx5[2];
  184. u32 clipmaxx, clipmaxy;
  185. u32 xxx6[2];
  186. u32 fg;
  187. u32 bg;
  188. u32 alu;
  189. u32 pm;
  190. u32 pixelm;
  191. u32 xxx7[2];
  192. u32 patalign;
  193. u32 pattern[8];
  194. u32 xxx8[432];
  195. u32 apointx, apointy, apointz;
  196. u32 xxx9[1];
  197. u32 rpointx, rpointy, rpointz;
  198. u32 xxx10[5];
  199. u32 pointr, pointg, pointb, pointa;
  200. u32 alinex, aliney, alinez;
  201. u32 xxx11[1];
  202. u32 rlinex, rliney, rlinez;
  203. u32 xxx12[5];
  204. u32 liner, lineg, lineb, linea;
  205. u32 atrix, atriy, atriz;
  206. u32 xxx13[1];
  207. u32 rtrix, rtriy, rtriz;
  208. u32 xxx14[5];
  209. u32 trir, trig, trib, tria;
  210. u32 aquadx, aquady, aquadz;
  211. u32 xxx15[1];
  212. u32 rquadx, rquady, rquadz;
  213. u32 xxx16[5];
  214. u32 quadr, quadg, quadb, quada;
  215. u32 arectx, arecty, arectz;
  216. u32 xxx17[1];
  217. u32 rrectx, rrecty, rrectz;
  218. u32 xxx18[5];
  219. u32 rectr, rectg, rectb, recta;
  220. };
  221. struct bt_regs {
  222. u32 addr;
  223. u32 color_map;
  224. u32 control;
  225. u32 cursor;
  226. };
  227. struct cg6_par {
  228. spinlock_t lock;
  229. struct bt_regs __iomem *bt;
  230. struct cg6_fbc __iomem *fbc;
  231. struct cg6_thc __iomem *thc;
  232. struct cg6_tec __iomem *tec;
  233. u32 __iomem *fhc;
  234. u32 flags;
  235. #define CG6_FLAG_BLANKED 0x00000001
  236. unsigned long physbase;
  237. unsigned long which_io;
  238. unsigned long fbsize;
  239. };
  240. static int cg6_sync(struct fb_info *info)
  241. {
  242. struct cg6_par *par = (struct cg6_par *) info->par;
  243. struct cg6_fbc __iomem *fbc = par->fbc;
  244. int limit = 10000;
  245. do {
  246. if (!(sbus_readl(&fbc->s) & 0x10000000))
  247. break;
  248. udelay(10);
  249. } while (--limit > 0);
  250. return 0;
  251. }
  252. /**
  253. * cg6_fillrect - REQUIRED function. Can use generic routines if
  254. * non acclerated hardware and packed pixel based.
  255. * Draws a rectangle on the screen.
  256. *
  257. * @info: frame buffer structure that represents a single frame buffer
  258. * @rect: structure defining the rectagle and operation.
  259. */
  260. static void cg6_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  261. {
  262. struct cg6_par *par = (struct cg6_par *) info->par;
  263. struct cg6_fbc __iomem *fbc = par->fbc;
  264. unsigned long flags;
  265. s32 val;
  266. /* XXX doesn't handle ROP_XOR */
  267. spin_lock_irqsave(&par->lock, flags);
  268. cg6_sync(info);
  269. sbus_writel(rect->color, &fbc->fg);
  270. sbus_writel(~(u32)0, &fbc->pixelm);
  271. sbus_writel(0xea80ff00, &fbc->alu);
  272. sbus_writel(0, &fbc->s);
  273. sbus_writel(0, &fbc->clip);
  274. sbus_writel(~(u32)0, &fbc->pm);
  275. sbus_writel(rect->dy, &fbc->arecty);
  276. sbus_writel(rect->dx, &fbc->arectx);
  277. sbus_writel(rect->dy + rect->height, &fbc->arecty);
  278. sbus_writel(rect->dx + rect->width, &fbc->arectx);
  279. do {
  280. val = sbus_readl(&fbc->draw);
  281. } while (val < 0 && (val & 0x20000000));
  282. spin_unlock_irqrestore(&par->lock, flags);
  283. }
  284. /**
  285. * cg6_imageblit - REQUIRED function. Can use generic routines if
  286. * non acclerated hardware and packed pixel based.
  287. * Copies a image from system memory to the screen.
  288. *
  289. * @info: frame buffer structure that represents a single frame buffer
  290. * @image: structure defining the image.
  291. */
  292. static void cg6_imageblit(struct fb_info *info, const struct fb_image *image)
  293. {
  294. struct cg6_par *par = (struct cg6_par *) info->par;
  295. struct cg6_fbc __iomem *fbc = par->fbc;
  296. const u8 *data = image->data;
  297. unsigned long flags;
  298. u32 x, y;
  299. int i, width;
  300. if (image->depth > 1) {
  301. cfb_imageblit(info, image);
  302. return;
  303. }
  304. spin_lock_irqsave(&par->lock, flags);
  305. cg6_sync(info);
  306. sbus_writel(image->fg_color, &fbc->fg);
  307. sbus_writel(image->bg_color, &fbc->bg);
  308. sbus_writel(0x140000, &fbc->mode);
  309. sbus_writel(0xe880fc30, &fbc->alu);
  310. sbus_writel(~(u32)0, &fbc->pixelm);
  311. sbus_writel(0, &fbc->s);
  312. sbus_writel(0, &fbc->clip);
  313. sbus_writel(0xff, &fbc->pm);
  314. sbus_writel(32, &fbc->incx);
  315. sbus_writel(0, &fbc->incy);
  316. x = image->dx;
  317. y = image->dy;
  318. for (i = 0; i < image->height; i++) {
  319. width = image->width;
  320. while (width >= 32) {
  321. u32 val;
  322. sbus_writel(y, &fbc->y0);
  323. sbus_writel(x, &fbc->x0);
  324. sbus_writel(x + 32 - 1, &fbc->x1);
  325. val = ((u32)data[0] << 24) |
  326. ((u32)data[1] << 16) |
  327. ((u32)data[2] << 8) |
  328. ((u32)data[3] << 0);
  329. sbus_writel(val, &fbc->font);
  330. data += 4;
  331. x += 32;
  332. width -= 32;
  333. }
  334. if (width) {
  335. u32 val;
  336. sbus_writel(y, &fbc->y0);
  337. sbus_writel(x, &fbc->x0);
  338. sbus_writel(x + width - 1, &fbc->x1);
  339. if (width <= 8) {
  340. val = (u32) data[0] << 24;
  341. data += 1;
  342. } else if (width <= 16) {
  343. val = ((u32) data[0] << 24) |
  344. ((u32) data[1] << 16);
  345. data += 2;
  346. } else {
  347. val = ((u32) data[0] << 24) |
  348. ((u32) data[1] << 16) |
  349. ((u32) data[2] << 8);
  350. data += 3;
  351. }
  352. sbus_writel(val, &fbc->font);
  353. }
  354. y += 1;
  355. x = image->dx;
  356. }
  357. spin_unlock_irqrestore(&par->lock, flags);
  358. }
  359. /**
  360. * cg6_setcolreg - Optional function. Sets a color register.
  361. * @regno: boolean, 0 copy local, 1 get_user() function
  362. * @red: frame buffer colormap structure
  363. * @green: The green value which can be up to 16 bits wide
  364. * @blue: The blue value which can be up to 16 bits wide.
  365. * @transp: If supported the alpha value which can be up to 16 bits wide.
  366. * @info: frame buffer info structure
  367. */
  368. static int cg6_setcolreg(unsigned regno,
  369. unsigned red, unsigned green, unsigned blue,
  370. unsigned transp, struct fb_info *info)
  371. {
  372. struct cg6_par *par = (struct cg6_par *) info->par;
  373. struct bt_regs __iomem *bt = par->bt;
  374. unsigned long flags;
  375. if (regno >= 256)
  376. return 1;
  377. red >>= 8;
  378. green >>= 8;
  379. blue >>= 8;
  380. spin_lock_irqsave(&par->lock, flags);
  381. sbus_writel((u32)regno << 24, &bt->addr);
  382. sbus_writel((u32)red << 24, &bt->color_map);
  383. sbus_writel((u32)green << 24, &bt->color_map);
  384. sbus_writel((u32)blue << 24, &bt->color_map);
  385. spin_unlock_irqrestore(&par->lock, flags);
  386. return 0;
  387. }
  388. /**
  389. * cg6_blank - Optional function. Blanks the display.
  390. * @blank_mode: the blank mode we want.
  391. * @info: frame buffer structure that represents a single frame buffer
  392. */
  393. static int
  394. cg6_blank(int blank, struct fb_info *info)
  395. {
  396. struct cg6_par *par = (struct cg6_par *) info->par;
  397. struct cg6_thc __iomem *thc = par->thc;
  398. unsigned long flags;
  399. u32 val;
  400. spin_lock_irqsave(&par->lock, flags);
  401. switch (blank) {
  402. case FB_BLANK_UNBLANK: /* Unblanking */
  403. val = sbus_readl(&thc->thc_misc);
  404. val |= CG6_THC_MISC_VIDEO;
  405. sbus_writel(val, &thc->thc_misc);
  406. par->flags &= ~CG6_FLAG_BLANKED;
  407. break;
  408. case FB_BLANK_NORMAL: /* Normal blanking */
  409. case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
  410. case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
  411. case FB_BLANK_POWERDOWN: /* Poweroff */
  412. val = sbus_readl(&thc->thc_misc);
  413. val &= ~CG6_THC_MISC_VIDEO;
  414. sbus_writel(val, &thc->thc_misc);
  415. par->flags |= CG6_FLAG_BLANKED;
  416. break;
  417. }
  418. spin_unlock_irqrestore(&par->lock, flags);
  419. return 0;
  420. }
  421. static struct sbus_mmap_map cg6_mmap_map[] = {
  422. {
  423. .voff = CG6_FBC,
  424. .poff = CG6_FBC_OFFSET,
  425. .size = PAGE_SIZE
  426. },
  427. {
  428. .voff = CG6_TEC,
  429. .poff = CG6_TEC_OFFSET,
  430. .size = PAGE_SIZE
  431. },
  432. {
  433. .voff = CG6_BTREGS,
  434. .poff = CG6_BROOKTREE_OFFSET,
  435. .size = PAGE_SIZE
  436. },
  437. {
  438. .voff = CG6_FHC,
  439. .poff = CG6_FHC_OFFSET,
  440. .size = PAGE_SIZE
  441. },
  442. {
  443. .voff = CG6_THC,
  444. .poff = CG6_THC_OFFSET,
  445. .size = PAGE_SIZE
  446. },
  447. {
  448. .voff = CG6_ROM,
  449. .poff = CG6_ROM_OFFSET,
  450. .size = 0x10000
  451. },
  452. {
  453. .voff = CG6_RAM,
  454. .poff = CG6_RAM_OFFSET,
  455. .size = SBUS_MMAP_FBSIZE(1)
  456. },
  457. {
  458. .voff = CG6_DHC,
  459. .poff = CG6_DHC_OFFSET,
  460. .size = 0x40000
  461. },
  462. { .size = 0 }
  463. };
  464. static int cg6_mmap(struct fb_info *info, struct vm_area_struct *vma)
  465. {
  466. struct cg6_par *par = (struct cg6_par *)info->par;
  467. return sbusfb_mmap_helper(cg6_mmap_map,
  468. par->physbase, par->fbsize,
  469. par->which_io, vma);
  470. }
  471. static int cg6_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  472. {
  473. struct cg6_par *par = (struct cg6_par *) info->par;
  474. return sbusfb_ioctl_helper(cmd, arg, info,
  475. FBTYPE_SUNFAST_COLOR, 8, par->fbsize);
  476. }
  477. /*
  478. * Initialisation
  479. */
  480. static void
  481. cg6_init_fix(struct fb_info *info, int linebytes)
  482. {
  483. struct cg6_par *par = (struct cg6_par *)info->par;
  484. const char *cg6_cpu_name, *cg6_card_name;
  485. u32 conf;
  486. conf = sbus_readl(par->fhc);
  487. switch(conf & CG6_FHC_CPU_MASK) {
  488. case CG6_FHC_CPU_SPARC:
  489. cg6_cpu_name = "sparc";
  490. break;
  491. case CG6_FHC_CPU_68020:
  492. cg6_cpu_name = "68020";
  493. break;
  494. default:
  495. cg6_cpu_name = "i386";
  496. break;
  497. };
  498. if (((conf >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK) >= 11) {
  499. if (par->fbsize <= 0x100000) {
  500. cg6_card_name = "TGX";
  501. } else {
  502. cg6_card_name = "TGX+";
  503. }
  504. } else {
  505. if (par->fbsize <= 0x100000) {
  506. cg6_card_name = "GX";
  507. } else {
  508. cg6_card_name = "GX+";
  509. }
  510. }
  511. sprintf(info->fix.id, "%s %s", cg6_card_name, cg6_cpu_name);
  512. info->fix.id[sizeof(info->fix.id)-1] = 0;
  513. info->fix.type = FB_TYPE_PACKED_PIXELS;
  514. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  515. info->fix.line_length = linebytes;
  516. info->fix.accel = FB_ACCEL_SUN_CGSIX;
  517. }
  518. /* Initialize Brooktree DAC */
  519. static void cg6_bt_init(struct cg6_par *par)
  520. {
  521. struct bt_regs __iomem *bt = par->bt;
  522. sbus_writel(0x04 << 24, &bt->addr); /* color planes */
  523. sbus_writel(0xff << 24, &bt->control);
  524. sbus_writel(0x05 << 24, &bt->addr);
  525. sbus_writel(0x00 << 24, &bt->control);
  526. sbus_writel(0x06 << 24, &bt->addr); /* overlay plane */
  527. sbus_writel(0x73 << 24, &bt->control);
  528. sbus_writel(0x07 << 24, &bt->addr);
  529. sbus_writel(0x00 << 24, &bt->control);
  530. }
  531. static void cg6_chip_init(struct fb_info *info)
  532. {
  533. struct cg6_par *par = (struct cg6_par *) info->par;
  534. struct cg6_tec __iomem *tec = par->tec;
  535. struct cg6_fbc __iomem *fbc = par->fbc;
  536. u32 rev, conf, mode;
  537. int i;
  538. /* Turn off stuff in the Transform Engine. */
  539. sbus_writel(0, &tec->tec_matrix);
  540. sbus_writel(0, &tec->tec_clip);
  541. sbus_writel(0, &tec->tec_vdc);
  542. /* Take care of bugs in old revisions. */
  543. rev = (sbus_readl(par->fhc) >> CG6_FHC_REV_SHIFT) & CG6_FHC_REV_MASK;
  544. if (rev < 5) {
  545. conf = (sbus_readl(par->fhc) & CG6_FHC_RES_MASK) |
  546. CG6_FHC_CPU_68020 | CG6_FHC_TEST |
  547. (11 << CG6_FHC_TEST_X_SHIFT) |
  548. (11 << CG6_FHC_TEST_Y_SHIFT);
  549. if (rev < 2)
  550. conf |= CG6_FHC_DST_DISABLE;
  551. sbus_writel(conf, par->fhc);
  552. }
  553. /* Set things in the FBC. Bad things appear to happen if we do
  554. * back to back store/loads on the mode register, so copy it
  555. * out instead. */
  556. mode = sbus_readl(&fbc->mode);
  557. do {
  558. i = sbus_readl(&fbc->s);
  559. } while (i & 0x10000000);
  560. mode &= ~(CG6_FBC_BLIT_MASK | CG6_FBC_MODE_MASK |
  561. CG6_FBC_DRAW_MASK | CG6_FBC_BWRITE0_MASK |
  562. CG6_FBC_BWRITE1_MASK | CG6_FBC_BREAD_MASK |
  563. CG6_FBC_BDISP_MASK);
  564. mode |= (CG6_FBC_BLIT_SRC | CG6_FBC_MODE_COLOR8 |
  565. CG6_FBC_DRAW_RENDER | CG6_FBC_BWRITE0_ENABLE |
  566. CG6_FBC_BWRITE1_DISABLE | CG6_FBC_BREAD_0 |
  567. CG6_FBC_BDISP_0);
  568. sbus_writel(mode, &fbc->mode);
  569. sbus_writel(0, &fbc->clip);
  570. sbus_writel(0, &fbc->offx);
  571. sbus_writel(0, &fbc->offy);
  572. sbus_writel(0, &fbc->clipminx);
  573. sbus_writel(0, &fbc->clipminy);
  574. sbus_writel(info->var.xres - 1, &fbc->clipmaxx);
  575. sbus_writel(info->var.yres - 1, &fbc->clipmaxy);
  576. }
  577. struct all_info {
  578. struct fb_info info;
  579. struct cg6_par par;
  580. };
  581. static void cg6_unmap_regs(struct of_device *op, struct all_info *all)
  582. {
  583. if (all->par.fbc)
  584. of_iounmap(&op->resource[0], all->par.fbc, 4096);
  585. if (all->par.tec)
  586. of_iounmap(&op->resource[0],
  587. all->par.tec, sizeof(struct cg6_tec));
  588. if (all->par.thc)
  589. of_iounmap(&op->resource[0],
  590. all->par.thc, sizeof(struct cg6_thc));
  591. if (all->par.bt)
  592. of_iounmap(&op->resource[0],
  593. all->par.bt, sizeof(struct bt_regs));
  594. if (all->par.fhc)
  595. of_iounmap(&op->resource[0],
  596. all->par.fhc, sizeof(u32));
  597. if (all->info.screen_base)
  598. of_iounmap(&op->resource[0],
  599. all->info.screen_base, all->par.fbsize);
  600. }
  601. static int __devinit cg6_init_one(struct of_device *op)
  602. {
  603. struct device_node *dp = op->node;
  604. struct all_info *all;
  605. int linebytes, err;
  606. all = kzalloc(sizeof(*all), GFP_KERNEL);
  607. if (!all)
  608. return -ENOMEM;
  609. spin_lock_init(&all->par.lock);
  610. all->par.physbase = op->resource[0].start;
  611. all->par.which_io = op->resource[0].flags & IORESOURCE_BITS;
  612. sbusfb_fill_var(&all->info.var, dp->node, 8);
  613. all->info.var.red.length = 8;
  614. all->info.var.green.length = 8;
  615. all->info.var.blue.length = 8;
  616. linebytes = of_getintprop_default(dp, "linebytes",
  617. all->info.var.xres);
  618. all->par.fbsize = PAGE_ALIGN(linebytes * all->info.var.yres);
  619. if (of_find_property(dp, "dblbuf", NULL))
  620. all->par.fbsize *= 4;
  621. all->par.fbc = of_ioremap(&op->resource[0], CG6_FBC_OFFSET,
  622. 4096, "cgsix fbc");
  623. all->par.tec = of_ioremap(&op->resource[0], CG6_TEC_OFFSET,
  624. sizeof(struct cg6_tec), "cgsix tec");
  625. all->par.thc = of_ioremap(&op->resource[0], CG6_THC_OFFSET,
  626. sizeof(struct cg6_thc), "cgsix thc");
  627. all->par.bt = of_ioremap(&op->resource[0], CG6_BROOKTREE_OFFSET,
  628. sizeof(struct bt_regs), "cgsix dac");
  629. all->par.fhc = of_ioremap(&op->resource[0], CG6_FHC_OFFSET,
  630. sizeof(u32), "cgsix fhc");
  631. all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_IMAGEBLIT |
  632. FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
  633. all->info.fbops = &cg6_ops;
  634. all->info.screen_base = of_ioremap(&op->resource[0], CG6_RAM_OFFSET,
  635. all->par.fbsize, "cgsix ram");
  636. if (!all->par.fbc || !all->par.tec || !all->par.thc ||
  637. !all->par.bt || !all->par.fhc || !all->info.screen_base) {
  638. cg6_unmap_regs(op, all);
  639. kfree(all);
  640. return -ENOMEM;
  641. }
  642. all->info.par = &all->par;
  643. all->info.var.accel_flags = FB_ACCELF_TEXT;
  644. cg6_bt_init(&all->par);
  645. cg6_chip_init(&all->info);
  646. cg6_blank(0, &all->info);
  647. if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
  648. cg6_unmap_regs(op, all);
  649. kfree(all);
  650. return -ENOMEM;
  651. }
  652. fb_set_cmap(&all->info.cmap, &all->info);
  653. cg6_init_fix(&all->info, linebytes);
  654. err = register_framebuffer(&all->info);
  655. if (err < 0) {
  656. cg6_unmap_regs(op, all);
  657. fb_dealloc_cmap(&all->info.cmap);
  658. kfree(all);
  659. return err;
  660. }
  661. dev_set_drvdata(&op->dev, all);
  662. printk("%s: CGsix [%s] at %lx:%lx\n",
  663. dp->full_name,
  664. all->info.fix.id,
  665. all->par.which_io, all->par.physbase);
  666. return 0;
  667. }
  668. static int __devinit cg6_probe(struct of_device *dev, const struct of_device_id *match)
  669. {
  670. struct of_device *op = to_of_device(&dev->dev);
  671. return cg6_init_one(op);
  672. }
  673. static int __devexit cg6_remove(struct of_device *op)
  674. {
  675. struct all_info *all = dev_get_drvdata(&op->dev);
  676. unregister_framebuffer(&all->info);
  677. fb_dealloc_cmap(&all->info.cmap);
  678. cg6_unmap_regs(op, all);
  679. kfree(all);
  680. dev_set_drvdata(&op->dev, NULL);
  681. return 0;
  682. }
  683. static struct of_device_id cg6_match[] = {
  684. {
  685. .name = "cgsix",
  686. },
  687. {
  688. .name = "cgthree+",
  689. },
  690. {},
  691. };
  692. MODULE_DEVICE_TABLE(of, cg6_match);
  693. static struct of_platform_driver cg6_driver = {
  694. .name = "cg6",
  695. .match_table = cg6_match,
  696. .probe = cg6_probe,
  697. .remove = __devexit_p(cg6_remove),
  698. };
  699. static int __init cg6_init(void)
  700. {
  701. if (fb_get_options("cg6fb", NULL))
  702. return -ENODEV;
  703. return of_register_driver(&cg6_driver, &of_bus_type);
  704. }
  705. static void __exit cg6_exit(void)
  706. {
  707. of_unregister_driver(&cg6_driver);
  708. }
  709. module_init(cg6_init);
  710. module_exit(cg6_exit);
  711. MODULE_DESCRIPTION("framebuffer driver for CGsix chipsets");
  712. MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
  713. MODULE_VERSION("2.0");
  714. MODULE_LICENSE("GPL");