s3c2410.c 44 KB

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  1. /*
  2. * linux/drivers/serial/s3c2410.c
  3. *
  4. * Driver for onboard UARTs on the Samsung S3C24XX
  5. *
  6. * Based on drivers/char/serial.c and drivers/char/21285.c
  7. *
  8. * Ben Dooks, (c) 2003-2005 Simtec Electronics
  9. * http://www.simtec.co.uk/products/SWLINUX/
  10. *
  11. * Changelog:
  12. *
  13. * 22-Jul-2004 BJD Finished off device rewrite
  14. *
  15. * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
  16. * problems with baud rate and loss of IR settings. Update
  17. * to add configuration via platform_device structure
  18. *
  19. * 28-Sep-2004 BJD Re-write for the following items
  20. * - S3C2410 and S3C2440 serial support
  21. * - Power Management support
  22. * - Fix console via IrDA devices
  23. * - SysReq (Herbert P?zl)
  24. * - Break character handling (Herbert P?zl)
  25. * - spin-lock initialisation (Dimitry Andric)
  26. * - added clock control
  27. * - updated init code to use platform_device info
  28. *
  29. * 06-Mar-2005 BJD Add s3c2440 fclk clock source
  30. *
  31. * 09-Mar-2005 BJD Add s3c2400 support
  32. *
  33. * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
  34. */
  35. /* Note on 2440 fclk clock source handling
  36. *
  37. * Whilst it is possible to use the fclk as clock source, the method
  38. * of properly switching too/from this is currently un-implemented, so
  39. * whichever way is configured at startup is the one that will be used.
  40. */
  41. /* Hote on 2410 error handling
  42. *
  43. * The s3c2410 manual has a love/hate affair with the contents of the
  44. * UERSTAT register in the UART blocks, and keeps marking some of the
  45. * error bits as reserved. Having checked with the s3c2410x01,
  46. * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  47. * feature from the latter versions of the manual.
  48. *
  49. * If it becomes aparrent that latter versions of the 2410 remove these
  50. * bits, then action will have to be taken to differentiate the versions
  51. * and change the policy on BREAK
  52. *
  53. * BJD, 04-Nov-2004
  54. */
  55. #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  56. #define SUPPORT_SYSRQ
  57. #endif
  58. #include <linux/module.h>
  59. #include <linux/ioport.h>
  60. #include <linux/platform_device.h>
  61. #include <linux/init.h>
  62. #include <linux/sysrq.h>
  63. #include <linux/console.h>
  64. #include <linux/tty.h>
  65. #include <linux/tty_flip.h>
  66. #include <linux/serial_core.h>
  67. #include <linux/serial.h>
  68. #include <linux/delay.h>
  69. #include <linux/clk.h>
  70. #include <asm/io.h>
  71. #include <asm/irq.h>
  72. #include <asm/hardware.h>
  73. #include <asm/arch/regs-serial.h>
  74. #include <asm/arch/regs-gpio.h>
  75. /* structures */
  76. struct s3c24xx_uart_info {
  77. char *name;
  78. unsigned int type;
  79. unsigned int fifosize;
  80. unsigned long rx_fifomask;
  81. unsigned long rx_fifoshift;
  82. unsigned long rx_fifofull;
  83. unsigned long tx_fifomask;
  84. unsigned long tx_fifoshift;
  85. unsigned long tx_fifofull;
  86. /* clock source control */
  87. int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
  88. int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
  89. /* uart controls */
  90. int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
  91. };
  92. struct s3c24xx_uart_port {
  93. unsigned char rx_claimed;
  94. unsigned char tx_claimed;
  95. struct s3c24xx_uart_info *info;
  96. struct s3c24xx_uart_clksrc *clksrc;
  97. struct clk *clk;
  98. struct clk *baudclk;
  99. struct uart_port port;
  100. };
  101. /* configuration defines */
  102. #if 0
  103. #if 1
  104. /* send debug to the low-level output routines */
  105. extern void printascii(const char *);
  106. static void
  107. s3c24xx_serial_dbg(const char *fmt, ...)
  108. {
  109. va_list va;
  110. char buff[256];
  111. va_start(va, fmt);
  112. vsprintf(buff, fmt, va);
  113. va_end(va);
  114. printascii(buff);
  115. }
  116. #define dbg(x...) s3c24xx_serial_dbg(x)
  117. #else
  118. #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
  119. #endif
  120. #else /* no debug */
  121. #define dbg(x...) do {} while(0)
  122. #endif
  123. /* UART name and device definitions */
  124. #define S3C24XX_SERIAL_NAME "ttySAC"
  125. #define S3C24XX_SERIAL_MAJOR 204
  126. #define S3C24XX_SERIAL_MINOR 64
  127. /* conversion functions */
  128. #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
  129. #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
  130. /* we can support 3 uarts, but not always use them */
  131. #ifdef CONFIG_CPU_S3C2400
  132. #define NR_PORTS (2)
  133. #else
  134. #define NR_PORTS (3)
  135. #endif
  136. /* port irq numbers */
  137. #define TX_IRQ(port) ((port)->irq + 1)
  138. #define RX_IRQ(port) ((port)->irq)
  139. /* register access controls */
  140. #define portaddr(port, reg) ((port)->membase + (reg))
  141. #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
  142. #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
  143. #define wr_regb(port, reg, val) \
  144. do { __raw_writeb(val, portaddr(port, reg)); } while(0)
  145. #define wr_regl(port, reg, val) \
  146. do { __raw_writel(val, portaddr(port, reg)); } while(0)
  147. /* macros to change one thing to another */
  148. #define tx_enabled(port) ((port)->unused[0])
  149. #define rx_enabled(port) ((port)->unused[1])
  150. /* flag to ignore all characters comming in */
  151. #define RXSTAT_DUMMY_READ (0x10000000)
  152. static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  153. {
  154. return container_of(port, struct s3c24xx_uart_port, port);
  155. }
  156. /* translate a port to the device name */
  157. static inline const char *s3c24xx_serial_portname(struct uart_port *port)
  158. {
  159. return to_platform_device(port->dev)->name;
  160. }
  161. static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
  162. {
  163. return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
  164. }
  165. static void s3c24xx_serial_rx_enable(struct uart_port *port)
  166. {
  167. unsigned long flags;
  168. unsigned int ucon, ufcon;
  169. int count = 10000;
  170. spin_lock_irqsave(&port->lock, flags);
  171. while (--count && !s3c24xx_serial_txempty_nofifo(port))
  172. udelay(100);
  173. ufcon = rd_regl(port, S3C2410_UFCON);
  174. ufcon |= S3C2410_UFCON_RESETRX;
  175. wr_regl(port, S3C2410_UFCON, ufcon);
  176. ucon = rd_regl(port, S3C2410_UCON);
  177. ucon |= S3C2410_UCON_RXIRQMODE;
  178. wr_regl(port, S3C2410_UCON, ucon);
  179. rx_enabled(port) = 1;
  180. spin_unlock_irqrestore(&port->lock, flags);
  181. }
  182. static void s3c24xx_serial_rx_disable(struct uart_port *port)
  183. {
  184. unsigned long flags;
  185. unsigned int ucon;
  186. spin_lock_irqsave(&port->lock, flags);
  187. ucon = rd_regl(port, S3C2410_UCON);
  188. ucon &= ~S3C2410_UCON_RXIRQMODE;
  189. wr_regl(port, S3C2410_UCON, ucon);
  190. rx_enabled(port) = 0;
  191. spin_unlock_irqrestore(&port->lock, flags);
  192. }
  193. static void s3c24xx_serial_stop_tx(struct uart_port *port)
  194. {
  195. if (tx_enabled(port)) {
  196. disable_irq(TX_IRQ(port));
  197. tx_enabled(port) = 0;
  198. if (port->flags & UPF_CONS_FLOW)
  199. s3c24xx_serial_rx_enable(port);
  200. }
  201. }
  202. static void s3c24xx_serial_start_tx(struct uart_port *port)
  203. {
  204. if (!tx_enabled(port)) {
  205. if (port->flags & UPF_CONS_FLOW)
  206. s3c24xx_serial_rx_disable(port);
  207. enable_irq(TX_IRQ(port));
  208. tx_enabled(port) = 1;
  209. }
  210. }
  211. static void s3c24xx_serial_stop_rx(struct uart_port *port)
  212. {
  213. if (rx_enabled(port)) {
  214. dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
  215. disable_irq(RX_IRQ(port));
  216. rx_enabled(port) = 0;
  217. }
  218. }
  219. static void s3c24xx_serial_enable_ms(struct uart_port *port)
  220. {
  221. }
  222. static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
  223. {
  224. return to_ourport(port)->info;
  225. }
  226. static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
  227. {
  228. if (port->dev == NULL)
  229. return NULL;
  230. return (struct s3c2410_uartcfg *)port->dev->platform_data;
  231. }
  232. static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
  233. unsigned long ufstat)
  234. {
  235. struct s3c24xx_uart_info *info = ourport->info;
  236. if (ufstat & info->rx_fifofull)
  237. return info->fifosize;
  238. return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
  239. }
  240. /* ? - where has parity gone?? */
  241. #define S3C2410_UERSTAT_PARITY (0x1000)
  242. static irqreturn_t
  243. s3c24xx_serial_rx_chars(int irq, void *dev_id)
  244. {
  245. struct s3c24xx_uart_port *ourport = dev_id;
  246. struct uart_port *port = &ourport->port;
  247. struct tty_struct *tty = port->info->tty;
  248. unsigned int ufcon, ch, flag, ufstat, uerstat;
  249. int max_count = 64;
  250. while (max_count-- > 0) {
  251. ufcon = rd_regl(port, S3C2410_UFCON);
  252. ufstat = rd_regl(port, S3C2410_UFSTAT);
  253. if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
  254. break;
  255. uerstat = rd_regl(port, S3C2410_UERSTAT);
  256. ch = rd_regb(port, S3C2410_URXH);
  257. if (port->flags & UPF_CONS_FLOW) {
  258. int txe = s3c24xx_serial_txempty_nofifo(port);
  259. if (rx_enabled(port)) {
  260. if (!txe) {
  261. rx_enabled(port) = 0;
  262. continue;
  263. }
  264. } else {
  265. if (txe) {
  266. ufcon |= S3C2410_UFCON_RESETRX;
  267. wr_regl(port, S3C2410_UFCON, ufcon);
  268. rx_enabled(port) = 1;
  269. goto out;
  270. }
  271. continue;
  272. }
  273. }
  274. /* insert the character into the buffer */
  275. flag = TTY_NORMAL;
  276. port->icount.rx++;
  277. if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
  278. dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
  279. ch, uerstat);
  280. /* check for break */
  281. if (uerstat & S3C2410_UERSTAT_BREAK) {
  282. dbg("break!\n");
  283. port->icount.brk++;
  284. if (uart_handle_break(port))
  285. goto ignore_char;
  286. }
  287. if (uerstat & S3C2410_UERSTAT_FRAME)
  288. port->icount.frame++;
  289. if (uerstat & S3C2410_UERSTAT_OVERRUN)
  290. port->icount.overrun++;
  291. uerstat &= port->read_status_mask;
  292. if (uerstat & S3C2410_UERSTAT_BREAK)
  293. flag = TTY_BREAK;
  294. else if (uerstat & S3C2410_UERSTAT_PARITY)
  295. flag = TTY_PARITY;
  296. else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
  297. flag = TTY_FRAME;
  298. }
  299. if (uart_handle_sysrq_char(port, ch))
  300. goto ignore_char;
  301. uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
  302. ignore_char:
  303. continue;
  304. }
  305. tty_flip_buffer_push(tty);
  306. out:
  307. return IRQ_HANDLED;
  308. }
  309. static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
  310. {
  311. struct s3c24xx_uart_port *ourport = id;
  312. struct uart_port *port = &ourport->port;
  313. struct circ_buf *xmit = &port->info->xmit;
  314. int count = 256;
  315. if (port->x_char) {
  316. wr_regb(port, S3C2410_UTXH, port->x_char);
  317. port->icount.tx++;
  318. port->x_char = 0;
  319. goto out;
  320. }
  321. /* if there isnt anything more to transmit, or the uart is now
  322. * stopped, disable the uart and exit
  323. */
  324. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  325. s3c24xx_serial_stop_tx(port);
  326. goto out;
  327. }
  328. /* try and drain the buffer... */
  329. while (!uart_circ_empty(xmit) && count-- > 0) {
  330. if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
  331. break;
  332. wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
  333. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  334. port->icount.tx++;
  335. }
  336. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  337. uart_write_wakeup(port);
  338. if (uart_circ_empty(xmit))
  339. s3c24xx_serial_stop_tx(port);
  340. out:
  341. return IRQ_HANDLED;
  342. }
  343. static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
  344. {
  345. struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
  346. unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
  347. unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
  348. if (ufcon & S3C2410_UFCON_FIFOMODE) {
  349. if ((ufstat & info->tx_fifomask) != 0 ||
  350. (ufstat & info->tx_fifofull))
  351. return 0;
  352. return 1;
  353. }
  354. return s3c24xx_serial_txempty_nofifo(port);
  355. }
  356. /* no modem control lines */
  357. static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
  358. {
  359. unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
  360. if (umstat & S3C2410_UMSTAT_CTS)
  361. return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
  362. else
  363. return TIOCM_CAR | TIOCM_DSR;
  364. }
  365. static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
  366. {
  367. /* todo - possibly remove AFC and do manual CTS */
  368. }
  369. static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
  370. {
  371. unsigned long flags;
  372. unsigned int ucon;
  373. spin_lock_irqsave(&port->lock, flags);
  374. ucon = rd_regl(port, S3C2410_UCON);
  375. if (break_state)
  376. ucon |= S3C2410_UCON_SBREAK;
  377. else
  378. ucon &= ~S3C2410_UCON_SBREAK;
  379. wr_regl(port, S3C2410_UCON, ucon);
  380. spin_unlock_irqrestore(&port->lock, flags);
  381. }
  382. static void s3c24xx_serial_shutdown(struct uart_port *port)
  383. {
  384. struct s3c24xx_uart_port *ourport = to_ourport(port);
  385. if (ourport->tx_claimed) {
  386. free_irq(TX_IRQ(port), ourport);
  387. tx_enabled(port) = 0;
  388. ourport->tx_claimed = 0;
  389. }
  390. if (ourport->rx_claimed) {
  391. free_irq(RX_IRQ(port), ourport);
  392. ourport->rx_claimed = 0;
  393. rx_enabled(port) = 0;
  394. }
  395. }
  396. static int s3c24xx_serial_startup(struct uart_port *port)
  397. {
  398. struct s3c24xx_uart_port *ourport = to_ourport(port);
  399. int ret;
  400. dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
  401. port->mapbase, port->membase);
  402. rx_enabled(port) = 1;
  403. ret = request_irq(RX_IRQ(port),
  404. s3c24xx_serial_rx_chars, 0,
  405. s3c24xx_serial_portname(port), ourport);
  406. if (ret != 0) {
  407. printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
  408. return ret;
  409. }
  410. ourport->rx_claimed = 1;
  411. dbg("requesting tx irq...\n");
  412. tx_enabled(port) = 1;
  413. ret = request_irq(TX_IRQ(port),
  414. s3c24xx_serial_tx_chars, 0,
  415. s3c24xx_serial_portname(port), ourport);
  416. if (ret) {
  417. printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
  418. goto err;
  419. }
  420. ourport->tx_claimed = 1;
  421. dbg("s3c24xx_serial_startup ok\n");
  422. /* the port reset code should have done the correct
  423. * register setup for the port controls */
  424. return ret;
  425. err:
  426. s3c24xx_serial_shutdown(port);
  427. return ret;
  428. }
  429. /* power power management control */
  430. static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
  431. unsigned int old)
  432. {
  433. struct s3c24xx_uart_port *ourport = to_ourport(port);
  434. switch (level) {
  435. case 3:
  436. if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
  437. clk_disable(ourport->baudclk);
  438. clk_disable(ourport->clk);
  439. break;
  440. case 0:
  441. clk_enable(ourport->clk);
  442. if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
  443. clk_enable(ourport->baudclk);
  444. break;
  445. default:
  446. printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
  447. }
  448. }
  449. /* baud rate calculation
  450. *
  451. * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
  452. * of different sources, including the peripheral clock ("pclk") and an
  453. * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
  454. * with a programmable extra divisor.
  455. *
  456. * The following code goes through the clock sources, and calculates the
  457. * baud clocks (and the resultant actual baud rates) and then tries to
  458. * pick the closest one and select that.
  459. *
  460. */
  461. #define MAX_CLKS (8)
  462. static struct s3c24xx_uart_clksrc tmp_clksrc = {
  463. .name = "pclk",
  464. .min_baud = 0,
  465. .max_baud = 0,
  466. .divisor = 1,
  467. };
  468. static inline int
  469. s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
  470. {
  471. struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
  472. return (info->get_clksrc)(port, c);
  473. }
  474. static inline int
  475. s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
  476. {
  477. struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
  478. return (info->set_clksrc)(port, c);
  479. }
  480. struct baud_calc {
  481. struct s3c24xx_uart_clksrc *clksrc;
  482. unsigned int calc;
  483. unsigned int quot;
  484. struct clk *src;
  485. };
  486. static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
  487. struct uart_port *port,
  488. struct s3c24xx_uart_clksrc *clksrc,
  489. unsigned int baud)
  490. {
  491. unsigned long rate;
  492. calc->src = clk_get(port->dev, clksrc->name);
  493. if (calc->src == NULL || IS_ERR(calc->src))
  494. return 0;
  495. rate = clk_get_rate(calc->src);
  496. rate /= clksrc->divisor;
  497. calc->clksrc = clksrc;
  498. #if 0
  499. /* Error to calculation of UART BAUD RATE DIVISOR */
  500. calc->quot = (rate + (8 * baud)) / (16 * baud);
  501. #else
  502. /* Error correction */
  503. calc->quot = (rate) / (16 * baud);
  504. #endif
  505. calc->calc = (rate / (calc->quot * 16));
  506. calc->quot--;
  507. return 1;
  508. }
  509. static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
  510. struct s3c24xx_uart_clksrc **clksrc,
  511. struct clk **clk,
  512. unsigned int baud)
  513. {
  514. struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
  515. struct s3c24xx_uart_clksrc *clkp;
  516. struct baud_calc res[MAX_CLKS];
  517. struct baud_calc *resptr, *best, *sptr;
  518. int i;
  519. clkp = cfg->clocks;
  520. best = NULL;
  521. if (cfg->clocks_size < 2) {
  522. if (cfg->clocks_size == 0)
  523. clkp = &tmp_clksrc;
  524. /* check to see if we're sourcing fclk, and if so we're
  525. * going to have to update the clock source
  526. */
  527. if (strcmp(clkp->name, "fclk") == 0) {
  528. struct s3c24xx_uart_clksrc src;
  529. s3c24xx_serial_getsource(port, &src);
  530. /* check that the port already using fclk, and if
  531. * not, then re-select fclk
  532. */
  533. if (strcmp(src.name, clkp->name) == 0) {
  534. s3c24xx_serial_setsource(port, clkp);
  535. s3c24xx_serial_getsource(port, &src);
  536. }
  537. clkp->divisor = src.divisor;
  538. }
  539. s3c24xx_serial_calcbaud(res, port, clkp, baud);
  540. best = res;
  541. resptr = best + 1;
  542. } else {
  543. resptr = res;
  544. for (i = 0; i < cfg->clocks_size; i++, clkp++) {
  545. if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
  546. resptr++;
  547. }
  548. }
  549. /* ok, we now need to select the best clock we found */
  550. if (!best) {
  551. unsigned int deviation = (1<<30)|((1<<30)-1);
  552. int calc_deviation;
  553. for (sptr = res; sptr < resptr; sptr++) {
  554. printk(KERN_DEBUG
  555. "found clk %p (%s) quot %d, calc %d\n",
  556. sptr->clksrc, sptr->clksrc->name,
  557. sptr->quot, sptr->calc);
  558. calc_deviation = baud - sptr->calc;
  559. if (calc_deviation < 0)
  560. calc_deviation = -calc_deviation;
  561. if (calc_deviation < deviation) {
  562. best = sptr;
  563. deviation = calc_deviation;
  564. }
  565. }
  566. printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
  567. }
  568. if (best != NULL){
  569. printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
  570. best->clksrc, best->clksrc->name, best->quot, best->calc);
  571. }
  572. /* store results to pass back */
  573. *clksrc = best->clksrc;
  574. *clk = best->src;
  575. return best->quot;
  576. }
  577. static void s3c24xx_serial_set_termios(struct uart_port *port,
  578. struct ktermios *termios,
  579. struct ktermios *old)
  580. {
  581. struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
  582. struct s3c24xx_uart_port *ourport = to_ourport(port);
  583. struct s3c24xx_uart_clksrc *clksrc = NULL;
  584. struct clk *clk = NULL;
  585. unsigned long flags;
  586. unsigned int baud, quot;
  587. unsigned int ulcon;
  588. unsigned int umcon;
  589. /*
  590. * We don't support modem control lines.
  591. */
  592. termios->c_cflag &= ~(HUPCL | CMSPAR);
  593. termios->c_cflag |= CLOCAL;
  594. /*
  595. * Ask the core to calculate the divisor for us.
  596. */
  597. baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
  598. if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
  599. quot = port->custom_divisor;
  600. else
  601. quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
  602. /* check to see if we need to change clock source */
  603. if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
  604. s3c24xx_serial_setsource(port, clksrc);
  605. if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
  606. clk_disable(ourport->baudclk);
  607. ourport->baudclk = NULL;
  608. }
  609. clk_enable(clk);
  610. ourport->clksrc = clksrc;
  611. ourport->baudclk = clk;
  612. }
  613. switch (termios->c_cflag & CSIZE) {
  614. case CS5:
  615. dbg("config: 5bits/char\n");
  616. ulcon = S3C2410_LCON_CS5;
  617. break;
  618. case CS6:
  619. dbg("config: 6bits/char\n");
  620. ulcon = S3C2410_LCON_CS6;
  621. break;
  622. case CS7:
  623. dbg("config: 7bits/char\n");
  624. ulcon = S3C2410_LCON_CS7;
  625. break;
  626. case CS8:
  627. default:
  628. dbg("config: 8bits/char\n");
  629. ulcon = S3C2410_LCON_CS8;
  630. break;
  631. }
  632. /* preserve original lcon IR settings */
  633. ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
  634. if (termios->c_cflag & CSTOPB)
  635. ulcon |= S3C2410_LCON_STOPB;
  636. umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
  637. if (termios->c_cflag & PARENB) {
  638. if (termios->c_cflag & PARODD)
  639. ulcon |= S3C2410_LCON_PODD;
  640. else
  641. ulcon |= S3C2410_LCON_PEVEN;
  642. } else {
  643. ulcon |= S3C2410_LCON_PNONE;
  644. }
  645. spin_lock_irqsave(&port->lock, flags);
  646. dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
  647. wr_regl(port, S3C2410_ULCON, ulcon);
  648. wr_regl(port, S3C2410_UBRDIV, quot);
  649. wr_regl(port, S3C2410_UMCON, umcon);
  650. dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
  651. rd_regl(port, S3C2410_ULCON),
  652. rd_regl(port, S3C2410_UCON),
  653. rd_regl(port, S3C2410_UFCON));
  654. /*
  655. * Update the per-port timeout.
  656. */
  657. uart_update_timeout(port, termios->c_cflag, baud);
  658. /*
  659. * Which character status flags are we interested in?
  660. */
  661. port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
  662. if (termios->c_iflag & INPCK)
  663. port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
  664. /*
  665. * Which character status flags should we ignore?
  666. */
  667. port->ignore_status_mask = 0;
  668. if (termios->c_iflag & IGNPAR)
  669. port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
  670. if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
  671. port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
  672. /*
  673. * Ignore all characters if CREAD is not set.
  674. */
  675. if ((termios->c_cflag & CREAD) == 0)
  676. port->ignore_status_mask |= RXSTAT_DUMMY_READ;
  677. spin_unlock_irqrestore(&port->lock, flags);
  678. }
  679. static const char *s3c24xx_serial_type(struct uart_port *port)
  680. {
  681. switch (port->type) {
  682. case PORT_S3C2410:
  683. return "S3C2410";
  684. case PORT_S3C2440:
  685. return "S3C2440";
  686. case PORT_S3C2412:
  687. return "S3C2412";
  688. default:
  689. return NULL;
  690. }
  691. }
  692. #define MAP_SIZE (0x100)
  693. static void s3c24xx_serial_release_port(struct uart_port *port)
  694. {
  695. release_mem_region(port->mapbase, MAP_SIZE);
  696. }
  697. static int s3c24xx_serial_request_port(struct uart_port *port)
  698. {
  699. const char *name = s3c24xx_serial_portname(port);
  700. return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
  701. }
  702. static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
  703. {
  704. struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
  705. if (flags & UART_CONFIG_TYPE &&
  706. s3c24xx_serial_request_port(port) == 0)
  707. port->type = info->type;
  708. }
  709. /*
  710. * verify the new serial_struct (for TIOCSSERIAL).
  711. */
  712. static int
  713. s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
  714. {
  715. struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
  716. if (ser->type != PORT_UNKNOWN && ser->type != info->type)
  717. return -EINVAL;
  718. return 0;
  719. }
  720. #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
  721. static struct console s3c24xx_serial_console;
  722. #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
  723. #else
  724. #define S3C24XX_SERIAL_CONSOLE NULL
  725. #endif
  726. static struct uart_ops s3c24xx_serial_ops = {
  727. .pm = s3c24xx_serial_pm,
  728. .tx_empty = s3c24xx_serial_tx_empty,
  729. .get_mctrl = s3c24xx_serial_get_mctrl,
  730. .set_mctrl = s3c24xx_serial_set_mctrl,
  731. .stop_tx = s3c24xx_serial_stop_tx,
  732. .start_tx = s3c24xx_serial_start_tx,
  733. .stop_rx = s3c24xx_serial_stop_rx,
  734. .enable_ms = s3c24xx_serial_enable_ms,
  735. .break_ctl = s3c24xx_serial_break_ctl,
  736. .startup = s3c24xx_serial_startup,
  737. .shutdown = s3c24xx_serial_shutdown,
  738. .set_termios = s3c24xx_serial_set_termios,
  739. .type = s3c24xx_serial_type,
  740. .release_port = s3c24xx_serial_release_port,
  741. .request_port = s3c24xx_serial_request_port,
  742. .config_port = s3c24xx_serial_config_port,
  743. .verify_port = s3c24xx_serial_verify_port,
  744. };
  745. static struct uart_driver s3c24xx_uart_drv = {
  746. .owner = THIS_MODULE,
  747. .dev_name = "s3c2410_serial",
  748. .nr = 3,
  749. .cons = S3C24XX_SERIAL_CONSOLE,
  750. .driver_name = S3C24XX_SERIAL_NAME,
  751. .major = S3C24XX_SERIAL_MAJOR,
  752. .minor = S3C24XX_SERIAL_MINOR,
  753. };
  754. static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
  755. [0] = {
  756. .port = {
  757. .lock = SPIN_LOCK_UNLOCKED,
  758. .iotype = UPIO_MEM,
  759. .irq = IRQ_S3CUART_RX0,
  760. .uartclk = 0,
  761. .fifosize = 16,
  762. .ops = &s3c24xx_serial_ops,
  763. .flags = UPF_BOOT_AUTOCONF,
  764. .line = 0,
  765. }
  766. },
  767. [1] = {
  768. .port = {
  769. .lock = SPIN_LOCK_UNLOCKED,
  770. .iotype = UPIO_MEM,
  771. .irq = IRQ_S3CUART_RX1,
  772. .uartclk = 0,
  773. .fifosize = 16,
  774. .ops = &s3c24xx_serial_ops,
  775. .flags = UPF_BOOT_AUTOCONF,
  776. .line = 1,
  777. }
  778. },
  779. #if NR_PORTS > 2
  780. [2] = {
  781. .port = {
  782. .lock = SPIN_LOCK_UNLOCKED,
  783. .iotype = UPIO_MEM,
  784. .irq = IRQ_S3CUART_RX2,
  785. .uartclk = 0,
  786. .fifosize = 16,
  787. .ops = &s3c24xx_serial_ops,
  788. .flags = UPF_BOOT_AUTOCONF,
  789. .line = 2,
  790. }
  791. }
  792. #endif
  793. };
  794. /* s3c24xx_serial_resetport
  795. *
  796. * wrapper to call the specific reset for this port (reset the fifos
  797. * and the settings)
  798. */
  799. static inline int s3c24xx_serial_resetport(struct uart_port * port,
  800. struct s3c2410_uartcfg *cfg)
  801. {
  802. struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
  803. return (info->reset_port)(port, cfg);
  804. }
  805. /* s3c24xx_serial_init_port
  806. *
  807. * initialise a single serial port from the platform device given
  808. */
  809. static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
  810. struct s3c24xx_uart_info *info,
  811. struct platform_device *platdev)
  812. {
  813. struct uart_port *port = &ourport->port;
  814. struct s3c2410_uartcfg *cfg;
  815. struct resource *res;
  816. dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
  817. if (platdev == NULL)
  818. return -ENODEV;
  819. cfg = s3c24xx_dev_to_cfg(&platdev->dev);
  820. if (port->mapbase != 0)
  821. return 0;
  822. if (cfg->hwport > 3)
  823. return -EINVAL;
  824. /* setup info for port */
  825. port->dev = &platdev->dev;
  826. ourport->info = info;
  827. /* copy the info in from provided structure */
  828. ourport->port.fifosize = info->fifosize;
  829. dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
  830. port->uartclk = 1;
  831. if (cfg->uart_flags & UPF_CONS_FLOW) {
  832. dbg("s3c24xx_serial_init_port: enabling flow control\n");
  833. port->flags |= UPF_CONS_FLOW;
  834. }
  835. /* sort our the physical and virtual addresses for each UART */
  836. res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
  837. if (res == NULL) {
  838. printk(KERN_ERR "failed to find memory resource for uart\n");
  839. return -EINVAL;
  840. }
  841. dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
  842. port->mapbase = res->start;
  843. port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
  844. port->irq = platform_get_irq(platdev, 0);
  845. #if 0
  846. if (port->irq < 0)
  847. port->irq = 0;
  848. #endif
  849. ourport->clk = clk_get(&platdev->dev, "uart");
  850. dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
  851. port->mapbase, port->membase, port->irq, port->uartclk);
  852. /* reset the fifos (and setup the uart) */
  853. s3c24xx_serial_resetport(port, cfg);
  854. return 0;
  855. }
  856. /* Device driver serial port probe */
  857. static int probe_index = 0;
  858. static int s3c24xx_serial_probe(struct platform_device *dev,
  859. struct s3c24xx_uart_info *info)
  860. {
  861. struct s3c24xx_uart_port *ourport;
  862. int ret;
  863. dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
  864. ourport = &s3c24xx_serial_ports[probe_index];
  865. probe_index++;
  866. dbg("%s: initialising port %p...\n", __FUNCTION__, ourport);
  867. ret = s3c24xx_serial_init_port(ourport, info, dev);
  868. if (ret < 0)
  869. goto probe_err;
  870. dbg("%s: adding port\n", __FUNCTION__);
  871. uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
  872. platform_set_drvdata(dev, &ourport->port);
  873. return 0;
  874. probe_err:
  875. return ret;
  876. }
  877. static int s3c24xx_serial_remove(struct platform_device *dev)
  878. {
  879. struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
  880. if (port)
  881. uart_remove_one_port(&s3c24xx_uart_drv, port);
  882. return 0;
  883. }
  884. /* UART power management code */
  885. #ifdef CONFIG_PM
  886. static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
  887. {
  888. struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
  889. if (port)
  890. uart_suspend_port(&s3c24xx_uart_drv, port);
  891. return 0;
  892. }
  893. static int s3c24xx_serial_resume(struct platform_device *dev)
  894. {
  895. struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
  896. struct s3c24xx_uart_port *ourport = to_ourport(port);
  897. if (port) {
  898. clk_enable(ourport->clk);
  899. s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
  900. clk_disable(ourport->clk);
  901. uart_resume_port(&s3c24xx_uart_drv, port);
  902. }
  903. return 0;
  904. }
  905. #else
  906. #define s3c24xx_serial_suspend NULL
  907. #define s3c24xx_serial_resume NULL
  908. #endif
  909. static int s3c24xx_serial_init(struct platform_driver *drv,
  910. struct s3c24xx_uart_info *info)
  911. {
  912. dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
  913. return platform_driver_register(drv);
  914. }
  915. /* now comes the code to initialise either the s3c2410 or s3c2440 serial
  916. * port information
  917. */
  918. /* cpu specific variations on the serial port support */
  919. #ifdef CONFIG_CPU_S3C2400
  920. static int s3c2400_serial_getsource(struct uart_port *port,
  921. struct s3c24xx_uart_clksrc *clk)
  922. {
  923. clk->divisor = 1;
  924. clk->name = "pclk";
  925. return 0;
  926. }
  927. static int s3c2400_serial_setsource(struct uart_port *port,
  928. struct s3c24xx_uart_clksrc *clk)
  929. {
  930. return 0;
  931. }
  932. static int s3c2400_serial_resetport(struct uart_port *port,
  933. struct s3c2410_uartcfg *cfg)
  934. {
  935. dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
  936. port, port->mapbase, cfg);
  937. wr_regl(port, S3C2410_UCON, cfg->ucon);
  938. wr_regl(port, S3C2410_ULCON, cfg->ulcon);
  939. /* reset both fifos */
  940. wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
  941. wr_regl(port, S3C2410_UFCON, cfg->ufcon);
  942. return 0;
  943. }
  944. static struct s3c24xx_uart_info s3c2400_uart_inf = {
  945. .name = "Samsung S3C2400 UART",
  946. .type = PORT_S3C2400,
  947. .fifosize = 16,
  948. .rx_fifomask = S3C2410_UFSTAT_RXMASK,
  949. .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
  950. .rx_fifofull = S3C2410_UFSTAT_RXFULL,
  951. .tx_fifofull = S3C2410_UFSTAT_TXFULL,
  952. .tx_fifomask = S3C2410_UFSTAT_TXMASK,
  953. .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
  954. .get_clksrc = s3c2400_serial_getsource,
  955. .set_clksrc = s3c2400_serial_setsource,
  956. .reset_port = s3c2400_serial_resetport,
  957. };
  958. static int s3c2400_serial_probe(struct platform_device *dev)
  959. {
  960. return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
  961. }
  962. static struct platform_driver s3c2400_serial_drv = {
  963. .probe = s3c2400_serial_probe,
  964. .remove = s3c24xx_serial_remove,
  965. .suspend = s3c24xx_serial_suspend,
  966. .resume = s3c24xx_serial_resume,
  967. .driver = {
  968. .name = "s3c2400-uart",
  969. .owner = THIS_MODULE,
  970. },
  971. };
  972. static inline int s3c2400_serial_init(void)
  973. {
  974. return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
  975. }
  976. static inline void s3c2400_serial_exit(void)
  977. {
  978. platform_driver_unregister(&s3c2400_serial_drv);
  979. }
  980. #define s3c2400_uart_inf_at &s3c2400_uart_inf
  981. #else
  982. static inline int s3c2400_serial_init(void)
  983. {
  984. return 0;
  985. }
  986. static inline void s3c2400_serial_exit(void)
  987. {
  988. }
  989. #define s3c2400_uart_inf_at NULL
  990. #endif /* CONFIG_CPU_S3C2400 */
  991. /* S3C2410 support */
  992. #ifdef CONFIG_CPU_S3C2410
  993. static int s3c2410_serial_setsource(struct uart_port *port,
  994. struct s3c24xx_uart_clksrc *clk)
  995. {
  996. unsigned long ucon = rd_regl(port, S3C2410_UCON);
  997. if (strcmp(clk->name, "uclk") == 0)
  998. ucon |= S3C2410_UCON_UCLK;
  999. else
  1000. ucon &= ~S3C2410_UCON_UCLK;
  1001. wr_regl(port, S3C2410_UCON, ucon);
  1002. return 0;
  1003. }
  1004. static int s3c2410_serial_getsource(struct uart_port *port,
  1005. struct s3c24xx_uart_clksrc *clk)
  1006. {
  1007. unsigned long ucon = rd_regl(port, S3C2410_UCON);
  1008. clk->divisor = 1;
  1009. clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
  1010. return 0;
  1011. }
  1012. static int s3c2410_serial_resetport(struct uart_port *port,
  1013. struct s3c2410_uartcfg *cfg)
  1014. {
  1015. dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
  1016. port, port->mapbase, cfg);
  1017. wr_regl(port, S3C2410_UCON, cfg->ucon);
  1018. wr_regl(port, S3C2410_ULCON, cfg->ulcon);
  1019. /* reset both fifos */
  1020. wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
  1021. wr_regl(port, S3C2410_UFCON, cfg->ufcon);
  1022. return 0;
  1023. }
  1024. static struct s3c24xx_uart_info s3c2410_uart_inf = {
  1025. .name = "Samsung S3C2410 UART",
  1026. .type = PORT_S3C2410,
  1027. .fifosize = 16,
  1028. .rx_fifomask = S3C2410_UFSTAT_RXMASK,
  1029. .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
  1030. .rx_fifofull = S3C2410_UFSTAT_RXFULL,
  1031. .tx_fifofull = S3C2410_UFSTAT_TXFULL,
  1032. .tx_fifomask = S3C2410_UFSTAT_TXMASK,
  1033. .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
  1034. .get_clksrc = s3c2410_serial_getsource,
  1035. .set_clksrc = s3c2410_serial_setsource,
  1036. .reset_port = s3c2410_serial_resetport,
  1037. };
  1038. /* device management */
  1039. static int s3c2410_serial_probe(struct platform_device *dev)
  1040. {
  1041. return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
  1042. }
  1043. static struct platform_driver s3c2410_serial_drv = {
  1044. .probe = s3c2410_serial_probe,
  1045. .remove = s3c24xx_serial_remove,
  1046. .suspend = s3c24xx_serial_suspend,
  1047. .resume = s3c24xx_serial_resume,
  1048. .driver = {
  1049. .name = "s3c2410-uart",
  1050. .owner = THIS_MODULE,
  1051. },
  1052. };
  1053. static inline int s3c2410_serial_init(void)
  1054. {
  1055. return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
  1056. }
  1057. static inline void s3c2410_serial_exit(void)
  1058. {
  1059. platform_driver_unregister(&s3c2410_serial_drv);
  1060. }
  1061. #define s3c2410_uart_inf_at &s3c2410_uart_inf
  1062. #else
  1063. static inline int s3c2410_serial_init(void)
  1064. {
  1065. return 0;
  1066. }
  1067. static inline void s3c2410_serial_exit(void)
  1068. {
  1069. }
  1070. #define s3c2410_uart_inf_at NULL
  1071. #endif /* CONFIG_CPU_S3C2410 */
  1072. #if defined(CONFIG_CPU_S3C2440)||defined(CONFIG_CPU_S3C2442)||defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1073. static int s3c2440_serial_setsource(struct uart_port *port,
  1074. struct s3c24xx_uart_clksrc *clk)
  1075. {
  1076. unsigned long ucon = rd_regl(port, S3C2410_UCON);
  1077. // todo - proper fclk<>nonfclk switch //
  1078. ucon &= ~S3C2440_UCON_CLKMASK;
  1079. if (strcmp(clk->name, "uclk") == 0)
  1080. ucon |= S3C2440_UCON_UCLK;
  1081. else if (strcmp(clk->name, "pclk") == 0)
  1082. ucon |= S3C2440_UCON_PCLK;
  1083. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1084. else if (strcmp(clk->name, "esysclk") == 0)
  1085. #else
  1086. else if (strcmp(clk->name, "fclk") == 0)
  1087. #endif
  1088. ucon |= S3C2440_UCON_FCLK;
  1089. else {
  1090. printk(KERN_ERR "unknown clock source %s\n", clk->name);
  1091. return -EINVAL;
  1092. }
  1093. wr_regl(port, S3C2410_UCON, ucon);
  1094. return 0;
  1095. }
  1096. static int s3c2440_serial_getsource(struct uart_port *port,
  1097. struct s3c24xx_uart_clksrc *clk)
  1098. {
  1099. unsigned long ucon = rd_regl(port, S3C2410_UCON);
  1100. unsigned long ucon0, ucon1, ucon2;
  1101. switch (ucon & S3C2440_UCON_CLKMASK) {
  1102. case S3C2440_UCON_UCLK:
  1103. clk->divisor = 1;
  1104. clk->name = "uclk";
  1105. break;
  1106. case S3C2440_UCON_PCLK:
  1107. case S3C2440_UCON_PCLK2:
  1108. clk->divisor = 1;
  1109. clk->name = "pclk";
  1110. break;
  1111. case S3C2440_UCON_FCLK:
  1112. /* the fun of calculating the uart divisors on
  1113. * the s3c2440 */
  1114. ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
  1115. ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
  1116. ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
  1117. printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
  1118. ucon0 &= S3C2440_UCON0_DIVMASK;
  1119. ucon1 &= S3C2440_UCON1_DIVMASK;
  1120. ucon2 &= S3C2440_UCON2_DIVMASK;
  1121. if (ucon0 != 0) {
  1122. clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
  1123. clk->divisor += 6;
  1124. } else if (ucon1 != 0) {
  1125. clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
  1126. clk->divisor += 21;
  1127. } else if (ucon2 != 0) {
  1128. clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
  1129. clk->divisor += 36;
  1130. } else {
  1131. /* manual calims 44, seems to be 9 */
  1132. clk->divisor = 9;
  1133. }
  1134. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450) || defined(CONFIG_CPU_S3C2416)
  1135. clk->name = "esysclk";
  1136. #else
  1137. clk->name = "fclk";
  1138. #endif
  1139. break;
  1140. }
  1141. return 0;
  1142. }
  1143. static int s3c2440_serial_resetport(struct uart_port *port,
  1144. struct s3c2410_uartcfg *cfg)
  1145. {
  1146. unsigned long ucon = rd_regl(port, S3C2410_UCON);
  1147. dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
  1148. port, port->mapbase, cfg);
  1149. /* ensure we don't change the clock settings... */
  1150. ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
  1151. wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
  1152. wr_regl(port, S3C2410_ULCON, cfg->ulcon);
  1153. /* reset both fifos */
  1154. wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
  1155. wr_regl(port, S3C2410_UFCON, cfg->ufcon);
  1156. return 0;
  1157. }
  1158. static struct s3c24xx_uart_info s3c2440_uart_inf = {
  1159. .name = "Samsung S3C2440 UART",
  1160. .type = PORT_S3C2440,
  1161. .fifosize = 64,
  1162. .rx_fifomask = S3C2440_UFSTAT_RXMASK,
  1163. .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
  1164. .rx_fifofull = S3C2440_UFSTAT_RXFULL,
  1165. .tx_fifofull = S3C2440_UFSTAT_TXFULL,
  1166. .tx_fifomask = S3C2440_UFSTAT_TXMASK,
  1167. .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
  1168. .get_clksrc = s3c2440_serial_getsource,
  1169. .set_clksrc = s3c2440_serial_setsource,
  1170. .reset_port = s3c2440_serial_resetport,
  1171. };
  1172. /* device management */
  1173. static int s3c2440_serial_probe(struct platform_device *dev)
  1174. {
  1175. dbg("s3c2440_serial_probe: dev=%p\n", dev);
  1176. return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
  1177. }
  1178. static struct platform_driver s3c2440_serial_drv = {
  1179. .probe = s3c2440_serial_probe,
  1180. .remove = s3c24xx_serial_remove,
  1181. .suspend = s3c24xx_serial_suspend,
  1182. .resume = s3c24xx_serial_resume,
  1183. .driver = {
  1184. .name = "s3c2440-uart",
  1185. .owner = THIS_MODULE,
  1186. },
  1187. };
  1188. static inline int s3c2440_serial_init(void)
  1189. {
  1190. return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
  1191. }
  1192. static inline void s3c2440_serial_exit(void)
  1193. {
  1194. platform_driver_unregister(&s3c2440_serial_drv);
  1195. }
  1196. #define s3c2440_uart_inf_at &s3c2440_uart_inf
  1197. #else
  1198. static inline int s3c2440_serial_init(void)
  1199. {
  1200. return 0;
  1201. }
  1202. static inline void s3c2440_serial_exit(void)
  1203. {
  1204. }
  1205. #define s3c2440_uart_inf_at NULL
  1206. #endif /* CONFIG_CPU_S3C2440 */
  1207. #if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
  1208. static int s3c2412_serial_setsource(struct uart_port *port,
  1209. struct s3c24xx_uart_clksrc *clk)
  1210. {
  1211. unsigned long ucon = rd_regl(port, S3C2410_UCON);
  1212. ucon &= ~S3C2412_UCON_CLKMASK;
  1213. if (strcmp(clk->name, "uclk") == 0)
  1214. ucon |= S3C2440_UCON_UCLK;
  1215. else if (strcmp(clk->name, "pclk") == 0)
  1216. ucon |= S3C2440_UCON_PCLK;
  1217. else if (strcmp(clk->name, "usysclk") == 0)
  1218. ucon |= S3C2412_UCON_USYSCLK;
  1219. else {
  1220. printk(KERN_ERR "unknown clock source %s\n", clk->name);
  1221. return -EINVAL;
  1222. }
  1223. wr_regl(port, S3C2410_UCON, ucon);
  1224. return 0;
  1225. }
  1226. static int s3c2412_serial_getsource(struct uart_port *port,
  1227. struct s3c24xx_uart_clksrc *clk)
  1228. {
  1229. unsigned long ucon = rd_regl(port, S3C2410_UCON);
  1230. switch (ucon & S3C2412_UCON_CLKMASK) {
  1231. case S3C2412_UCON_UCLK:
  1232. clk->divisor = 1;
  1233. clk->name = "uclk";
  1234. break;
  1235. case S3C2412_UCON_PCLK:
  1236. case S3C2412_UCON_PCLK2:
  1237. clk->divisor = 1;
  1238. clk->name = "pclk";
  1239. break;
  1240. case S3C2412_UCON_USYSCLK:
  1241. clk->divisor = 1;
  1242. clk->name = "usysclk";
  1243. break;
  1244. }
  1245. return 0;
  1246. }
  1247. static int s3c2412_serial_resetport(struct uart_port *port,
  1248. struct s3c2410_uartcfg *cfg)
  1249. {
  1250. unsigned long ucon = rd_regl(port, S3C2410_UCON);
  1251. dbg("%s: port=%p (%08lx), cfg=%p\n",
  1252. __FUNCTION__, port, port->mapbase, cfg);
  1253. /* ensure we don't change the clock settings... */
  1254. ucon &= S3C2412_UCON_CLKMASK;
  1255. wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
  1256. wr_regl(port, S3C2410_ULCON, cfg->ulcon);
  1257. /* reset both fifos */
  1258. wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
  1259. wr_regl(port, S3C2410_UFCON, cfg->ufcon);
  1260. return 0;
  1261. }
  1262. static struct s3c24xx_uart_info s3c2412_uart_inf = {
  1263. .name = "Samsung S3C2412 UART",
  1264. .type = PORT_S3C2412,
  1265. .fifosize = 64,
  1266. .rx_fifomask = S3C2440_UFSTAT_RXMASK,
  1267. .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
  1268. .rx_fifofull = S3C2440_UFSTAT_RXFULL,
  1269. .tx_fifofull = S3C2440_UFSTAT_TXFULL,
  1270. .tx_fifomask = S3C2440_UFSTAT_TXMASK,
  1271. .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
  1272. .get_clksrc = s3c2412_serial_getsource,
  1273. .set_clksrc = s3c2412_serial_setsource,
  1274. .reset_port = s3c2412_serial_resetport,
  1275. };
  1276. /* device management */
  1277. static int s3c2412_serial_probe(struct platform_device *dev)
  1278. {
  1279. dbg("s3c2440_serial_probe: dev=%p\n", dev);
  1280. return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
  1281. }
  1282. static struct platform_driver s3c2412_serial_drv = {
  1283. .probe = s3c2412_serial_probe,
  1284. .remove = s3c24xx_serial_remove,
  1285. .suspend = s3c24xx_serial_suspend,
  1286. .resume = s3c24xx_serial_resume,
  1287. .driver = {
  1288. .name = "s3c2412-uart",
  1289. .owner = THIS_MODULE,
  1290. },
  1291. };
  1292. static inline int s3c2412_serial_init(void)
  1293. {
  1294. return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
  1295. }
  1296. static inline void s3c2412_serial_exit(void)
  1297. {
  1298. platform_driver_unregister(&s3c2412_serial_drv);
  1299. }
  1300. #define s3c2412_uart_inf_at &s3c2412_uart_inf
  1301. #else
  1302. static inline int s3c2412_serial_init(void)
  1303. {
  1304. return 0;
  1305. }
  1306. static inline void s3c2412_serial_exit(void)
  1307. {
  1308. }
  1309. #define s3c2412_uart_inf_at NULL
  1310. #endif /* CONFIG_CPU_S3C2440 */
  1311. /* module initialisation code */
  1312. static int __init s3c24xx_serial_modinit(void)
  1313. {
  1314. int ret;
  1315. ret = uart_register_driver(&s3c24xx_uart_drv);
  1316. if (ret < 0) {
  1317. printk(KERN_ERR "failed to register UART driver\n");
  1318. return -1;
  1319. }
  1320. s3c2400_serial_init();
  1321. s3c2410_serial_init();
  1322. s3c2412_serial_init();
  1323. s3c2440_serial_init();
  1324. return 0;
  1325. }
  1326. static void __exit s3c24xx_serial_modexit(void)
  1327. {
  1328. s3c2400_serial_exit();
  1329. s3c2410_serial_exit();
  1330. s3c2412_serial_exit();
  1331. s3c2440_serial_exit();
  1332. uart_unregister_driver(&s3c24xx_uart_drv);
  1333. }
  1334. module_init(s3c24xx_serial_modinit);
  1335. module_exit(s3c24xx_serial_modexit);
  1336. /* Console code */
  1337. #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
  1338. static struct uart_port *cons_uart;
  1339. static int
  1340. s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
  1341. {
  1342. struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
  1343. unsigned long ufstat, utrstat;
  1344. if (ufcon & S3C2410_UFCON_FIFOMODE) {
  1345. /* fifo mode - check ammount of data in fifo registers... */
  1346. ufstat = rd_regl(port, S3C2410_UFSTAT);
  1347. return (ufstat & info->tx_fifofull) ? 0 : 1;
  1348. }
  1349. /* in non-fifo mode, we go and use the tx buffer empty */
  1350. utrstat = rd_regl(port, S3C2410_UTRSTAT);
  1351. return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
  1352. }
  1353. static void
  1354. s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
  1355. {
  1356. unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
  1357. while (!s3c24xx_serial_console_txrdy(port, ufcon))
  1358. barrier();
  1359. wr_regb(cons_uart, S3C2410_UTXH, ch);
  1360. }
  1361. static void
  1362. s3c24xx_serial_console_write(struct console *co, const char *s,
  1363. unsigned int count)
  1364. {
  1365. uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
  1366. }
  1367. static void __init
  1368. s3c24xx_serial_get_options(struct uart_port *port, int *baud,
  1369. int *parity, int *bits)
  1370. {
  1371. struct s3c24xx_uart_clksrc clksrc;
  1372. struct clk *clk;
  1373. unsigned int ulcon;
  1374. unsigned int ucon;
  1375. unsigned int ubrdiv;
  1376. unsigned long rate;
  1377. ulcon = rd_regl(port, S3C2410_ULCON);
  1378. ucon = rd_regl(port, S3C2410_UCON);
  1379. ubrdiv = rd_regl(port, S3C2410_UBRDIV);
  1380. dbg("s3c24xx_serial_get_options: port=%p\n"
  1381. "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
  1382. port, ulcon, ucon, ubrdiv);
  1383. if ((ucon & 0xf) != 0) {
  1384. /* consider the serial port configured if the tx/rx mode set */
  1385. switch (ulcon & S3C2410_LCON_CSMASK) {
  1386. case S3C2410_LCON_CS5:
  1387. *bits = 5;
  1388. break;
  1389. case S3C2410_LCON_CS6:
  1390. *bits = 6;
  1391. break;
  1392. case S3C2410_LCON_CS7:
  1393. *bits = 7;
  1394. break;
  1395. default:
  1396. case S3C2410_LCON_CS8:
  1397. *bits = 8;
  1398. break;
  1399. }
  1400. switch (ulcon & S3C2410_LCON_PMASK) {
  1401. case S3C2410_LCON_PEVEN:
  1402. *parity = 'e';
  1403. break;
  1404. case S3C2410_LCON_PODD:
  1405. *parity = 'o';
  1406. break;
  1407. case S3C2410_LCON_PNONE:
  1408. default:
  1409. *parity = 'n';
  1410. }
  1411. /* now calculate the baud rate */
  1412. s3c24xx_serial_getsource(port, &clksrc);
  1413. clk = clk_get(port->dev, clksrc.name);
  1414. if (!IS_ERR(clk) && clk != NULL)
  1415. rate = clk_get_rate(clk) / clksrc.divisor;
  1416. else
  1417. rate = 1;
  1418. *baud = rate / ( 16 * (ubrdiv + 1));
  1419. dbg("calculated baud %d\n", *baud);
  1420. }
  1421. }
  1422. /* s3c24xx_serial_init_ports
  1423. *
  1424. * initialise the serial ports from the machine provided initialisation
  1425. * data.
  1426. */
  1427. static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
  1428. {
  1429. struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
  1430. struct platform_device **platdev_ptr;
  1431. int i;
  1432. dbg("s3c24xx_serial_init_ports: initialising ports...\n");
  1433. platdev_ptr = s3c24xx_uart_devs;
  1434. for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
  1435. s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
  1436. }
  1437. return 0;
  1438. }
  1439. static int __init
  1440. s3c24xx_serial_console_setup(struct console *co, char *options)
  1441. {
  1442. struct uart_port *port;
  1443. int baud = 9600;
  1444. int bits = 8;
  1445. int parity = 'n';
  1446. int flow = 'n';
  1447. dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
  1448. co, co->index, options);
  1449. /* is this a valid port */
  1450. if (co->index == -1 || co->index >= NR_PORTS)
  1451. co->index = 0;
  1452. port = &s3c24xx_serial_ports[co->index].port;
  1453. /* is the port configured? */
  1454. if (port->mapbase == 0x0) {
  1455. co->index = 0;
  1456. port = &s3c24xx_serial_ports[co->index].port;
  1457. }
  1458. cons_uart = port;
  1459. dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
  1460. /*
  1461. * Check whether an invalid uart number has been specified, and
  1462. * if so, search for the first available port that does have
  1463. * console support.
  1464. */
  1465. if (options)
  1466. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1467. else
  1468. s3c24xx_serial_get_options(port, &baud, &parity, &bits);
  1469. dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
  1470. return uart_set_options(port, co, baud, parity, bits, flow);
  1471. }
  1472. /* s3c24xx_serial_initconsole
  1473. *
  1474. * initialise the console from one of the uart drivers
  1475. */
  1476. static struct console s3c24xx_serial_console =
  1477. {
  1478. .name = S3C24XX_SERIAL_NAME,
  1479. .device = uart_console_device,
  1480. .flags = CON_PRINTBUFFER,
  1481. .index = -1,
  1482. .write = s3c24xx_serial_console_write,
  1483. .setup = s3c24xx_serial_console_setup
  1484. };
  1485. static int s3c24xx_serial_initconsole(void)
  1486. {
  1487. struct s3c24xx_uart_info *info;
  1488. struct platform_device *dev = s3c24xx_uart_devs[0];
  1489. dbg("s3c24xx_serial_initconsole\n");
  1490. /* select driver based on the cpu */
  1491. if (dev == NULL) {
  1492. printk(KERN_ERR "s3c24xx: no devices for console init\n");
  1493. return 0;
  1494. }
  1495. if (strcmp(dev->name, "s3c2400-uart") == 0) {
  1496. info = s3c2400_uart_inf_at;
  1497. } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
  1498. info = s3c2410_uart_inf_at;
  1499. } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
  1500. info = s3c2440_uart_inf_at;
  1501. } else if (strcmp(dev->name, "s3c2412-uart") == 0) {
  1502. info = s3c2412_uart_inf_at;
  1503. } else {
  1504. printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
  1505. return 0;
  1506. }
  1507. if (info == NULL) {
  1508. printk(KERN_ERR "s3c24xx: no driver for console\n");
  1509. return 0;
  1510. }
  1511. s3c24xx_serial_console.data = &s3c24xx_uart_drv;
  1512. s3c24xx_serial_init_ports(info);
  1513. register_console(&s3c24xx_serial_console);
  1514. return 0;
  1515. }
  1516. console_initcall(s3c24xx_serial_initconsole);
  1517. #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
  1518. MODULE_LICENSE("GPL");
  1519. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
  1520. MODULE_DESCRIPTION("Samsung S3C2410/S3C2440/S3C2412 Serial port driver");