mach-smdk2416.c 11 KB

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  1. /* linux/arch/arm/mach-s3c2416/mach-smdk2416.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. * Ryu Euiyoul <ryu.real@gmail.com>
  6. *
  7. * http://www.fluff.org/ben/smdk2443/
  8. *
  9. * Thanks to Samsung for the loan of an SMDK2416
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. *
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/types.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/list.h>
  20. #include <linux/timer.h>
  21. #include <linux/init.h>
  22. #include <linux/serial_core.h>
  23. #include <linux/platform_device.h>
  24. #include <asm/mach/arch.h>
  25. #include <asm/mach/map.h>
  26. #include <asm/mach/irq.h>
  27. #include <asm/setup.h>
  28. #include <asm/hardware.h>
  29. #include <asm/io.h>
  30. #include <asm/irq.h>
  31. #include <asm/mach-types.h>
  32. #include <asm/arch/regs-serial.h>
  33. #include <asm/arch/regs-gpio.h>
  34. #include <asm/arch/regs-gpioj.h>
  35. #include <asm/arch/regs-lcd.h>
  36. #include <asm/arch/regs-mem.h>
  37. #include <asm/arch/idle.h>
  38. #include <asm/arch/fb.h>
  39. #include <asm/plat-s3c24xx/s3c2410.h>
  40. #include <asm/plat-s3c24xx/s3c2440.h>
  41. #include <asm/plat-s3c24xx/clock.h>
  42. #include <asm/plat-s3c24xx/devs.h>
  43. #include <asm/plat-s3c24xx/cpu.h>
  44. #include <asm/plat-s3c24xx/common-smdk.h>
  45. #include <asm/arch/nand.h>
  46. #include <linux/mtd/mtd.h>
  47. #include <linux/mtd/partitions.h>
  48. #include <asm/arch/hsmmc.h>
  49. static struct map_desc smdk2416_iodesc[] __initdata = {
  50. IODESC_ENT(CS8900),
  51. };
  52. #define UCON S3C2410_UCON_DEFAULT | S3C2440_UCON_FCLK
  53. #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  54. #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  55. static struct s3c24xx_uart_clksrc smdk2416_serial_clocks[] = {
  56. [0] = {
  57. .name = "pclk",
  58. .divisor = 1,
  59. .min_baud = 0,
  60. .max_baud = 0,
  61. },
  62. [1] = {
  63. .name = "esysclk",
  64. .divisor = 1,
  65. .min_baud = 0,
  66. .max_baud = 0,
  67. }
  68. };
  69. static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
  70. [0] = {
  71. .hwport = 0,
  72. .flags = 0,
  73. .ucon = 0x3c5,
  74. .ulcon = 0x03,
  75. .ufcon = 0x51,
  76. },
  77. [1] = {
  78. .hwport = 1,
  79. .flags = 0,
  80. /* Use PCLK */
  81. .ucon = 0x3c5,
  82. //.ucon = 0xfc5,
  83. .ulcon = 0x03,
  84. .ufcon = 0x51,
  85. #ifndef CONFIG_QISDA_BK060B00
  86. .clocks = smdk2416_serial_clocks,
  87. .clocks_size = ARRAY_SIZE(smdk2416_serial_clocks),
  88. #endif
  89. },
  90. /* IR port */
  91. [2] = {
  92. .hwport = 2,
  93. .flags = 0,
  94. .ucon = 0x3c5,
  95. // .ucon = 0xfc5,
  96. .ulcon = 0x03,
  97. // .ulcon = 0x43,
  98. .ufcon = 0x51,
  99. .clocks = smdk2416_serial_clocks,
  100. .clocks_size = ARRAY_SIZE(smdk2416_serial_clocks),
  101. }
  102. };
  103. static struct platform_device *smdk2416_devices[] __initdata = {
  104. &s3c_device_spi0,
  105. &s3c_device_spi1,
  106. &s3c_device_wdt,
  107. &s3c_device_i2c,
  108. &s3c_device_lcd,
  109. &s3c_device_rtc,
  110. &s3c_device_adc,
  111. &s3c_device_iis,
  112. &s3c_device_usbgadget,
  113. &s3c_device_usb,
  114. &s3c_device_hsmmc0,
  115. &s3c_device_hsmmc1,
  116. //Qisda Tony 090324, add keypad [
  117. &s3c_device_keypad_qisda,
  118. //Qisda Tony 090324, add keypad ]
  119. //Qisda Tony 090406, add Auo touch i2c driver [
  120. &s3c_device_ts_iic,
  121. //Qisda Tony 090406, add Auo touch i2c driver ]
  122. };
  123. static struct s3c24xx_board smdk2416_board __initdata = {
  124. .devices = smdk2416_devices,
  125. .devices_count = ARRAY_SIZE(smdk2416_devices)
  126. };
  127. static void __init smdk2416_map_io(void)
  128. {
  129. s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
  130. s3c24xx_init_clocks(12000000);
  131. s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
  132. s3c24xx_set_board(&smdk2416_board);
  133. }
  134. static void smdk2416_cs89x0_set(void)
  135. {
  136. u32 val;
  137. val = readl(S3C_BANK_CFG);
  138. val &= ~((1<<8)|(1<<9)|(1<<10));
  139. writel(val, S3C_BANK_CFG);
  140. /* Bank1 Idle cycle ctrl. */
  141. writel(0xf, S3C_SSMC_SMBIDCYR1);
  142. /* Bank1 Read Wait State cont. = 14 clk Tacc? */
  143. writel(12, S3C_SSMC_SMBWSTRDR1);
  144. /* Bank1 Write Wait State ctrl. */
  145. writel(12, S3C_SSMC_SMBWSTWRR1);
  146. /* Bank1 Output Enable Assertion Delay ctrl. Tcho? */
  147. writel(2, S3C_SSMC_SMBWSTOENR1);
  148. /* Bank1 Write Enable Assertion Delay ctrl. */
  149. writel(2, S3C_SSMC_SMBWSTWENR1);
  150. /* SMWAIT active High, Read Byte Lane Enabl WS1? */
  151. val = readl(S3C_SSMC_SMBCR1);
  152. val |= ((1<<15)|(1<<7));
  153. writel(val, S3C_SSMC_SMBCR1);
  154. val = readl(S3C_SSMC_SMBCR1);
  155. val |= ((1<<2)|(1<<0));
  156. writel(val, S3C_SSMC_SMBCR1);
  157. val = readl(S3C_SSMC_SMBCR1);
  158. val &= ~((3<<20)|(3<<12));
  159. writel(val, S3C_SSMC_SMBCR1);
  160. val = readl(S3C_SSMC_SMBCR1);
  161. val &= ~(3<<4);
  162. writel(val, S3C_SSMC_SMBCR1);
  163. val = readl(S3C_SSMC_SMBCR1);
  164. val |= (1<<4);
  165. writel(val, S3C_SSMC_SMBCR1);
  166. }
  167. /* Qisda Mark Tsai, 2010/01/13 { */
  168. static void smdk2416_power_off(void)
  169. {
  170. printk("[smdk2416_power_off]T-CON Off\n");
  171. if(is_Epaper_Write_Ready())
  172. {
  173. //AUO T-CON Standby
  174. msleep(100);
  175. Epaper_Enter_Standby_Mode(1);
  176. msleep(100);
  177. //AUO T-CON Sleep
  178. Epaper_Enter_Sleep_Mode(1);
  179. msleep(5);
  180. //Shutdown T-CON Power
  181. Epaper_Power(0);
  182. //Shutdown i80 of s3c
  183. EPaper_CloseLcdPort();
  184. //msleep(1000);
  185. //u32PowerState = EN_EPD_DEVICE_POWER_STATE_D3;
  186. }
  187. printk("[smdk2416_power_off]Power Off\n");
  188. writeb(0x0, 0xc8a30029);
  189. msleep(100);
  190. #ifdef CONFIG_QISDA_BK060B00
  191. s3c2410_gpio_cfgpin(S3C2410_GPD14, S3C2410_GPG14_OUTP);
  192. s3c2410_gpio_setpin(S3C2410_GPG14, 0);
  193. #else
  194. s3c2410_gpio_cfgpin(S3C2410_GPG0, S3C2410_GPG0_OUTP);
  195. s3c2410_gpio_setpin(S3C2410_GPG0, 0);
  196. #endif
  197. }
  198. /* Qisda Mark Tsai, 2010/01/13 } */
  199. static void __init smdk2416_machine_init(void)
  200. {
  201. /* SROM init for NFS */
  202. smdk2416_cs89x0_set();
  203. smdk_machine_init();
  204. /* Qisda Mark Tsai, 2010/01/13 { */
  205. pm_power_off = smdk2416_power_off;
  206. /* Qisda Mark Tsai, 2010/01/13 } */
  207. }
  208. static void __init smdk2416_fixup (struct machine_desc *desc, struct tag *tags,
  209. char **cmdline, struct meminfo *mi)
  210. {
  211. /*
  212. * Bank start addresses are not present in the information
  213. * passed in from the boot loader. We could potentially
  214. * detect them, but instead we hard-code them.
  215. */
  216. mi->bank[0].start = 0x30000000;
  217. #if defined(CONFIG_VIDEO_SAMSUNG)
  218. mi->bank[0].size = 49*1024*1024;
  219. #elif defined(CONFIG_PP_S3C2443)
  220. mi->bank[0].size = 60*1024*1024;
  221. #else
  222. /*Qisda Qube for 128MB*/
  223. #if defined(CONFIG_QISDA_E600_EVT2) || defined(CONFIG_QISDA_AS090B00_EVT1) || defined (CONFIG_QISDA_AS090B00_EVT1_1) || defined (CONFIG_QISDA_QD060N00_DVT1_1) ||defined (CONFIG_QISDA_L600) || defined (CONFIG_QISDA_QD090B00_EVT1)
  224. mi->bank[0].size = 128*1024*1024;
  225. #else
  226. mi->bank[0].size = 64*1024*1024;
  227. #endif
  228. /*Qisda Qube for 128MB*/
  229. #endif
  230. mi->bank[0].node = 0;
  231. mi->nr_banks = 1;
  232. }
  233. MACHINE_START(SMDK2416, "SMDK2416")
  234. /* Maintainer: Ben Dooks <ben@fluff.org> */
  235. .phys_io = S3C2410_PA_UART,
  236. .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
  237. .boot_params = S3C2410_SDRAM_PA + 0x100,
  238. .init_irq = s3c24xx_init_irq,
  239. .map_io = smdk2416_map_io,
  240. .fixup = smdk2416_fixup,
  241. .init_machine = smdk2416_machine_init,
  242. .timer = &s3c24xx_timer,
  243. MACHINE_END
  244. /*
  245. * HS-MMC GPIO Set function for S3C2416 SMDK board
  246. */
  247. void hsmmc_set_gpio (uint channel, uint width)
  248. {
  249. switch (channel) {
  250. /* can supports 1 and 4 bit bus */
  251. case 0:
  252. /* GPIO E : Command, Clock */
  253. s3c2410_gpio_cfgpin(S3C2410_GPE5, S3C2450_GPE5_SD0_CLK);
  254. s3c2410_gpio_cfgpin(S3C2410_GPE6, S3C2450_GPE6_SD0_CMD);
  255. if (width == 1) {
  256. /* GPIO E : MMC DATA0[0] */
  257. s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
  258. }
  259. else if (width == 4) {
  260. /* GPIO E : MMC DATA0[0:3] */
  261. s3c2410_gpio_cfgpin(S3C2410_GPE7, S3C2450_GPE7_SD0_DAT0);
  262. s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2450_GPE8_SD0_DAT1);
  263. s3c2410_gpio_cfgpin(S3C2410_GPE9, S3C2450_GPE9_SD0_DAT2);
  264. s3c2410_gpio_cfgpin(S3C2410_GPE10, S3C2450_GPE10_SD0_DAT3);
  265. }
  266. break;
  267. /* can supports 1, 4, and 8 bit bus */
  268. case 1:
  269. /* GPIO L : Command, Clock */
  270. s3c2410_gpio_cfgpin(S3C2443_GPL8, S3C2450_GPL8_SD1CMD);
  271. s3c2410_gpio_cfgpin(S3C2443_GPL9, S3C2450_GPL9_SD1CLK);
  272. /* GPIO J : Chip detect, LED, Write Protect */
  273. s3c2410_gpio_cfgpin(S3C2443_GPJ13, S3C2450_GPJ13_SD1LED);
  274. s3c2410_gpio_cfgpin(S3C2443_GPJ14, S3C2450_GPJ14_nSD1CD);
  275. s3c2410_gpio_cfgpin(S3C2443_GPJ15, S3C2450_GPJ15_nSD1WP); /* write protect enable */
  276. s3c2410_gpio_setpin(S3C2443_GPJ15, 1);
  277. if (width == 1) {
  278. /* GPIO L : MMC DATA1[0] */
  279. s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
  280. }
  281. else if (width == 4) {
  282. /* GPIO L : MMC DATA1[0:3] */
  283. s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
  284. s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
  285. s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
  286. s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
  287. }
  288. else if (width == 8) {
  289. /* GPIO L : MMC DATA1[0:7] */
  290. s3c2410_gpio_cfgpin(S3C2443_GPL0, S3C2450_GPL0_SD1DAT0);
  291. s3c2410_gpio_cfgpin(S3C2443_GPL1, S3C2450_GPL1_SD1DAT1);
  292. s3c2410_gpio_cfgpin(S3C2443_GPL2, S3C2450_GPL2_SD1DAT2);
  293. s3c2410_gpio_cfgpin(S3C2443_GPL3, S3C2450_GPL3_SD1DAT3);
  294. s3c2410_gpio_cfgpin(S3C2443_GPL4, S3C2450_GPL4_SD1DAT4);
  295. s3c2410_gpio_cfgpin(S3C2443_GPL5, S3C2450_GPL5_SD1DAT5);
  296. s3c2410_gpio_cfgpin(S3C2443_GPL6, S3C2450_GPL6_SD1DAT6);
  297. s3c2410_gpio_cfgpin(S3C2443_GPL7, S3C2450_GPL7_SD1DAT7);
  298. }
  299. break;
  300. default:
  301. break;
  302. }
  303. }
  304. EXPORT_SYMBOL_GPL(hsmmc_set_gpio);
  305. #define HOST_CAPS (MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | \
  306. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED)
  307. /* Channel 0 : added HS-MMC channel */
  308. struct s3c_hsmmc_cfg s3c_hsmmc0_platform = {
  309. .hwport = 0,
  310. .enabled = 1,
  311. /* BAN 20090608 update for wifi driver fail*/
  312. //.host_caps = HOST_CAPS,
  313. .host_caps = 0xF ,
  314. /* BAN 20090608 update for wifi driver fail*/
  315. .bus_width = 4,
  316. .highspeed = 0,
  317. /* ctrl for mmc */
  318. .fd_ctrl[MMC_MODE_MMC] = {
  319. .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
  320. .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
  321. .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
  322. .ctrl4 = 0x3,
  323. },
  324. /* ctrl for sd */
  325. .fd_ctrl[MMC_MODE_SD] = {
  326. .ctrl2 = 0xC0000100, /* ctrl2 for sd */
  327. .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
  328. .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
  329. .ctrl4 = 0x3,
  330. },
  331. .clk_name[0] = "hsmmc", /* 1st clock source */
  332. .clk_name[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
  333. .clk_name[2] = "hsmmc-ext", /* 3rd clock source */
  334. };
  335. /* Channel 1 : default HS-MMC channel */
  336. struct s3c_hsmmc_cfg s3c_hsmmc1_platform = {
  337. .hwport = 1,
  338. .enabled = 1,
  339. /* BAN 20090608 update for wifi driver fail*/
  340. //.host_caps = HOST_CAPS , /* GeorgeKuo_modify| MMC_CAP_8_BIT_DATA,*/
  341. .host_caps = 0xF ,
  342. /* BAN 20090608 update for wifi driver fail*/
  343. .bus_width = 8,
  344. .highspeed = 0,
  345. /* ctrl for mmc */
  346. .fd_ctrl[MMC_MODE_MMC] = {
  347. .ctrl2 = 0xC0000100, /* ctrl2 for mmc */
  348. .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
  349. .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
  350. .ctrl4 = 0x3,
  351. },
  352. /* ctrl for sd */
  353. .fd_ctrl[MMC_MODE_SD] = {
  354. .ctrl2 = 0xC0000100, /* ctrl2 for sd */
  355. .ctrl3[SPEED_NORMAL] = 0, /* ctrl3 for low speed */
  356. .ctrl3[SPEED_HIGH] = 0, /* ctrl3 for high speed */
  357. .ctrl4 = 0x3,
  358. },
  359. .clk_name[0] = "hsmmc", /* 1st clock source */
  360. .clk_name[1] = "esysclk", /* 2nd clock source hsmmc-epll by Ben Dooks */
  361. .clk_name[2] = "hsmmc-ext", /* 3rd clock source */
  362. };