clock.c 24 KB

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  1. /* linux/arch/arm/mach-s3c2416/clock.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. * Ryu Euiyoul <ryu.real@gmail.com>
  6. *
  7. * S3C2416 Clock control support
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. */
  23. #include <linux/init.h>
  24. #include <linux/module.h>
  25. #include <linux/kernel.h>
  26. #include <linux/list.h>
  27. #include <linux/errno.h>
  28. #include <linux/err.h>
  29. #include <linux/sysdev.h>
  30. #include <linux/clk.h>
  31. #include <linux/mutex.h>
  32. #include <linux/delay.h>
  33. #include <linux/serial_core.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/hardware.h>
  36. #include <asm/io.h>
  37. #include <asm/arch/regs-s3c2416-clock.h>
  38. #include <asm/plat-s3c24xx/s3c2416.h>
  39. #include <asm/plat-s3c24xx/clock.h>
  40. #include <asm/plat-s3c24xx/cpu.h>
  41. /* We currently have to assume that the system is running
  42. * from the XTPll input, and that all ***REFCLKs are being
  43. * fed from it, as we cannot read the state of OM[4] from
  44. * software.
  45. *
  46. * It would be possible for each board initialisation to
  47. * set the correct muxing at initialisation
  48. */
  49. static int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
  50. {
  51. unsigned int clocks = clk->ctrlbit;
  52. unsigned long clkcon;
  53. clkcon = __raw_readl(S3C2443_HCLKCON);
  54. if (enable)
  55. clkcon |= clocks;
  56. else
  57. clkcon &= ~clocks;
  58. __raw_writel(clkcon, S3C2443_HCLKCON);
  59. return 0;
  60. }
  61. static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
  62. {
  63. unsigned int clocks = clk->ctrlbit;
  64. unsigned long clkcon;
  65. clkcon = __raw_readl(S3C2443_PCLKCON);
  66. if (enable)
  67. clkcon |= clocks;
  68. else
  69. clkcon &= ~clocks;
  70. __raw_writel(clkcon, S3C2443_HCLKCON);
  71. return 0;
  72. }
  73. static int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
  74. {
  75. unsigned int clocks = clk->ctrlbit;
  76. unsigned long clkcon;
  77. clkcon = __raw_readl(S3C2443_SCLKCON);
  78. if (enable)
  79. clkcon |= clocks;
  80. else
  81. clkcon &= ~clocks;
  82. __raw_writel(clkcon, S3C2443_SCLKCON);
  83. return 0;
  84. }
  85. static unsigned long s3c2443_roundrate_clksrc(struct clk *clk,
  86. unsigned long rate,
  87. unsigned int max)
  88. {
  89. unsigned long parent_rate = clk_get_rate(clk->parent);
  90. int div;
  91. if (rate > parent_rate)
  92. return parent_rate;
  93. /* note, we remove the +/- 1 calculations as they cancel out */
  94. div = (rate / parent_rate);
  95. if (div < 1)
  96. div = 1;
  97. else if (div > max)
  98. div = max;
  99. return parent_rate / div;
  100. }
  101. static unsigned long s3c2443_roundrate_clksrc4(struct clk *clk,
  102. unsigned long rate)
  103. {
  104. return s3c2443_roundrate_clksrc(clk, rate, 4);
  105. }
  106. static unsigned long s3c2443_roundrate_clksrc16(struct clk *clk,
  107. unsigned long rate)
  108. {
  109. return s3c2443_roundrate_clksrc(clk, rate, 16);
  110. }
  111. static unsigned long s3c2443_roundrate_clksrc256(struct clk *clk,
  112. unsigned long rate)
  113. {
  114. return s3c2443_roundrate_clksrc(clk, rate, 256);
  115. }
  116. /* clock selections */
  117. /* CPU EXTCLK input */
  118. static struct clk clk_ext = {
  119. .name = "ext",
  120. .id = -1,
  121. };
  122. static struct clk clk_mpllref = {
  123. .name = "mpllref",
  124. .parent = &clk_xtal,
  125. .id = -1,
  126. };
  127. #if 0
  128. static struct clk clk_mpll = {
  129. .name = "mpll",
  130. .parent = &clk_mpllref,
  131. .id = -1,
  132. };
  133. #endif
  134. static struct clk clk_epllref;
  135. static struct clk clk_epll = {
  136. .name = "epll",
  137. .parent = &clk_epllref,
  138. .id = -1,
  139. };
  140. static struct clk clk_i2s_ext = {
  141. .name = "i2s-ext",
  142. .id = -1,
  143. };
  144. static int s3c2443_setparent_epllref(struct clk *clk, struct clk *parent)
  145. {
  146. unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
  147. clksrc &= ~S3C2443_CLKSRC_EPLLREF_MASK;
  148. if (parent == &clk_xtal)
  149. clksrc |= S3C2443_CLKSRC_EPLLREF_XTAL;
  150. else if (parent == &clk_ext)
  151. clksrc |= S3C2443_CLKSRC_EPLLREF_EXTCLK;
  152. else if (parent != &clk_mpllref)
  153. return -EINVAL;
  154. __raw_writel(clksrc, S3C2443_CLKSRC);
  155. clk->parent = parent;
  156. return 0;
  157. }
  158. static struct clk clk_epllref = {
  159. .name = "epllref",
  160. .id = -1,
  161. .set_parent = s3c2443_setparent_epllref,
  162. };
  163. static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
  164. {
  165. unsigned long parent_rate = clk_get_rate(clk->parent);
  166. unsigned long div = __raw_readl(S3C2443_CLKDIV0);
  167. div &= S3C2443_CLKDIV0_EXTDIV_MASK;
  168. div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1); /* x2 */
  169. return parent_rate / (div + 1);
  170. }
  171. static struct clk clk_mdivclk = {
  172. .name = "mdivclk",
  173. .parent = &clk_mpllref,
  174. .id = -1,
  175. .get_rate = s3c2443_getrate_mdivclk,
  176. };
  177. static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
  178. {
  179. unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
  180. clksrc &= ~(S3C2443_CLKSRC_MSYSCLK_MPLL |
  181. S3C2443_CLKSRC_EXTCLK_DIV);
  182. if (parent == &clk_mpll)
  183. clksrc |= S3C2443_CLKSRC_MSYSCLK_MPLL;
  184. else if (parent == &clk_mdivclk)
  185. clksrc |= S3C2443_CLKSRC_EXTCLK_DIV;
  186. else if (parent != &clk_mpllref)
  187. return -EINVAL;
  188. __raw_writel(clksrc, S3C2443_CLKSRC);
  189. clk->parent = parent;
  190. return 0;
  191. }
  192. static struct clk clk_msysclk = {
  193. .name = "msysclk",
  194. .parent = &clk_xtal,
  195. .id = -1,
  196. .set_parent = s3c2443_setparent_msysclk,
  197. };
  198. /* esysclk
  199. *
  200. * this is sourced from either the EPLL or the EPLLref clock
  201. */
  202. static int s3c2443_setparent_esysclk(struct clk *clk, struct clk *parent)
  203. {
  204. unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
  205. if (parent == &clk_epll)
  206. clksrc |= S3C2443_CLKSRC_ESYSCLK_EPLL;
  207. else if (parent == &clk_epllref)
  208. clksrc &= ~S3C2443_CLKSRC_ESYSCLK_EPLL;
  209. else
  210. return -EINVAL;
  211. __raw_writel(clksrc, S3C2443_CLKSRC);
  212. clk->parent = parent;
  213. return 0;
  214. }
  215. static struct clk clk_esysclk = {
  216. .name = "esysclk",
  217. .parent = &clk_epll,
  218. .id = -1,
  219. .set_parent = s3c2443_setparent_esysclk,
  220. };
  221. /* uartclk
  222. *
  223. * UART baud-rate clock sourced from esysclk via a divisor
  224. */
  225. static unsigned long s3c2443_getrate_uart(struct clk *clk)
  226. {
  227. unsigned long parent_rate = clk_get_rate(clk->parent);
  228. unsigned long div = __raw_readl(S3C2443_CLKDIV1);
  229. div &= S3C2443_CLKDIV1_UARTDIV_MASK;
  230. div >>= S3C2443_CLKDIV1_UARTDIV_SHIFT;
  231. return parent_rate / (div + 1);
  232. }
  233. static int s3c2443_setrate_uart(struct clk *clk, unsigned long rate)
  234. {
  235. unsigned long parent_rate = clk_get_rate(clk->parent);
  236. unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
  237. rate = s3c2443_roundrate_clksrc16(clk, rate);
  238. rate = parent_rate / rate;
  239. clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
  240. clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
  241. __raw_writel(clkdivn, S3C2443_CLKDIV1);
  242. return 0;
  243. }
  244. static struct clk clk_uart = {
  245. .name = "uartclk",
  246. .id = -1,
  247. .parent = &clk_esysclk,
  248. .get_rate = s3c2443_getrate_uart,
  249. .set_rate = s3c2443_setrate_uart,
  250. .round_rate = s3c2443_roundrate_clksrc16,
  251. };
  252. /* hsspi
  253. *
  254. * high-speed spi clock, sourced from esysclk
  255. */
  256. static unsigned long s3c2443_getrate_hsspi(struct clk *clk)
  257. {
  258. unsigned long parent_rate = clk_get_rate(clk->parent);
  259. unsigned long div = __raw_readl(S3C2443_CLKDIV1);
  260. div &= S3C2443_CLKDIV1_HSSPIDIV_MASK;
  261. div >>= S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
  262. return parent_rate / (div + 1);
  263. }
  264. static int s3c2443_setrate_hsspi(struct clk *clk, unsigned long rate)
  265. {
  266. unsigned long parent_rate = clk_get_rate(clk->parent);
  267. unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
  268. rate = s3c2443_roundrate_clksrc4(clk, rate);
  269. rate = parent_rate / rate;
  270. clkdivn &= ~S3C2443_CLKDIV1_HSSPIDIV_MASK;
  271. clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSSPIDIV_SHIFT;
  272. __raw_writel(clkdivn, S3C2443_CLKDIV1);
  273. return 0;
  274. }
  275. static struct clk clk_hsspi = {
  276. .name = "hsspi",
  277. .id = -1,
  278. .parent = &clk_esysclk,
  279. .ctrlbit = S3C2443_SCLKCON_HSSPICLK,
  280. .enable = s3c2443_clkcon_enable_s,
  281. .get_rate = s3c2443_getrate_hsspi,
  282. .set_rate = s3c2443_setrate_hsspi,
  283. .round_rate = s3c2443_roundrate_clksrc4,
  284. };
  285. /* usbhost
  286. *
  287. * usb host bus-clock, usually 48MHz to provide USB bus clock timing
  288. */
  289. static unsigned long s3c2443_getrate_usbhost(struct clk *clk)
  290. {
  291. unsigned long parent_rate = clk_get_rate(clk->parent);
  292. unsigned long div = __raw_readl(S3C2443_CLKDIV1);
  293. div &= S3C2443_CLKDIV1_USBHOSTDIV_MASK;
  294. div >>= S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
  295. return parent_rate / (div + 1);
  296. }
  297. static int s3c2443_setrate_usbhost(struct clk *clk, unsigned long rate)
  298. {
  299. unsigned long parent_rate = clk_get_rate(clk->parent);
  300. unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
  301. rate = s3c2443_roundrate_clksrc4(clk, rate);
  302. rate = parent_rate / rate;
  303. clkdivn &= ~S3C2443_CLKDIV1_USBHOSTDIV_MASK;
  304. clkdivn |= (rate - 1) << S3C2443_CLKDIV1_USBHOSTDIV_SHIFT;
  305. __raw_writel(clkdivn, S3C2443_CLKDIV1);
  306. return 0;
  307. }
  308. struct clk clk_usb_bus_host = {
  309. .name = "usb-bus-host-parent",
  310. .id = -1,
  311. .parent = &clk_esysclk,
  312. .ctrlbit = S3C2443_SCLKCON_USBHOST,
  313. .enable = s3c2443_clkcon_enable_s,
  314. .get_rate = s3c2443_getrate_usbhost,
  315. .set_rate = s3c2443_setrate_usbhost,
  316. .round_rate = s3c2443_roundrate_clksrc4,
  317. };
  318. /* clk_hsmcc_div
  319. *
  320. * this clock is sourced from epll, and is fed through a divider,
  321. * to a mux controlled by sclkcon where either it or a extclk can
  322. * be fed to the hsmmc block
  323. */
  324. static unsigned long s3c2443_getrate_hsmmc_div(struct clk *clk)
  325. {
  326. unsigned long parent_rate = clk_get_rate(clk->parent);
  327. unsigned long div = __raw_readl(S3C2443_CLKDIV1);
  328. div &= S3C2443_CLKDIV1_HSMMCDIV_MASK;
  329. div >>= S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
  330. return parent_rate / (div + 1);
  331. }
  332. static int s3c2443_setrate_hsmmc_div(struct clk *clk, unsigned long rate)
  333. {
  334. unsigned long parent_rate = clk_get_rate(clk->parent);
  335. unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
  336. rate = s3c2443_roundrate_clksrc4(clk, rate);
  337. rate = parent_rate / rate;
  338. clkdivn &= ~S3C2443_CLKDIV1_HSMMCDIV_MASK;
  339. clkdivn |= (rate - 1) << S3C2443_CLKDIV1_HSMMCDIV_SHIFT;
  340. __raw_writel(clkdivn, S3C2443_CLKDIV1);
  341. return 0;
  342. }
  343. static struct clk clk_hsmmc_div = {
  344. .name = "hsmmc-div",
  345. .id = -1,
  346. .parent = &clk_esysclk,
  347. .get_rate = s3c2443_getrate_hsmmc_div,
  348. .set_rate = s3c2443_setrate_hsmmc_div,
  349. .round_rate = s3c2443_roundrate_clksrc4,
  350. };
  351. static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
  352. {
  353. unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
  354. clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
  355. S3C2443_SCLKCON_HSMMCCLK_EPLL);
  356. if (parent == &clk_epll)
  357. clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
  358. else if (parent == &clk_ext)
  359. clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
  360. else
  361. return -EINVAL;
  362. if (clk->usage > 0) {
  363. __raw_writel(clksrc, S3C2443_SCLKCON);
  364. }
  365. clk->parent = parent;
  366. return 0;
  367. }
  368. static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
  369. {
  370. return s3c2443_setparent_hsmmc(clk, clk->parent);
  371. }
  372. static struct clk clk_hsmmc = {
  373. .name = "hsmmc-if",
  374. .id = -1,
  375. .parent = &clk_hsmmc_div,
  376. .enable = s3c2443_enable_hsmmc,
  377. .set_parent = s3c2443_setparent_hsmmc,
  378. };
  379. /* i2s_eplldiv
  380. *
  381. * this clock is the output from the i2s divisor of esysclk
  382. */
  383. static unsigned long s3c2443_getrate_i2s_eplldiv(struct clk *clk)
  384. {
  385. unsigned long parent_rate = clk_get_rate(clk->parent);
  386. unsigned long div = __raw_readl(S3C2443_CLKDIV1);
  387. div &= S3C2443_CLKDIV1_I2SDIV_MASK;
  388. div >>= S3C2443_CLKDIV1_I2SDIV_SHIFT;
  389. return parent_rate / (div + 1);
  390. }
  391. static int s3c2443_setrate_i2s_eplldiv(struct clk *clk, unsigned long rate)
  392. {
  393. unsigned long parent_rate = clk_get_rate(clk->parent);
  394. unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
  395. rate = s3c2443_roundrate_clksrc16(clk, rate);
  396. rate = parent_rate / rate;
  397. clkdivn &= ~S3C2443_CLKDIV1_I2SDIV_MASK;
  398. clkdivn |= (rate - 1) << S3C2443_CLKDIV1_I2SDIV_SHIFT;
  399. __raw_writel(clkdivn, S3C2443_CLKDIV1);
  400. return 0;
  401. }
  402. static struct clk clk_i2s_eplldiv = {
  403. .name = "i2s-eplldiv",
  404. .id = -1,
  405. .parent = &clk_esysclk,
  406. .get_rate = s3c2443_getrate_i2s_eplldiv,
  407. .set_rate = s3c2443_setrate_i2s_eplldiv,
  408. .round_rate = s3c2443_roundrate_clksrc16,
  409. };
  410. /* i2s-ref
  411. *
  412. * i2s bus reference clock, selectable from external, esysclk or epllref
  413. */
  414. static int s3c2443_setparent_i2s(struct clk *clk, struct clk *parent)
  415. {
  416. unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
  417. clksrc &= ~S3C2443_CLKSRC_I2S_MASK;
  418. if (parent == &clk_epllref)
  419. clksrc |= S3C2443_CLKSRC_I2S_EPLLREF;
  420. else if (parent == &clk_i2s_ext)
  421. clksrc |= S3C2443_CLKSRC_I2S_EXT;
  422. else if (parent != &clk_i2s_eplldiv)
  423. return -EINVAL;
  424. clk->parent = parent;
  425. __raw_writel(clksrc, S3C2443_CLKSRC);
  426. return 0;
  427. }
  428. static struct clk clk_i2s = {
  429. .name = "i2s-if",
  430. .id = -1,
  431. .parent = &clk_i2s_eplldiv,
  432. .ctrlbit = S3C2443_SCLKCON_I2SCLK,
  433. .enable = s3c2443_clkcon_enable_s,
  434. .set_parent = s3c2443_setparent_i2s,
  435. };
  436. /* cam-if
  437. *
  438. * camera interface bus-clock, divided down from esysclk
  439. */
  440. static unsigned long s3c2443_getrate_cam(struct clk *clk)
  441. {
  442. unsigned long parent_rate = clk_get_rate(clk->parent);
  443. unsigned long div = __raw_readl(S3C2443_CLKDIV1);
  444. div &= S3C2443_CLKDIV1_CAMDIV_MASK;
  445. div >>= S3C2443_CLKDIV1_CAMDIV_SHIFT;
  446. return parent_rate / (div + 1);
  447. }
  448. static int s3c2443_setrate_cam(struct clk *clk, unsigned long rate)
  449. {
  450. unsigned long parent_rate = clk_get_rate(clk->parent);
  451. unsigned long clkdiv1 = __raw_readl(S3C2443_CLKDIV1);
  452. rate = (int) (parent_rate / 19200000);
  453. clkdiv1 &= ~S3C2443_CLKDIV1_CAMDIV_MASK;
  454. clkdiv1 |= (rate - 1) << S3C2443_CLKDIV1_CAMDIV_SHIFT;
  455. __raw_writel(clkdiv1, S3C2443_CLKDIV1);
  456. return 0;
  457. }
  458. static struct clk clk_cam = {
  459. .name = "camif-upll", /* same as 2440 name */
  460. .id = -1,
  461. .parent = &clk_esysclk,
  462. .ctrlbit = S3C2443_SCLKCON_CAMCLK,
  463. .enable = s3c2443_clkcon_enable_s,
  464. .get_rate = s3c2443_getrate_cam,
  465. .set_rate = s3c2443_setrate_cam,
  466. .round_rate = s3c2443_roundrate_clksrc16,
  467. };
  468. /* display-if
  469. *
  470. * display interface clock, divided from esysclk
  471. */
  472. static unsigned long s3c2443_getrate_display(struct clk *clk)
  473. {
  474. unsigned long parent_rate = clk_get_rate(clk->parent);
  475. unsigned long div = __raw_readl(S3C2443_CLKDIV1);
  476. div &= S3C2443_CLKDIV1_DISPDIV_MASK;
  477. div >>= S3C2443_CLKDIV1_DISPDIV_SHIFT;
  478. return parent_rate / (div + 1);
  479. }
  480. static int s3c2443_setrate_display(struct clk *clk, unsigned long rate)
  481. {
  482. unsigned long parent_rate = clk_get_rate(clk->parent);
  483. unsigned long clkdivn = __raw_readl(S3C2443_CLKDIV1);
  484. rate = s3c2443_roundrate_clksrc256(clk, rate);
  485. rate = parent_rate / rate;
  486. clkdivn &= ~S3C2443_CLKDIV1_UARTDIV_MASK;
  487. clkdivn |= (rate - 1) << S3C2443_CLKDIV1_UARTDIV_SHIFT;
  488. __raw_writel(clkdivn, S3C2443_CLKDIV1);
  489. return 0;
  490. }
  491. static struct clk clk_display = {
  492. .name = "display-if",
  493. .id = -1,
  494. .parent = &clk_esysclk,
  495. .ctrlbit = S3C2443_SCLKCON_DISPCLK,
  496. .enable = s3c2443_clkcon_enable_s,
  497. .get_rate = s3c2443_getrate_display,
  498. .set_rate = s3c2443_setrate_display,
  499. .round_rate = s3c2443_roundrate_clksrc256,
  500. };
  501. /* standard clock definitions */
  502. static struct clk init_clocks_disable[] = {
  503. {
  504. .name = "nand",
  505. .id = -1,
  506. .parent = &clk_h,
  507. }, {
  508. .name = "sdi",
  509. .id = -1,
  510. .parent = &clk_p,
  511. .enable = s3c2443_clkcon_enable_p,
  512. .ctrlbit = S3C2443_PCLKCON_SDI,
  513. }, {
  514. .name = "adc",
  515. .id = -1,
  516. .parent = &clk_p,
  517. .enable = s3c2443_clkcon_enable_p,
  518. .ctrlbit = S3C2443_PCLKCON_ADC,
  519. }, {
  520. .name = "i2c",
  521. .id = -1,
  522. .parent = &clk_p,
  523. .enable = s3c2443_clkcon_enable_p,
  524. .ctrlbit = S3C2443_PCLKCON_IIC,
  525. }, {
  526. .name = "iis",
  527. .id = -1,
  528. .parent = &clk_p,
  529. .enable = s3c2443_clkcon_enable_p,
  530. .ctrlbit = S3C2443_PCLKCON_IIS,
  531. }, {
  532. .name = "spi",
  533. .id = 0,
  534. .parent = &clk_p,
  535. .enable = s3c2443_clkcon_enable_p,
  536. .ctrlbit = S3C2443_PCLKCON_SPI0,
  537. }, {
  538. .name = "spi",
  539. .id = 1,
  540. .parent = &clk_p,
  541. .enable = s3c2443_clkcon_enable_p,
  542. .ctrlbit = S3C2443_PCLKCON_SPI1,
  543. }
  544. };
  545. static struct clk init_clocks[] = {
  546. {
  547. .name = "dma",
  548. .id = 0,
  549. .parent = &clk_h,
  550. .enable = s3c2443_clkcon_enable_h,
  551. .ctrlbit = S3C2443_HCLKCON_DMA0,
  552. }, {
  553. .name = "dma",
  554. .id = 1,
  555. .parent = &clk_h,
  556. .enable = s3c2443_clkcon_enable_h,
  557. .ctrlbit = S3C2443_HCLKCON_DMA1,
  558. }, {
  559. .name = "dma",
  560. .id = 2,
  561. .parent = &clk_h,
  562. .enable = s3c2443_clkcon_enable_h,
  563. .ctrlbit = S3C2443_HCLKCON_DMA2,
  564. }, {
  565. .name = "dma",
  566. .id = 3,
  567. .parent = &clk_h,
  568. .enable = s3c2443_clkcon_enable_h,
  569. .ctrlbit = S3C2443_HCLKCON_DMA3,
  570. }, {
  571. .name = "dma",
  572. .id = 4,
  573. .parent = &clk_h,
  574. .enable = s3c2443_clkcon_enable_h,
  575. .ctrlbit = S3C2443_HCLKCON_DMA4,
  576. }, {
  577. .name = "dma",
  578. .id = 5,
  579. .parent = &clk_h,
  580. .enable = s3c2443_clkcon_enable_h,
  581. .ctrlbit = S3C2443_HCLKCON_DMA5,
  582. }, {
  583. .name = "dma",
  584. .id = 6,
  585. .parent = &clk_h,
  586. .enable = s3c2443_clkcon_enable_h,
  587. .ctrlbit = S3C2443_HCLKCON_DMA6,
  588. }, {
  589. .name = "dma",
  590. .id = 7,
  591. .parent = &clk_h,
  592. .enable = s3c2443_clkcon_enable_h,
  593. .ctrlbit = S3C2443_HCLKCON_DMA7,
  594. }, {
  595. .name = "lcd",
  596. .id = -1,
  597. .parent = &clk_h,
  598. .enable = s3c2443_clkcon_enable_h,
  599. .ctrlbit = S3C2443_HCLKCON_LCDC,
  600. }, {
  601. .name = "gpio",
  602. .id = -1,
  603. .parent = &clk_p,
  604. .enable = s3c2443_clkcon_enable_p,
  605. .ctrlbit = S3C2443_PCLKCON_GPIO,
  606. }, {
  607. .name = "usb-host",
  608. .id = -1,
  609. .parent = &clk_h,
  610. .enable = s3c2443_clkcon_enable_h,
  611. .ctrlbit = S3C2443_HCLKCON_USBH,
  612. }, {
  613. .name = "usb-device",
  614. .id = -1,
  615. .parent = &clk_h,
  616. .enable = s3c2443_clkcon_enable_h,
  617. .ctrlbit = S3C2443_HCLKCON_USBD,
  618. }, {
  619. .name = "timers",
  620. .id = -1,
  621. .parent = &clk_p,
  622. .enable = s3c2443_clkcon_enable_p,
  623. .ctrlbit = S3C2443_PCLKCON_PWMT,
  624. }, {
  625. .name = "uart",
  626. .id = 0,
  627. .parent = &clk_p,
  628. .enable = s3c2443_clkcon_enable_p,
  629. .ctrlbit = S3C2443_PCLKCON_UART0,
  630. }, {
  631. .name = "uart",
  632. .id = 1,
  633. .parent = &clk_p,
  634. .enable = s3c2443_clkcon_enable_p,
  635. .ctrlbit = S3C2443_PCLKCON_UART1,
  636. }, {
  637. .name = "uart",
  638. .id = 2,
  639. .parent = &clk_p,
  640. .enable = s3c2443_clkcon_enable_p,
  641. .ctrlbit = S3C2443_PCLKCON_UART2,
  642. }, {
  643. .name = "uart",
  644. .id = 3,
  645. .parent = &clk_p,
  646. .enable = s3c2443_clkcon_enable_p,
  647. .ctrlbit = S3C2443_PCLKCON_UART3,
  648. }, {
  649. .name = "rtc",
  650. .id = -1,
  651. .parent = &clk_p,
  652. .enable = s3c2443_clkcon_enable_p,
  653. .ctrlbit = S3C2443_PCLKCON_RTC,
  654. }, {
  655. .name = "watchdog",
  656. .id = -1,
  657. .parent = &clk_p,
  658. .ctrlbit = S3C2443_PCLKCON_WDT,
  659. }, {
  660. .name = "usb-bus-host",
  661. .id = -1,
  662. .parent = &clk_usb_bus_host,
  663. },{
  664. .name = "hsmmc",
  665. .id = -1,
  666. .parent = &clk_h,
  667. .enable = s3c2443_clkcon_enable_h,
  668. .ctrlbit = S3C2443_HCLKCON_HSMMC
  669. },{
  670. .name = "hsmmc-epll",
  671. .id = -1,
  672. .parent = &clk_epll,
  673. },{
  674. .name = "hsmmc-ext",
  675. .id = -1,
  676. .parent = &clk_ext,
  677. .enable = s3c2443_clkcon_enable_s,
  678. .ctrlbit = S3C2443_SCLKCON_HSMMCCLK_EXT,
  679. .rate = 12 * 1000 * 1000
  680. },
  681. };
  682. /* clocks to add where we need to check their parentage */
  683. /* s3c2443_clk_initparents
  684. *
  685. * Initialise the parents for the clocks that we get at start-time
  686. */
  687. static int __init clk_init_set_parent(struct clk *clk, struct clk *parent)
  688. {
  689. printk(KERN_DEBUG "clock %s: parent %s\n", clk->name, parent->name);
  690. return clk_set_parent(clk, parent);
  691. }
  692. static void __init s3c2443_clk_initparents(void)
  693. {
  694. unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
  695. struct clk *parent;
  696. switch (clksrc & S3C2443_CLKSRC_EPLLREF_MASK) {
  697. case S3C2443_CLKSRC_EPLLREF_EXTCLK:
  698. parent = &clk_ext;
  699. break;
  700. case S3C2443_CLKSRC_EPLLREF_XTAL:
  701. default:
  702. parent = &clk_xtal;
  703. break;
  704. case S3C2443_CLKSRC_EPLLREF_MPLLREF:
  705. case S3C2443_CLKSRC_EPLLREF_MPLLREF2:
  706. parent = &clk_mpllref;
  707. break;
  708. }
  709. clk_init_set_parent(&clk_epllref, parent);
  710. switch (clksrc & S3C2443_CLKSRC_I2S_MASK) {
  711. case S3C2443_CLKSRC_I2S_EXT:
  712. parent = &clk_i2s_ext;
  713. break;
  714. case S3C2443_CLKSRC_I2S_EPLLDIV:
  715. default:
  716. parent = &clk_i2s_eplldiv;
  717. break;
  718. case S3C2443_CLKSRC_I2S_EPLLREF:
  719. case S3C2443_CLKSRC_I2S_EPLLREF3:
  720. parent = &clk_epllref;
  721. }
  722. clk_init_set_parent(&clk_i2s, &clk_epllref);
  723. /* esysclk source */
  724. parent = (clksrc & S3C2443_CLKSRC_ESYSCLK_EPLL) ?
  725. &clk_epll : &clk_epllref;
  726. clk_init_set_parent(&clk_esysclk, parent);
  727. /* msysclk source */
  728. if (clksrc & S3C2443_CLKSRC_MSYSCLK_MPLL) {
  729. parent = &clk_mpll;
  730. } else {
  731. parent = (clksrc & S3C2443_CLKSRC_EXTCLK_DIV) ?
  732. &clk_mdivclk : &clk_mpllref;
  733. }
  734. clk_init_set_parent(&clk_msysclk, parent);
  735. }
  736. /* armdiv divisor table */
  737. static unsigned int armdiv[16] = {
  738. [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 1,
  739. [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 2,
  740. [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 3,
  741. [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 4,
  742. [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 6,
  743. [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 8,
  744. [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 12,
  745. [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT] = 16,
  746. };
  747. static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
  748. {
  749. clkcon0 &= S3C2443_CLKDIV0_ARMDIV_MASK;
  750. return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
  751. }
  752. static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0)
  753. {
  754. clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK;
  755. clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
  756. return clkcon0 + 1;
  757. }
  758. /* clocks to add straight away */
  759. static struct clk *clks[] __initdata = {
  760. &clk_ext,
  761. &clk_epll,
  762. &clk_usb_bus_host,
  763. &clk_usb_bus,
  764. &clk_esysclk,
  765. &clk_epllref,
  766. &clk_mpllref,
  767. &clk_msysclk,
  768. &clk_uart,
  769. &clk_display,
  770. &clk_cam,
  771. &clk_i2s_eplldiv,
  772. &clk_i2s,
  773. &clk_hsspi,
  774. &clk_hsmmc_div,
  775. &clk_hsmmc,
  776. };
  777. void __init s3c2416_init_clocks(int xtal)
  778. {
  779. unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
  780. unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
  781. unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
  782. unsigned long pll;
  783. unsigned long fclk;
  784. unsigned long hclk;
  785. unsigned long pclk;
  786. struct clk *clkp;
  787. int ret;
  788. int ptr;
  789. pll = s3c2443_get_mpll(mpllcon, xtal);
  790. fclk = pll / s3c2443_fclk_div(clkdiv0);
  791. /* bug fix */
  792. /* hclk = fclk / s3c2443_get_prediv(clkdiv0); */
  793. hclk = pll / s3c2443_get_prediv(clkdiv0);
  794. hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
  795. pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
  796. s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
  797. printk("S3C2416: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
  798. (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on",
  799. print_mhz(pll), print_mhz(fclk),
  800. print_mhz(hclk), print_mhz(pclk));
  801. s3c2443_clk_initparents();
  802. for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
  803. clkp = clks[ptr];
  804. ret = s3c24xx_register_clock(clkp);
  805. if (ret < 0) {
  806. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  807. clkp->name, ret);
  808. }
  809. }
  810. clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
  811. clk_usb_bus.parent = &clk_usb_bus_host;
  812. /* ensure usb bus clock is within correct rate of 48MHz */
  813. if (clk_get_rate(&clk_usb_bus_host) != (48 * 1000 * 1000)) {
  814. printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
  815. clk_set_rate(&clk_usb_bus_host, 48*1000*1000);
  816. }
  817. printk("S3C2416: epll %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
  818. (epllcon & S3C2443_PLLCON_OFF) ? "off":"on",
  819. print_mhz(clk_get_rate(&clk_epll)),
  820. print_mhz(clk_get_rate(&clk_usb_bus)));
  821. /* register clocks from clock array */
  822. clkp = init_clocks;
  823. for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
  824. ret = s3c24xx_register_clock(clkp);
  825. if (ret < 0) {
  826. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  827. clkp->name, ret);
  828. }
  829. }
  830. /* We must be careful disabling the clocks we are not intending to
  831. * be using at boot time, as subsytems such as the LCD which do
  832. * their own DMA requests to the bus can cause the system to lockup
  833. * if they where in the middle of requesting bus access.
  834. *
  835. * Disabling the LCD clock if the LCD is active is very dangerous,
  836. * and therefore the bootloader should be careful to not enable
  837. * the LCD clock if it is not needed.
  838. */
  839. /* install (and disable) the clocks we do not need immediately */
  840. clkp = init_clocks_disable;
  841. for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
  842. ret = s3c24xx_register_clock(clkp);
  843. if (ret < 0) {
  844. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  845. clkp->name, ret);
  846. }
  847. (clkp->enable)(clkp, 0);
  848. }
  849. }