eagle_soc.h 11 KB

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  1. /*
  2. * Copyright (c) Espressif System 2010 - 2012
  3. *
  4. */
  5. #ifndef _EAGLE_SOC_H_
  6. #define _EAGLE_SOC_H_
  7. //Register Bits{{
  8. #define BIT31 0x80000000
  9. #define BIT30 0x40000000
  10. #define BIT29 0x20000000
  11. #define BIT28 0x10000000
  12. #define BIT27 0x08000000
  13. #define BIT26 0x04000000
  14. #define BIT25 0x02000000
  15. #define BIT24 0x01000000
  16. #define BIT23 0x00800000
  17. #define BIT22 0x00400000
  18. #define BIT21 0x00200000
  19. #define BIT20 0x00100000
  20. #define BIT19 0x00080000
  21. #define BIT18 0x00040000
  22. #define BIT17 0x00020000
  23. #define BIT16 0x00010000
  24. #define BIT15 0x00008000
  25. #define BIT14 0x00004000
  26. #define BIT13 0x00002000
  27. #define BIT12 0x00001000
  28. #define BIT11 0x00000800
  29. #define BIT10 0x00000400
  30. #define BIT9 0x00000200
  31. #define BIT8 0x00000100
  32. #define BIT7 0x00000080
  33. #define BIT6 0x00000040
  34. #define BIT5 0x00000020
  35. #define BIT4 0x00000010
  36. #define BIT3 0x00000008
  37. #define BIT2 0x00000004
  38. #define BIT1 0x00000002
  39. #define BIT0 0x00000001
  40. //}}
  41. //Registers Operation {{
  42. #define ETS_UNCACHED_ADDR(addr) (addr)
  43. #define ETS_CACHED_ADDR(addr) (addr)
  44. #define READ_PERI_REG(addr) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)))
  45. #define WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val)
  46. #define CLEAR_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))))
  47. #define SET_PERI_REG_MASK(reg, mask) WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)))
  48. #define GET_PERI_REG_BITS(reg, hipos,lowpos) ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
  49. #define SET_PERI_REG_BITS(reg,bit_map,value,shift) (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|((value)<<(shift)) ))
  50. //}}
  51. //Periheral Clock {{
  52. #define CPU_CLK_FREQ 80*1000000 //unit: Hz
  53. #define APB_CLK_FREQ CPU_CLK_FREQ
  54. #define UART_CLK_FREQ APB_CLK_FREQ
  55. #define TIMER_CLK_FREQ (APB_CLK_FREQ>>8) //divided by 256
  56. //}}
  57. //Peripheral device base address define{{
  58. #define PERIPHS_DPORT_BASEADDR 0x3ff00000
  59. #define PERIPHS_GPIO_BASEADDR 0x60000300
  60. #define PERIPHS_TIMER_BASEDDR 0x60000600
  61. #define PERIPHS_RTC_BASEADDR 0x60000700
  62. #define PERIPHS_IO_MUX 0x60000800
  63. //}}
  64. //Interrupt remap control registers define{{
  65. #define EDGE_INT_ENABLE_REG (PERIPHS_DPORT_BASEADDR+0x04)
  66. #define TM1_EDGE_INT_ENABLE() SET_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
  67. #define TM1_EDGE_INT_DISABLE() CLEAR_PERI_REG_MASK(EDGE_INT_ENABLE_REG, BIT1)
  68. //}}
  69. //GPIO reg {{
  70. #define GPIO_REG_READ(reg) READ_PERI_REG(PERIPHS_GPIO_BASEADDR + reg)
  71. #define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(PERIPHS_GPIO_BASEADDR + reg, val)
  72. #define GPIO_OUT_ADDRESS 0x00
  73. #define GPIO_OUT_W1TS_ADDRESS 0x04
  74. #define GPIO_OUT_W1TC_ADDRESS 0x08
  75. #define GPIO_ENABLE_ADDRESS 0x0c
  76. #define GPIO_ENABLE_W1TS_ADDRESS 0x10
  77. #define GPIO_ENABLE_W1TC_ADDRESS 0x14
  78. #define GPIO_OUT_W1TC_DATA_MASK 0x0000ffff
  79. #define GPIO_IN_ADDRESS 0x18
  80. #define GPIO_STATUS_ADDRESS 0x1c
  81. #define GPIO_STATUS_W1TS_ADDRESS 0x20
  82. #define GPIO_STATUS_W1TC_ADDRESS 0x24
  83. #define GPIO_STATUS_INTERRUPT_MASK 0x0000ffff
  84. #define GPIO_RTC_CALIB_SYNC PERIPHS_GPIO_BASEADDR+0x6c
  85. #define RTC_CALIB_START BIT31 //first write to zero, then to one to start
  86. #define RTC_PERIOD_NUM_MASK 0x3ff //max 8ms
  87. #define GPIO_RTC_CALIB_VALUE PERIPHS_GPIO_BASEADDR+0x70
  88. #define RTC_CALIB_RDY_S 31 //after measure, flag to one, when start from zero to one, turn to zero
  89. #define RTC_CALIB_VALUE_MASK 0xfffff
  90. #define GPIO_PIN0_ADDRESS 0x28
  91. #define GPIO_ID_PIN0 0
  92. #define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
  93. #define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(15)
  94. #define GPIO_ID_NONE 0xffffffff
  95. #define GPIO_PIN_COUNT 16
  96. #define GPIO_PIN_CONFIG_MSB 12
  97. #define GPIO_PIN_CONFIG_LSB 11
  98. #define GPIO_PIN_CONFIG_MASK 0x00001800
  99. #define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
  100. #define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
  101. #define GPIO_WAKEUP_ENABLE 1
  102. #define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE)
  103. #define GPIO_PIN_WAKEUP_ENABLE_MSB 10
  104. #define GPIO_PIN_WAKEUP_ENABLE_LSB 10
  105. #define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400
  106. #define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
  107. #define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
  108. #define GPIO_PIN_INT_TYPE_MASK 0x380
  109. #define GPIO_PIN_INT_TYPE_MSB 9
  110. #define GPIO_PIN_INT_TYPE_LSB 7
  111. #define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
  112. #define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
  113. #define GPIO_PAD_DRIVER_ENABLE 1
  114. #define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE)
  115. #define GPIO_PIN_PAD_DRIVER_MSB 2
  116. #define GPIO_PIN_PAD_DRIVER_LSB 2
  117. #define GPIO_PIN_PAD_DRIVER_MASK 0x00000004
  118. #define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
  119. #define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
  120. #define GPIO_AS_PIN_SOURCE 0
  121. #define SIGMA_AS_PIN_SOURCE (~GPIO_AS_PIN_SOURCE)
  122. #define GPIO_PIN_SOURCE_MSB 0
  123. #define GPIO_PIN_SOURCE_LSB 0
  124. #define GPIO_PIN_SOURCE_MASK 0x00000001
  125. #define GPIO_PIN_SOURCE_GET(x) (((x) & GPIO_PIN_SOURCE_MASK) >> GPIO_PIN_SOURCE_LSB)
  126. #define GPIO_PIN_SOURCE_SET(x) (((x) << GPIO_PIN_SOURCE_LSB) & GPIO_PIN_SOURCE_MASK)
  127. // }}
  128. // TIMER reg {{
  129. #define RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr)
  130. #define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val)
  131. #define RTC_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask)
  132. /* Returns the current time according to the timer timer. */
  133. #define NOW() RTC_REG_READ(FRC2_COUNT_ADDRESS)
  134. //load initial_value to timer1
  135. #define FRC1_LOAD_ADDRESS 0x00
  136. //timer1's counter value(count from initial_value to 0)
  137. #define FRC1_COUNT_ADDRESS 0x04
  138. #define FRC1_CTRL_ADDRESS 0x08
  139. //clear timer1's interrupt when write this address
  140. #define FRC1_INT_ADDRESS 0x0c
  141. #define FRC1_INT_CLR_MASK 0x00000001
  142. //timer2's counter value(count from initial_value to 0)
  143. #define FRC2_COUNT_ADDRESS 0x24
  144. // }}
  145. //RTC reg {{
  146. #define REG_RTC_BASE PERIPHS_RTC_BASEADDR
  147. #define RTC_GPIO_OUT (REG_RTC_BASE + 0x068)
  148. #define RTC_GPIO_ENABLE (REG_RTC_BASE + 0x074)
  149. #define RTC_GPIO_IN_DATA (REG_RTC_BASE + 0x08C)
  150. #define RTC_GPIO_CONF (REG_RTC_BASE + 0x090)
  151. #define PAD_XPD_DCDC_CONF (REG_RTC_BASE + 0x0A0)
  152. //}}
  153. //PIN Mux reg {{
  154. #define PERIPHS_IO_MUX_FUNC 0x13
  155. #define PERIPHS_IO_MUX_FUNC_S 4
  156. #define PERIPHS_IO_MUX_PULLUP BIT7
  157. #define PERIPHS_IO_MUX_PULLDWN BIT6
  158. #define PERIPHS_IO_MUX_SLEEP_PULLUP BIT3
  159. #define PERIPHS_IO_MUX_SLEEP_PULLDWN BIT2
  160. #define PERIPHS_IO_MUX_SLEEP_OE BIT1
  161. #define PERIPHS_IO_MUX_OE BIT0
  162. #define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00)
  163. #define SPI0_CLK_EQU_SYS_CLK BIT8
  164. #define SPI1_CLK_EQU_SYS_CLK BIT9
  165. #define PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04)
  166. #define FUNC_GPIO12 3
  167. #define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08)
  168. #define FUNC_GPIO13 3
  169. #define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C)
  170. #define FUNC_GPIO14 3
  171. #define PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10)
  172. #define FUNC_GPIO15 3
  173. #define FUNC_U0RTS 4
  174. #define PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14)
  175. #define FUNC_U0RXD 0
  176. #define FUNC_GPIO3 3
  177. #define PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18)
  178. #define FUNC_U0TXD 0
  179. #define FUNC_GPIO1 3
  180. #define PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c)
  181. #define FUNC_SDCLK 0
  182. #define FUNC_SPICLK 1
  183. #define PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20)
  184. #define FUNC_SDDATA0 0
  185. #define FUNC_SPIQ 1
  186. #define FUNC_U1TXD 4
  187. #define PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24)
  188. #define FUNC_SDDATA1 0
  189. #define FUNC_SPID 1
  190. #define FUNC_U1RXD 4
  191. #define FUNC_SDDATA1_U1RXD 7
  192. #define PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28)
  193. #define FUNC_SDDATA2 0
  194. #define FUNC_SPIHD 1
  195. #define FUNC_GPIO9 3
  196. #define PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c)
  197. #define FUNC_SDDATA3 0
  198. #define FUNC_SPIWP 1
  199. #define FUNC_GPIO10 3
  200. #define PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30)
  201. #define FUNC_SDCMD 0
  202. #define FUNC_SPICS0 1
  203. #define PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34)
  204. #define FUNC_GPIO0 0
  205. #define PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38)
  206. #define FUNC_GPIO2 0
  207. #define FUNC_U1TXD_BK 2
  208. #define FUNC_U0TXD_BK 4
  209. #define PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C)
  210. #define FUNC_GPIO4 0
  211. #define PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40)
  212. #define FUNC_GPIO5 0
  213. #define PIN_PULLUP_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
  214. #define PIN_PULLUP_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLUP)
  215. #define PIN_PULLDWN_DIS(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLDWN)
  216. #define PIN_PULLDWN_EN(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME, PERIPHS_IO_MUX_PULLDWN)
  217. #define PIN_FUNC_SELECT(PIN_NAME, FUNC) do { \
  218. CLEAR_PERI_REG_MASK(PIN_NAME, (PERIPHS_IO_MUX_FUNC<<PERIPHS_IO_MUX_FUNC_S)); \
  219. SET_PERI_REG_MASK(PIN_NAME, (((FUNC&BIT2)<<2)|(FUNC&0x3))<<PERIPHS_IO_MUX_FUNC_S); \
  220. } while (0)
  221. //}}
  222. #endif //_EAGLE_SOC_H_