platform.c 33 KB

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  1. // Platform-dependent functions and includes
  2. #include "platform.h"
  3. #include "common.h"
  4. #include <stdio.h>
  5. #include <string.h>
  6. #include <stdlib.h>
  7. #include <stdint.h>
  8. #include "gpio.h"
  9. #include "user_interface.h"
  10. #include "driver/gpio16.h"
  11. #include "driver/i2c_master.h"
  12. #include "driver/spi.h"
  13. #include "driver/uart.h"
  14. #include "driver/sigma_delta.h"
  15. #define INTERRUPT_TYPE_IS_LEVEL(x) ((x) >= GPIO_PIN_INTR_LOLEVEL)
  16. #ifdef GPIO_INTERRUPT_ENABLE
  17. static platform_task_handle_t gpio_task_handle;
  18. static int task_init_handler(void);
  19. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  20. struct gpio_hook_entry {
  21. platform_hook_function func;
  22. uint32_t bits;
  23. };
  24. struct gpio_hook {
  25. uint32_t all_bits;
  26. uint32_t count;
  27. struct gpio_hook_entry entry[1];
  28. };
  29. static struct gpio_hook *platform_gpio_hook;
  30. #endif
  31. #endif
  32. static const int uart_bitrates[] = {
  33. BIT_RATE_300,
  34. BIT_RATE_600,
  35. BIT_RATE_1200,
  36. BIT_RATE_2400,
  37. BIT_RATE_4800,
  38. BIT_RATE_9600,
  39. BIT_RATE_19200,
  40. BIT_RATE_31250,
  41. BIT_RATE_38400,
  42. BIT_RATE_57600,
  43. BIT_RATE_74880,
  44. BIT_RATE_115200,
  45. BIT_RATE_230400,
  46. BIT_RATE_256000,
  47. BIT_RATE_460800,
  48. BIT_RATE_921600,
  49. BIT_RATE_1843200,
  50. BIT_RATE_3686400
  51. };
  52. int platform_init ()
  53. {
  54. // Setup the various forward and reverse mappings for the pins
  55. get_pin_map();
  56. (void) task_init_handler();
  57. cmn_platform_init();
  58. // All done
  59. return PLATFORM_OK;
  60. }
  61. // ****************************************************************************
  62. // KEY_LED functions
  63. uint8_t platform_key_led( uint8_t level){
  64. uint8_t temp;
  65. gpio16_output_set(1); // set to high first, for reading key low level
  66. gpio16_input_conf();
  67. temp = gpio16_input_get();
  68. gpio16_output_conf();
  69. gpio16_output_set(level);
  70. return temp;
  71. }
  72. // ****************************************************************************
  73. // GPIO functions
  74. /*
  75. * Set GPIO mode to output. Optionally in RAM helper because interrupts are dsabled
  76. */
  77. static void NO_INTR_CODE set_gpio_no_interrupt(uint8_t pin, uint8_t push_pull) {
  78. unsigned pnum = pin_num[pin];
  79. ETS_GPIO_INTR_DISABLE();
  80. #ifdef GPIO_INTERRUPT_ENABLE
  81. pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
  82. #endif
  83. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  84. //disable interrupt
  85. gpio_pin_intr_state_set(GPIO_ID_PIN(pnum), GPIO_PIN_INTR_DISABLE);
  86. //clear interrupt status
  87. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pnum));
  88. // configure push-pull vs open-drain
  89. if (push_pull) {
  90. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  91. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) &
  92. (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
  93. } else {
  94. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  95. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) |
  96. GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //enable open drain;
  97. }
  98. ETS_GPIO_INTR_ENABLE();
  99. }
  100. /*
  101. * Set GPIO mode to interrupt. Optionally RAM helper because interrupts are dsabled
  102. */
  103. #ifdef GPIO_INTERRUPT_ENABLE
  104. static void NO_INTR_CODE set_gpio_interrupt(uint8_t pin) {
  105. ETS_GPIO_INTR_DISABLE();
  106. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  107. GPIO_DIS_OUTPUT(pin_num[pin]);
  108. gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  109. GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
  110. | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
  111. | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
  112. ETS_GPIO_INTR_ENABLE();
  113. }
  114. #endif
  115. int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
  116. {
  117. NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n", pin_mux[pin], pin_func[pin]);
  118. if (pin >= NUM_GPIO)
  119. return -1;
  120. if(pin == 0){
  121. if(mode==PLATFORM_GPIO_INPUT)
  122. gpio16_input_conf();
  123. else
  124. gpio16_output_conf();
  125. return 1;
  126. }
  127. #ifdef LUA_USE_MODULES_PWM
  128. platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
  129. #endif
  130. if (pull == PLATFORM_GPIO_PULLUP) {
  131. PIN_PULLUP_EN(pin_mux[pin]);
  132. } else {
  133. PIN_PULLUP_DIS(pin_mux[pin]);
  134. }
  135. switch(mode){
  136. case PLATFORM_GPIO_INPUT:
  137. GPIO_DIS_OUTPUT(pin_num[pin]);
  138. set_gpio_no_interrupt(pin, TRUE);
  139. break;
  140. case PLATFORM_GPIO_OUTPUT:
  141. set_gpio_no_interrupt(pin, TRUE);
  142. GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, BIT(pin_num[pin]));
  143. break;
  144. case PLATFORM_GPIO_OPENDRAIN:
  145. set_gpio_no_interrupt(pin, FALSE);
  146. GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, BIT(pin_num[pin]));
  147. break;
  148. #ifdef GPIO_INTERRUPT_ENABLE
  149. case PLATFORM_GPIO_INT:
  150. set_gpio_interrupt(pin);
  151. break;
  152. #endif
  153. default:
  154. break;
  155. }
  156. return 1;
  157. }
  158. int platform_gpio_write( unsigned pin, unsigned level )
  159. {
  160. // NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
  161. if (pin >= NUM_GPIO)
  162. return -1;
  163. if(pin == 0){
  164. gpio16_output_conf();
  165. gpio16_output_set(level);
  166. return 1;
  167. }
  168. GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
  169. }
  170. int platform_gpio_read( unsigned pin )
  171. {
  172. // NODE_DBG("Function platform_gpio_read() is called. pin:%d\n",GPIO_ID_PIN(pin_num[pin]));
  173. if (pin >= NUM_GPIO)
  174. return -1;
  175. if(pin == 0){
  176. // gpio16_input_conf();
  177. return 0x1 & gpio16_input_get();
  178. }
  179. // GPIO_DIS_OUTPUT(pin_num[pin]);
  180. return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
  181. }
  182. #ifdef GPIO_INTERRUPT_ENABLE
  183. static void ICACHE_RAM_ATTR platform_gpio_intr_dispatcher (void *dummy){
  184. uint32_t j=0;
  185. uint32_t gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  186. uint32_t now = system_get_time();
  187. (void)(dummy);
  188. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  189. if (gpio_status & platform_gpio_hook->all_bits) {
  190. for (j = 0; j < platform_gpio_hook->count; j++) {
  191. if (gpio_status & platform_gpio_hook->entry[j].bits)
  192. gpio_status = (platform_gpio_hook->entry[j].func)(gpio_status);
  193. }
  194. }
  195. #endif
  196. /*
  197. * gpio_status is a bit map where bit 0 is set if unmapped gpio pin 0 (pin3) has
  198. * triggered the ISR. bit 1 if unmapped gpio pin 1 (pin10=U0TXD), etc. Since this
  199. * is the ISR, it makes sense to optimize this by doing a fast scan of the status
  200. * and reverse mapping any set bits.
  201. */
  202. for (j = 0; gpio_status>0; j++, gpio_status >>= 1) {
  203. if (gpio_status&1) {
  204. int i = pin_num_inv[j];
  205. if (pin_int_type[i]) {
  206. uint16_t diff = pin_counter[i].seen ^ pin_counter[i].reported;
  207. pin_counter[i].seen = 0x7fff & (pin_counter[i].seen + 1);
  208. if (INTERRUPT_TYPE_IS_LEVEL(pin_int_type[i])) {
  209. //disable interrupt
  210. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  211. }
  212. //clear interrupt status
  213. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  214. if (diff == 0 || diff & 0x8000) {
  215. uint32_t level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(j));
  216. if (!platform_post_high (gpio_task_handle, (now << 8) + (i<<1) + level)) {
  217. // If we fail to post, then try on the next interrupt
  218. pin_counter[i].seen |= 0x8000;
  219. }
  220. // We re-enable the interrupt when we execute the callback (if level)
  221. }
  222. } else {
  223. // this is an unexpected interrupt so shut it off for now
  224. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  225. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  226. }
  227. }
  228. }
  229. }
  230. void platform_gpio_init( platform_task_handle_t gpio_task )
  231. {
  232. gpio_task_handle = gpio_task;
  233. // No error handling but this is called at startup when there is a lot of free RAM
  234. platform_gpio_hook = calloc (1, sizeof(*platform_gpio_hook) - sizeof(struct gpio_hook_entry));
  235. ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, NULL);
  236. }
  237. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  238. /*
  239. * Register an ISR hook to be called from the GPIO ISR for a given GPIO bitmask.
  240. * This routine is only called a few times so has been optimised for size and
  241. * the unregister is a special case when the bits are 0.
  242. *
  243. * Each hook function can only be registered once. If it is re-registered
  244. * then the hooked bits are just updated to the new value.
  245. */
  246. int platform_gpio_register_intr_hook(uint32_t bits, platform_hook_function hook)
  247. {
  248. struct gpio_hook *oh = platform_gpio_hook;
  249. int i, j, cur = -1;
  250. if (!hook) // Cannot register or unregister null hook
  251. return 0;
  252. // Is the hook already registered?
  253. for (i=0; i<oh->count; i++) {
  254. if (hook == oh->entry[i].func) {
  255. cur = i;
  256. break;
  257. }
  258. }
  259. // return error status if there is a bits clash
  260. if (oh->all_bits & ~(cur < 0 ? 0 : oh->entry[cur].bits) & bits)
  261. return 0;
  262. // Allocate replacement hook block and return 0 on alloc failure
  263. int count = oh->count + (cur < 0 ? 1 : (bits == 0 ? -1 : 0));
  264. struct gpio_hook *nh = malloc (sizeof *oh + (count -1)*sizeof(struct gpio_hook_entry));
  265. if (!oh)
  266. return 0;
  267. nh->all_bits = 0;
  268. nh->count = count;
  269. for (i=0, j=0; i<oh->count; i++) {
  270. if (i == cur && !bits)
  271. continue; /* unregister entry is a no-op */
  272. nh->entry[j] = oh->entry[i]; /* copy existing entry */
  273. if (i == cur)
  274. nh->entry[j].bits = bits; /* update bits if this is a replacement */
  275. nh->all_bits |= nh->entry[j++].bits;
  276. }
  277. if (cur < 0) { /* append new hook entry */
  278. nh->entry[j].func = hook;
  279. nh->entry[j].bits = bits;
  280. nh->all_bits |= bits;
  281. }
  282. ETS_GPIO_INTR_DISABLE();
  283. platform_gpio_hook = nh;
  284. ETS_GPIO_INTR_ENABLE();
  285. free(oh);
  286. return 1;
  287. }
  288. #endif // GPIO_INTERRUPT_HOOK_ENABLE
  289. /*
  290. * Initialise GPIO interrupt mode. Optionally in RAM because interrupts are disabled
  291. */
  292. void NO_INTR_CODE platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
  293. {
  294. if (platform_gpio_exists(pin)) {
  295. ETS_GPIO_INTR_DISABLE();
  296. //clear interrupt status
  297. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  298. pin_int_type[pin] = type;
  299. //enable interrupt
  300. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
  301. ETS_GPIO_INTR_ENABLE();
  302. }
  303. }
  304. #endif
  305. // ****************************************************************************
  306. // UART
  307. // TODO: Support timeouts.
  308. // UartDev is defined and initialized in rom code.
  309. extern UartDevice UartDev;
  310. uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits )
  311. {
  312. switch( baud )
  313. {
  314. case BIT_RATE_300:
  315. case BIT_RATE_600:
  316. case BIT_RATE_1200:
  317. case BIT_RATE_2400:
  318. case BIT_RATE_4800:
  319. case BIT_RATE_9600:
  320. case BIT_RATE_19200:
  321. case BIT_RATE_31250:
  322. case BIT_RATE_38400:
  323. case BIT_RATE_57600:
  324. case BIT_RATE_74880:
  325. case BIT_RATE_115200:
  326. case BIT_RATE_230400:
  327. case BIT_RATE_256000:
  328. case BIT_RATE_460800:
  329. case BIT_RATE_921600:
  330. case BIT_RATE_1843200:
  331. case BIT_RATE_3686400:
  332. UartDev.baut_rate = baud;
  333. break;
  334. default:
  335. UartDev.baut_rate = BIT_RATE_9600;
  336. break;
  337. }
  338. switch( databits )
  339. {
  340. case 5:
  341. UartDev.data_bits = FIVE_BITS;
  342. break;
  343. case 6:
  344. UartDev.data_bits = SIX_BITS;
  345. break;
  346. case 7:
  347. UartDev.data_bits = SEVEN_BITS;
  348. break;
  349. case 8:
  350. UartDev.data_bits = EIGHT_BITS;
  351. break;
  352. default:
  353. UartDev.data_bits = EIGHT_BITS;
  354. break;
  355. }
  356. switch (stopbits)
  357. {
  358. case PLATFORM_UART_STOPBITS_1_5:
  359. UartDev.stop_bits = ONE_HALF_STOP_BIT;
  360. break;
  361. case PLATFORM_UART_STOPBITS_2:
  362. UartDev.stop_bits = TWO_STOP_BIT;
  363. break;
  364. default:
  365. UartDev.stop_bits = ONE_STOP_BIT;
  366. break;
  367. }
  368. switch (parity)
  369. {
  370. case PLATFORM_UART_PARITY_EVEN:
  371. UartDev.parity = EVEN_BITS;
  372. UartDev.exist_parity = STICK_PARITY_EN;
  373. break;
  374. case PLATFORM_UART_PARITY_ODD:
  375. UartDev.parity = ODD_BITS;
  376. UartDev.exist_parity = STICK_PARITY_EN;
  377. break;
  378. default:
  379. UartDev.parity = NONE_BITS;
  380. UartDev.exist_parity = STICK_PARITY_DIS;
  381. break;
  382. }
  383. uart_setup(id);
  384. return baud;
  385. }
  386. void platform_uart_get_config(unsigned id, uint32_t *baudp, uint32_t *databitsp, uint32_t *parityp, uint32_t *stopbitsp) {
  387. UartConfig config = uart_get_config(id);
  388. int i;
  389. int offset = config.baut_rate;
  390. for (i = 0; i < sizeof(uart_bitrates) / sizeof(uart_bitrates[0]); i++) {
  391. int diff = config.baut_rate - uart_bitrates[i];
  392. if (diff < 0) {
  393. diff = -diff;
  394. }
  395. if (diff < offset) {
  396. offset = diff;
  397. *baudp = uart_bitrates[i];
  398. }
  399. }
  400. switch( config.data_bits )
  401. {
  402. case FIVE_BITS:
  403. *databitsp = 5;
  404. break;
  405. case SIX_BITS:
  406. *databitsp = 6;
  407. break;
  408. case SEVEN_BITS:
  409. *databitsp = 7;
  410. break;
  411. case EIGHT_BITS:
  412. default:
  413. *databitsp = 8;
  414. break;
  415. }
  416. switch (config.stop_bits)
  417. {
  418. case ONE_HALF_STOP_BIT:
  419. *stopbitsp = PLATFORM_UART_STOPBITS_1_5;
  420. break;
  421. case TWO_STOP_BIT:
  422. *stopbitsp = PLATFORM_UART_STOPBITS_2;
  423. break;
  424. default:
  425. *stopbitsp = PLATFORM_UART_STOPBITS_1;
  426. break;
  427. }
  428. if (config.exist_parity == STICK_PARITY_DIS) {
  429. *parityp = PLATFORM_UART_PARITY_NONE;
  430. } else if (config.parity == EVEN_BITS) {
  431. *parityp = PLATFORM_UART_PARITY_EVEN;
  432. } else {
  433. *parityp = PLATFORM_UART_PARITY_ODD;
  434. }
  435. }
  436. // if set=1, then alternate serial output pins are used. (15=rx, 13=tx)
  437. void platform_uart_alt( int set )
  438. {
  439. uart0_alt( set );
  440. return;
  441. }
  442. // Send: version with and without mux
  443. void platform_uart_send( unsigned id, u8 data )
  444. {
  445. uart_tx_one_char(id, data);
  446. }
  447. // ****************************************************************************
  448. // PWMs
  449. static uint16_t pwms_duty[NUM_PWM] = {0};
  450. void platform_pwm_init()
  451. {
  452. int i;
  453. for(i=0;i<NUM_PWM;i++){
  454. pwms_duty[i] = DUTY(0);
  455. }
  456. pwm_init(500, NULL);
  457. // NODE_DBG("Function pwms_init() is called.\n");
  458. }
  459. // Return the PWM clock
  460. // NOTE: Can't find a function to query for the period set for the timer,
  461. // therefore using the struct.
  462. // This may require adjustment if driver libraries are updated.
  463. uint32_t platform_pwm_get_clock( unsigned pin )
  464. {
  465. // NODE_DBG("Function platform_pwm_get_clock() is called.\n");
  466. if( pin >= NUM_PWM)
  467. return 0;
  468. if(!pwm_exist(pin))
  469. return 0;
  470. return (uint32_t)pwm_get_freq(pin);
  471. }
  472. // Set the PWM clock
  473. uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
  474. {
  475. // NODE_DBG("Function platform_pwm_set_clock() is called.\n");
  476. if( pin >= NUM_PWM)
  477. return 0;
  478. if(!pwm_exist(pin))
  479. return 0;
  480. pwm_set_freq((uint16_t)clock, pin);
  481. pwm_start();
  482. return (uint32_t)pwm_get_freq( pin );
  483. }
  484. uint32_t platform_pwm_get_duty( unsigned pin )
  485. {
  486. // NODE_DBG("Function platform_pwm_get_duty() is called.\n");
  487. if( pin < NUM_PWM){
  488. if(!pwm_exist(pin))
  489. return 0;
  490. // return NORMAL_DUTY(pwm_get_duty(pin));
  491. return pwms_duty[pin];
  492. }
  493. return 0;
  494. }
  495. // Set the PWM duty
  496. uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
  497. {
  498. // NODE_DBG("Function platform_pwm_set_duty() is called.\n");
  499. if ( pin < NUM_PWM)
  500. {
  501. if(!pwm_exist(pin))
  502. return 0;
  503. pwm_set_duty(DUTY(duty), pin);
  504. } else {
  505. return 0;
  506. }
  507. pwm_start();
  508. pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
  509. return pwms_duty[pin];
  510. }
  511. uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
  512. {
  513. uint32_t clock;
  514. if ( pin < NUM_PWM)
  515. {
  516. platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
  517. if(!pwm_add(pin))
  518. return 0;
  519. // pwm_set_duty(DUTY(duty), pin);
  520. pwm_set_duty(0, pin);
  521. pwms_duty[pin] = duty;
  522. pwm_set_freq((uint16_t)frequency, pin);
  523. } else {
  524. return 0;
  525. }
  526. clock = platform_pwm_get_clock( pin );
  527. if (!pwm_start()) {
  528. return 0;
  529. }
  530. return clock;
  531. }
  532. void platform_pwm_close( unsigned pin )
  533. {
  534. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  535. if ( pin < NUM_PWM)
  536. {
  537. pwm_delete(pin);
  538. pwm_start();
  539. }
  540. }
  541. bool platform_pwm_start( unsigned pin )
  542. {
  543. // NODE_DBG("Function platform_pwm_start() is called.\n");
  544. if ( pin < NUM_PWM)
  545. {
  546. if(!pwm_exist(pin))
  547. return FALSE;
  548. pwm_set_duty(DUTY(pwms_duty[pin]), pin);
  549. return pwm_start();
  550. }
  551. return FALSE;
  552. }
  553. void platform_pwm_stop( unsigned pin )
  554. {
  555. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  556. if ( pin < NUM_PWM)
  557. {
  558. if(!pwm_exist(pin))
  559. return;
  560. pwm_set_duty(0, pin);
  561. pwm_start();
  562. }
  563. }
  564. // *****************************************************************************
  565. // Sigma-Delta platform interface
  566. uint8_t platform_sigma_delta_setup( uint8_t pin )
  567. {
  568. if (pin < 1 || pin > NUM_GPIO)
  569. return 0;
  570. sigma_delta_setup();
  571. // set GPIO output mode for this pin
  572. platform_gpio_mode( pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT );
  573. platform_gpio_write( pin, PLATFORM_GPIO_LOW );
  574. // enable sigma-delta on this pin
  575. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  576. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  577. GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
  578. return 1;
  579. }
  580. uint8_t platform_sigma_delta_close( uint8_t pin )
  581. {
  582. if (pin < 1 || pin > NUM_GPIO)
  583. return 0;
  584. sigma_delta_stop();
  585. // set GPIO input mode for this pin
  586. platform_gpio_mode( pin, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP );
  587. // CONNECT GPIO TO PIN PAD
  588. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  589. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  590. GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
  591. return 1;
  592. }
  593. void platform_sigma_delta_set_pwmduty( uint8_t duty )
  594. {
  595. uint8_t target = 0, prescale = 0;
  596. target = duty > 128 ? 256 - duty : duty;
  597. prescale = target == 0 ? 0 : target-1;
  598. //freq = 80000 (khz) /256 /duty_target * (prescale+1)
  599. sigma_delta_set_prescale_target( prescale, duty );
  600. }
  601. void platform_sigma_delta_set_prescale( uint8_t prescale )
  602. {
  603. sigma_delta_set_prescale_target( prescale, -1 );
  604. }
  605. void ICACHE_RAM_ATTR platform_sigma_delta_set_target( uint8_t target )
  606. {
  607. sigma_delta_set_prescale_target( -1, target );
  608. }
  609. // *****************************************************************************
  610. // I2C platform interface
  611. uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed ){
  612. if (sda >= NUM_GPIO || scl >= NUM_GPIO)
  613. return 0;
  614. // platform_pwm_close(sda);
  615. // platform_pwm_close(scl);
  616. // disable gpio interrupt first
  617. platform_gpio_mode(sda, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // inside this func call platform_pwm_close
  618. platform_gpio_mode(scl, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // disable gpio interrupt first
  619. return i2c_master_setup(id, sda, scl, speed);
  620. }
  621. bool platform_i2c_configured( unsigned id ){
  622. return i2c_master_configured(id);
  623. }
  624. void platform_i2c_send_start( unsigned id ){
  625. i2c_master_start(id);
  626. }
  627. void platform_i2c_send_stop( unsigned id ){
  628. i2c_master_stop(id);
  629. }
  630. int platform_i2c_send_address( unsigned id, uint16_t address, int direction ){
  631. // Convert enum codes to R/w bit value.
  632. // If TX == 0 and RX == 1, this test will be removed by the compiler
  633. if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
  634. PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
  635. direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
  636. }
  637. return i2c_master_writeByte(id,
  638. (uint8_t) ((address << 1) + (direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ? 0 : 1))
  639. );
  640. }
  641. int platform_i2c_send_byte(unsigned id, uint8_t data ){
  642. return i2c_master_writeByte(id, data);
  643. }
  644. int platform_i2c_recv_byte( unsigned id, int ack ){
  645. return i2c_master_readByte(id, ack);
  646. }
  647. // *****************************************************************************
  648. // SPI platform interface
  649. uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div )
  650. {
  651. spi_master_init( id, cpol, cpha, clock_div );
  652. // all platform functions assume LSB order for MOSI & MISO buffer
  653. spi_mast_byte_order( id, SPI_ORDER_LSB );
  654. return 1;
  655. }
  656. int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
  657. {
  658. if (bitlen > 32)
  659. return PLATFORM_ERR;
  660. spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
  661. return PLATFORM_OK;
  662. }
  663. spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data )
  664. {
  665. if (bitlen > 32)
  666. return 0;
  667. spi_mast_set_mosi( id, 0, bitlen, data );
  668. spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
  669. return spi_mast_get_miso( id, 0, bitlen );
  670. }
  671. int platform_spi_blkwrite( uint8_t id, size_t len, const uint8_t *data )
  672. {
  673. while (len > 0) {
  674. size_t chunk_len = len > 64 ? 64 : len;
  675. spi_mast_blkset( id, chunk_len * 8, data );
  676. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, 0 );
  677. data = &(data[chunk_len]);
  678. len -= chunk_len;
  679. }
  680. return PLATFORM_OK;
  681. }
  682. int platform_spi_blkread( uint8_t id, size_t len, uint8_t *data )
  683. {
  684. uint8_t mosi_idle[64];
  685. os_memset( (void *)mosi_idle, 0xff, len > 64 ? 64 : len );
  686. while (len > 0 ) {
  687. size_t chunk_len = len > 64 ? 64 : len;
  688. spi_mast_blkset( id, chunk_len * 8, mosi_idle );
  689. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, -1 );
  690. spi_mast_blkget( id, chunk_len * 8, data );
  691. data = &(data[chunk_len]);
  692. len -= chunk_len;
  693. }
  694. return PLATFORM_OK;
  695. }
  696. int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
  697. uint8_t addr_bitlen, spi_data_type addr_data,
  698. uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen )
  699. {
  700. if ((cmd_bitlen > 16) ||
  701. (addr_bitlen > 32) ||
  702. (mosi_bitlen > 512) ||
  703. (dummy_bitlen > 256) ||
  704. (miso_bitlen > 512))
  705. return PLATFORM_ERR;
  706. spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
  707. return PLATFORM_OK;
  708. }
  709. // ****************************************************************************
  710. // Flash access functions
  711. /*
  712. * Assumptions:
  713. * > toaddr is INTERNAL_FLASH_WRITE_UNIT_SIZE aligned
  714. * > size is a multiple of INTERNAL_FLASH_WRITE_UNIT_SIZE
  715. */
  716. uint32_t platform_s_flash_write( const void *from, uint32_t toaddr, uint32_t size )
  717. {
  718. SpiFlashOpResult r;
  719. const uint32_t blkmask = INTERNAL_FLASH_WRITE_UNIT_SIZE - 1;
  720. uint32_t *apbuf = NULL;
  721. uint32_t fromaddr = (uint32_t)from;
  722. if( (fromaddr & blkmask ) || (fromaddr >= INTERNAL_FLASH_MAPPED_ADDRESS)) {
  723. apbuf = (uint32_t *)malloc(size);
  724. if(!apbuf)
  725. return 0;
  726. memcpy(apbuf, from, size);
  727. }
  728. system_soft_wdt_feed ();
  729. r = flash_write(toaddr, apbuf?(uint32_t *)apbuf:(uint32_t *)from, size);
  730. if(apbuf)
  731. free(apbuf);
  732. if(SPI_FLASH_RESULT_OK == r)
  733. return size;
  734. else{
  735. NODE_ERR( "ERROR in flash_write: r=%d at %p\n", r, toaddr);
  736. return 0;
  737. }
  738. }
  739. /*
  740. * Assumptions:
  741. * > fromaddr is INTERNAL_FLASH_READ_UNIT_SIZE aligned
  742. * > size is a multiple of INTERNAL_FLASH_READ_UNIT_SIZE
  743. */
  744. uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
  745. {
  746. if (size==0)
  747. return 0;
  748. SpiFlashOpResult r;
  749. system_soft_wdt_feed ();
  750. const uint32_t blkmask = (INTERNAL_FLASH_READ_UNIT_SIZE - 1);
  751. if( ((uint32_t)to) & blkmask )
  752. {
  753. uint32_t size2=size-INTERNAL_FLASH_READ_UNIT_SIZE;
  754. uint32_t* to2=(uint32_t*)((((uint32_t)to)&(~blkmask))+INTERNAL_FLASH_READ_UNIT_SIZE);
  755. r = flash_read(fromaddr, to2, size2);
  756. if(SPI_FLASH_RESULT_OK == r)
  757. {
  758. memmove(to,to2,size2); // This is overlapped so must be memmove and not memcpy
  759. char back[ INTERNAL_FLASH_READ_UNIT_SIZE ] __attribute__ ((aligned(INTERNAL_FLASH_READ_UNIT_SIZE)));
  760. r=flash_read(fromaddr+size2,(uint32*)back,INTERNAL_FLASH_READ_UNIT_SIZE);
  761. memcpy((uint8_t*)to+size2,back,INTERNAL_FLASH_READ_UNIT_SIZE);
  762. }
  763. }
  764. else
  765. r = flash_read(fromaddr, (uint32_t *)to, size);
  766. if(SPI_FLASH_RESULT_OK == r)
  767. return size;
  768. else{
  769. NODE_ERR( "ERROR in flash_read: r=%d at %p\n", r, fromaddr);
  770. return 0;
  771. }
  772. }
  773. int platform_flash_erase_sector( uint32_t sector_id )
  774. {
  775. NODE_DBG( "flash_erase_sector(%u)\n", sector_id);
  776. return flash_erase( sector_id ) == SPI_FLASH_RESULT_OK ? PLATFORM_OK : PLATFORM_ERR;
  777. }
  778. static uint32_t flash_map_meg_offset (void) {
  779. uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
  780. if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
  781. return -1;
  782. uint32_t m0 = (cache_ctrl & CACHE_FLASH_MAPPED0) ? 0x100000 : 0;
  783. uint32_t m1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 0x200000 : 0;
  784. return m0 + m1;
  785. }
  786. uint32_t platform_flash_mapped2phys (uint32_t mapped_addr) {
  787. uint32_t meg = flash_map_meg_offset();
  788. return (meg&1) ? -1 : mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg ;
  789. }
  790. uint32_t platform_flash_phys2mapped (uint32_t phys_addr) {
  791. uint32_t meg = flash_map_meg_offset();
  792. return (meg&1) ? -1 : phys_addr + INTERNAL_FLASH_MAPPED_ADDRESS - meg;
  793. }
  794. uint32_t platform_flash_get_partition (uint32_t part_id, uint32_t *addr) {
  795. partition_item_t pt = {0,0,0};
  796. system_partition_get_item(SYSTEM_PARTITION_CUSTOMER_BEGIN + part_id, &pt);
  797. if (addr) {
  798. *addr = pt.addr;
  799. }
  800. return pt.type == 0 ? 0 : pt.size;
  801. }
  802. /*
  803. * The Reboot Config Records are stored in the 4K flash page at offset 0x10000 (in
  804. * the linker section .irom0.ptable) and is used for configuration changes that
  805. * persist across reboots. This page contains a sequence of records, each of which
  806. * is word-aligned and comprises a header and body of length 0-64 words. The 4-byte
  807. * header comprises a length, a RCR id, and two zero fill bytes. These are written
  808. * using flash NAND writing rules, so any unused area (all 0xFF) can be overwritten
  809. * by a new record without needing to erase the RCR page. Ditto any existing
  810. * record can be marked as deleted by over-writing the header with the id set to
  811. * PLATFORM_RCR_DELETED (0x0). Note that the last word is not used additions so a
  812. * scan for PLATFORM_RCR_FREE will always terminate.
  813. *
  814. * The number of updates is extremely low, so it is unlikely (but possible) that
  815. * the page might fill with the churn of new RCRs, so in this case the write function
  816. * compacts the page by eliminating all deleted records. This does require a flash
  817. * sector erase.
  818. *
  819. * NOTE THAT THIS ALGO ISN'T 100% ROBUST, eg. a powerfail between the erase and the
  820. * wite-back will leave the page unitialised; ditto a powerfail between the record
  821. * appned and old deletion will leave two records. However this is better than the
  822. * general integrity of SPIFFS, for example and the vulnerable window is typically
  823. * less than 1 mSec every configuration change.
  824. */
  825. extern uint32_t _irom0_text_start[];
  826. #define RCR_WORD(i) (_irom0_text_start[i])
  827. #define WORDSIZE sizeof(uint32_t)
  828. #define FLASH_SECTOR_WORDS (INTERNAL_FLASH_SECTOR_SIZE/WORDSIZE)
  829. uint32_t platform_rcr_read (uint8_t rec_id, void **rec) {
  830. platform_rcr_t *rcr = (platform_rcr_t *) &RCR_WORD(0);
  831. uint32_t i = 0;
  832. /*
  833. * Chain down the RCR page looking for a record that matches the record
  834. * ID. If found return the size of the record and optionally its address.
  835. */
  836. while (1) {
  837. // copy RCR header into RAM to avoid unaligned exceptions
  838. platform_rcr_t r = (platform_rcr_t) RCR_WORD(i);
  839. if (r.id == rec_id) {
  840. if (rec) *rec = &RCR_WORD(i+1);
  841. return r.len * WORDSIZE;
  842. } else if (r.id == PLATFORM_RCR_FREE) {
  843. break;
  844. }
  845. i += 1 + r.len;
  846. }
  847. return ~0;
  848. }
  849. uint32_t platform_rcr_get_startup_option() {
  850. static uint32_t option = ~0;
  851. uint32_t *option_p;
  852. if (option == ~0) {
  853. option = 0;
  854. if (platform_rcr_read(PLATFORM_RCR_STARTUP_OPTION, (void **) &option_p) == sizeof(*option_p)) {
  855. option = *option_p;
  856. }
  857. }
  858. return option;
  859. }
  860. uint32_t platform_rcr_delete (uint8_t rec_id) {
  861. uint32_t *rec = NULL;
  862. platform_rcr_read(rec_id, (void**)&rec);
  863. if (rec) {
  864. uint32_t *pHdr = rec - 1; /* the header is the word proceeding the rec */
  865. platform_rcr_t hdr = {.hdr = *pHdr};
  866. hdr.id = PLATFORM_RCR_DELETED;
  867. platform_s_flash_write(&hdr, platform_flash_mapped2phys((uint32_t) pHdr), WORDSIZE);
  868. return 0;
  869. }
  870. return ~0;
  871. }
  872. /*
  873. * Chain down the RCR page and look for an existing record that matches the record
  874. * ID and the first free record. If there is enough room, then append the new
  875. * record and mark any previous record as deleted. If the page is full then GC,
  876. * erase the page and rewrite with the GCed content.
  877. */
  878. #define MAXREC 65
  879. uint32_t platform_rcr_write (uint8_t rec_id, const void *inrec, uint8_t n) {
  880. uint32_t nwords = (n+WORDSIZE-1) / WORDSIZE;
  881. uint32_t reclen = (nwords+1)*WORDSIZE;
  882. uint32_t *prev=NULL, *new = NULL;
  883. // make local stack copy of inrec including header and any trailing fill bytes
  884. uint32_t rec[MAXREC];
  885. if (nwords >= MAXREC)
  886. return ~0;
  887. rec[0] = 0; rec[nwords] = 0;
  888. ((platform_rcr_t *) rec)->id = rec_id;
  889. ((platform_rcr_t *) rec)->len = nwords;
  890. memcpy(rec+1, inrec, n); // let memcpy handle 0 and odd byte cases
  891. // find previous copy if any and exit if the replacement is the same value
  892. uint8_t np = platform_rcr_read (rec_id, (void **) &prev);
  893. if (prev && !os_memcmp(prev-1, rec, reclen))
  894. return n;
  895. // find next free slot
  896. platform_rcr_read (PLATFORM_RCR_FREE, (void **) &new);
  897. uint32_t nfree = &RCR_WORD(FLASH_SECTOR_WORDS) - new;
  898. // Is there enough room to fit the rec in the RCR page?
  899. if (nwords < nfree) { // Note inequality needed to leave at least one all set word
  900. uint32_t addr = platform_flash_mapped2phys((uint32_t)&new[-1]);
  901. platform_s_flash_write(rec, addr, reclen);
  902. if (prev) { // If a previous exists, then overwrite the hdr as DELETED
  903. platform_rcr_t rcr = {0};
  904. addr = platform_flash_mapped2phys((uint32_t)&prev[-1]);
  905. rcr.id = PLATFORM_RCR_DELETED; rcr.len = np/WORDSIZE;
  906. platform_s_flash_write(&rcr, addr, WORDSIZE);
  907. }
  908. } else {
  909. platform_rcr_t *rcr = (platform_rcr_t *) &RCR_WORD(0), newrcr = {0};
  910. uint32_t flash_addr = platform_flash_mapped2phys((uint32_t)&RCR_WORD(0));
  911. uint32_t *buf, i, l, pass;
  912. for (pass = 1; pass <= 2; pass++) {
  913. for (i = 0, l = 0; i < FLASH_SECTOR_WORDS - nfree; ) {
  914. platform_rcr_t r = rcr[i]; // again avoid unaligned exceptions
  915. if (r.id == PLATFORM_RCR_FREE)
  916. break;
  917. if (r.id != PLATFORM_RCR_DELETED && r.id != rec_id) {
  918. if (pass == 2) memcpy(buf + l, rcr + i, (r.len + 1)*WORDSIZE);
  919. l += r.len + 1;
  920. }
  921. i += r.len + 1;
  922. }
  923. if (pass == 2) memcpy(buf + l, rec, reclen);
  924. l += nwords + 1;
  925. if (pass == 1) buf = malloc(l * WORDSIZE);
  926. if (l >= FLASH_SECTOR_WORDS || !buf)
  927. return ~0;
  928. }
  929. platform_flash_erase_sector(flash_addr/INTERNAL_FLASH_SECTOR_SIZE);
  930. platform_s_flash_write(buf, flash_addr, l*WORDSIZE);
  931. free(buf);
  932. }
  933. return nwords*WORDSIZE;
  934. }
  935. void* platform_print_deprecation_note( const char *msg, const char *time_frame)
  936. {
  937. printf( "Warning, deprecated API! %s. It will be removed %s. See documentation for details.\n", msg, time_frame );
  938. }
  939. #define TH_MONIKER 0x68680000
  940. #define TH_MASK 0xFFF80000
  941. #define TH_UNMASK (~TH_MASK)
  942. #define TH_SHIFT 2
  943. #define TH_ALLOCATION_BRICK 4 // must be a power of 2
  944. #define TASK_DEFAULT_QUEUE_LEN 8
  945. #define TASK_PRIORITY_MASK 3
  946. #define TASK_PRIORITY_COUNT 3
  947. /*
  948. * Private struct to hold the 3 event task queues and the dispatch callbacks
  949. */
  950. static struct taskQblock {
  951. os_event_t *task_Q[TASK_PRIORITY_COUNT];
  952. platform_task_callback_t *task_func;
  953. int task_count;
  954. } TQB = {0};
  955. static void platform_task_dispatch (os_event_t *e) {
  956. platform_task_handle_t handle = e->sig;
  957. if ( (handle & TH_MASK) == TH_MONIKER) {
  958. uint16_t entry = (handle & TH_UNMASK) >> TH_SHIFT;
  959. uint8_t priority = handle & TASK_PRIORITY_MASK;
  960. if ( priority <= PLATFORM_TASK_PRIORITY_HIGH &&
  961. TQB.task_func &&
  962. entry < TQB.task_count ){
  963. /* call the registered task handler with the specified parameter and priority */
  964. TQB.task_func[entry](e->par, priority);
  965. return;
  966. }
  967. }
  968. /* Invalid signals are ignored */
  969. NODE_DBG ( "Invalid signal issued: %08x", handle);
  970. }
  971. /*
  972. * Initialise the task handle callback for a given priority.
  973. */
  974. static int task_init_handler (void) {
  975. int p, qlen = TASK_DEFAULT_QUEUE_LEN;
  976. for (p = 0; p < TASK_PRIORITY_COUNT; p++){
  977. TQB.task_Q[p] = (os_event_t *) malloc( sizeof(os_event_t)*qlen );
  978. if (TQB.task_Q[p]) {
  979. os_memset(TQB.task_Q[p], 0, sizeof(os_event_t)*qlen);
  980. system_os_task(platform_task_dispatch, p, TQB.task_Q[p], TASK_DEFAULT_QUEUE_LEN);
  981. } else {
  982. NODE_DBG ( "Malloc failure in platform_task_init_handler" );
  983. return PLATFORM_ERR;
  984. }
  985. }
  986. }
  987. /*
  988. * Allocate a task handle in the relevant TCB.task_Q. Note that these Qs are resized
  989. * as needed growing in 4 unit bricks. No GC is adopted so handles are permanently
  990. * allocated during boot life. This isn't an issue in practice as only a few handles
  991. * are created per priority during application init and the more volitile Lua tasks
  992. * are allocated in the Lua registery using the luaX interface which is layered on
  993. * this mechanism.
  994. */
  995. platform_task_handle_t platform_task_get_id (platform_task_callback_t t) {
  996. if ( (TQB.task_count & (TH_ALLOCATION_BRICK - 1)) == 0 ) {
  997. TQB.task_func = (platform_task_callback_t *) realloc(
  998. TQB.task_func,
  999. sizeof(platform_task_callback_t) * (TQB.task_count+TH_ALLOCATION_BRICK));
  1000. if (!TQB.task_func) {
  1001. NODE_DBG ( "Malloc failure in platform_task_get_id");
  1002. return 0;
  1003. }
  1004. os_memset (TQB.task_func+TQB.task_count, 0,
  1005. sizeof(platform_task_callback_t)*TH_ALLOCATION_BRICK);
  1006. }
  1007. TQB.task_func[TQB.task_count++] = t;
  1008. return TH_MONIKER + ((TQB.task_count-1) << TH_SHIFT);
  1009. }