hw_timer.c 18 KB

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  1. /******************************************************************************
  2. * Copyright 2013-2014 Espressif Systems (Wuxi)
  3. *
  4. * FileName: hw_timer.c
  5. *
  6. * Description: hw_timer driver
  7. *
  8. * Modification history:
  9. * 2014/5/1, v1.0 create this file.
  10. *
  11. * Adapted for NodeMCU 2016
  12. *
  13. * The owner parameter should be a unique value per module using this API
  14. * It could be a pointer to a bit of data or code
  15. * e.g. #define OWNER ((os_param_t) module_init)
  16. * where module_init is a function. For builtin modules, it might be
  17. * a small numeric value that is known not to clash.
  18. *******************************************************************************/
  19. #include "platform.h"
  20. #include <stdio.h>
  21. #include <stdlib.h>
  22. #include "ets_sys.h"
  23. #include "os_type.h"
  24. #include "osapi.h"
  25. #include "hw_timer.h"
  26. //#define DEBUG_HW_TIMER
  27. //#undef NODE_DBG
  28. //#define NODE_DBG dbg_printf
  29. #define FRC1_ENABLE_TIMER BIT7
  30. #define FRC1_AUTO_LOAD BIT6
  31. //TIMER PREDIVIDED MODE
  32. typedef enum {
  33. DIVIDED_BY_1 = 0, //timer clock
  34. DIVIDED_BY_16 = 4, //divided by 16
  35. DIVIDED_BY_256 = 8, //divided by 256
  36. } TIMER_PREDIVIDED_MODE;
  37. typedef enum { //timer interrupt mode
  38. TM_LEVEL_INT = 1, // level interrupt
  39. TM_EDGE_INT = 0, //edge interrupt
  40. } TIMER_INT_MODE;
  41. /*
  42. * This represents a single user of the timer functionality. It is keyed by the owner
  43. * field.
  44. */
  45. typedef struct _timer_user {
  46. struct _timer_user *next;
  47. bool autoload;
  48. int32_t delay; // once on the active list, this is difference in delay from the preceding element
  49. int32_t autoload_delay;
  50. uint32_t expected_interrupt_time;
  51. os_param_t owner;
  52. os_param_t callback_arg;
  53. void (* user_hw_timer_cb)(os_param_t);
  54. #ifdef DEBUG_HW_TIMER
  55. int cb_count;
  56. #endif
  57. } timer_user;
  58. /*
  59. * There are two lists of timer_user blocks. The active list are those which are waiting
  60. * for timeouts to happen, and the inactive list contains idle blocks. Unfortunately
  61. * there isn't a way to clean up the inactive blocks as some modules call the
  62. * close method from interrupt level.
  63. */
  64. static timer_user *active;
  65. static timer_user *inactive;
  66. /*
  67. * There are a fair number of places when interrupts need to be disabled as many of
  68. * the methods can be called from interrupt level. The lock/unlock calls support
  69. * multiple LOCKs and then the same number of UNLOCKs are required to re-enable
  70. * interrupts. This is imolemeted by counting the number of times that lock is called.
  71. */
  72. static uint8_t lock_count;
  73. static uint8_t timer_running;
  74. static uint32_t time_next_expiry;
  75. static int32_t last_timer_load;
  76. #define LOCK() do { ets_intr_lock(); lock_count++; } while (0)
  77. #define UNLOCK() if (--lock_count == 0) ets_intr_unlock()
  78. /*
  79. * It is possible to reserve the timer exclusively, for one module alone.
  80. * This way the interrupt overhead is minimal.
  81. * Drawback is that no other module can use the timer at same time.
  82. * If flag if true, indicates someone reserved the timer exclusively.
  83. * Unline shared used (default), only one client can reserve exclusively.
  84. */
  85. static bool reserved_exclusively = false;
  86. /*
  87. * To start a timer, you write to FRCI_LOAD_ADDRESS, and that starts the counting
  88. * down. When it reaches zero, the interrupt fires -- but the counting continues.
  89. * The counter is 23 bits wide. The current value of the counter can be read
  90. * at FRC1_COUNT_ADDRESS. The unit is 200ns, and so it takes somewhat over a second
  91. * to wrap the counter.
  92. */
  93. #ifdef DEBUG_HW_TIMER
  94. void ICACHE_RAM_ATTR hw_timer_debug() {
  95. dbg_printf("timer_running=%d\n", timer_running);
  96. timer_user *tu;
  97. for (tu = active; tu; tu = tu->next) {
  98. dbg_printf("Owner: 0x%x, delay=%d, autoload=%d, autoload_delay=%d, cb_count=%d\n",
  99. tu->owner, tu->delay, tu->autoload, tu->autoload_delay, tu->cb_count);
  100. }
  101. }
  102. #endif
  103. static void ICACHE_RAM_ATTR set_timer(int delay, const char *caller) {
  104. if (delay < 1) {
  105. delay = 1;
  106. }
  107. int32_t time_left = (RTC_REG_READ(FRC1_COUNT_ADDRESS)) & ((1 << 23) - 1);
  108. RTC_REG_WRITE(FRC1_LOAD_ADDRESS, delay);
  109. if (time_left > last_timer_load) {
  110. // We have missed the interrupt
  111. time_left -= 1 << 23;
  112. }
  113. NODE_DBG("%s(%x): time_next=%d, left=%d (load=%d), delay=%d => %d\n", caller, active->owner, time_next_expiry, time_left, last_timer_load, delay, time_next_expiry - time_left + delay);
  114. time_next_expiry = time_next_expiry - time_left + delay;
  115. last_timer_load = delay;
  116. timer_running = 1;
  117. }
  118. static void ICACHE_RAM_ATTR adjust_root() {
  119. // Can only ge called with interrupts disabled
  120. // change the initial active delay so that relative stuff still works
  121. // Also, set the last_timer_load to be now
  122. int32_t time_left = (RTC_REG_READ(FRC1_COUNT_ADDRESS)) & ((1 << 23) - 1);
  123. if (time_left > last_timer_load) {
  124. // We have missed the interrupt
  125. time_left -= 1 << 23;
  126. }
  127. if (active && timer_running) {
  128. active->delay = time_left;
  129. }
  130. if (active) {
  131. NODE_DBG("adjust(%x): time_left=%d (last_load=%d)\n", active->owner, time_left, last_timer_load);
  132. } else {
  133. NODE_DBG("adjust: time_left=%d (last_load=%d)\n", time_left, last_timer_load);
  134. }
  135. last_timer_load = time_left;
  136. }
  137. /*
  138. * Find the timer_user block for this owner. This just returns
  139. * a pointer to the block, or NULL.
  140. */
  141. static timer_user * ICACHE_RAM_ATTR find_tu(os_param_t owner) {
  142. // Try the inactive chain first
  143. timer_user **p;
  144. LOCK();
  145. for (p = &inactive; *p; p = &((*p)->next)) {
  146. if ((*p)->owner == owner) {
  147. timer_user *result = *p;
  148. UNLOCK();
  149. return result;
  150. }
  151. }
  152. for (p = &active; *p; p = &((*p)->next)) {
  153. if ((*p)->owner == owner) {
  154. timer_user *result = *p;
  155. UNLOCK();
  156. return result;
  157. }
  158. }
  159. UNLOCK();
  160. return NULL;
  161. }
  162. /*
  163. * Find the timer_user block for this owner. This just returns
  164. * a pointer to the block, or NULL. If it finds the block, then it is
  165. * removed from whichever chain it is on. Note that this may require
  166. * triggering a timer.
  167. */
  168. static timer_user * ICACHE_RAM_ATTR find_tu_and_remove(os_param_t owner) {
  169. // Try the inactive chain first
  170. timer_user **p;
  171. LOCK();
  172. for (p = &inactive; *p; p = &((*p)->next)) {
  173. if ((*p)->owner == owner) {
  174. timer_user *result = *p;
  175. *p = result->next;
  176. result->next = NULL;
  177. UNLOCK();
  178. return result;
  179. }
  180. }
  181. for (p = &active; *p; p = &((*p)->next)) {
  182. if ((*p)->owner == owner) {
  183. timer_user *result = *p;
  184. bool need_to_reset = (result == active) && result->next;
  185. if (need_to_reset) {
  186. adjust_root();
  187. }
  188. // Increase the delay on the next element
  189. if (result->next) {
  190. result->next->delay += result->delay;
  191. }
  192. // Cut out of chain
  193. *p = result->next;
  194. result->next = NULL;
  195. if (need_to_reset) {
  196. set_timer(active->delay, "find_tu");
  197. }
  198. UNLOCK();
  199. return result;
  200. }
  201. }
  202. UNLOCK();
  203. return NULL;
  204. }
  205. /*
  206. * This inserts a timer_user block into the active chain. This is a sightly
  207. * complex process as it can involve triggering a timer load.
  208. */
  209. static void ICACHE_RAM_ATTR insert_active_tu(timer_user *tu) {
  210. timer_user **p;
  211. LOCK();
  212. tu->expected_interrupt_time = time_next_expiry - last_timer_load + tu->delay;
  213. for (p = &active; *p; p = &((*p)->next)) {
  214. if ((*p)->delay >= tu->delay) {
  215. break;
  216. }
  217. tu->delay -= (*p)->delay;
  218. }
  219. if (*p) {
  220. (*p)->delay -= tu->delay;
  221. }
  222. tu->next = *p;
  223. *p = tu;
  224. if (tu == active) {
  225. // We have a new leader
  226. set_timer(active->delay, "insert_active");
  227. }
  228. UNLOCK();
  229. }
  230. /******************************************************************************
  231. * FunctionName : platform_hw_timer_arm_ticks
  232. * Description : set a trigger timer delay for this timer.
  233. * Parameters : os_param_t owner
  234. * uint32 ticks :
  235. * Returns : true if it worked
  236. *******************************************************************************/
  237. bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks(os_param_t owner, uint32_t ticks)
  238. {
  239. if (reserved_exclusively) return false;
  240. timer_user *tu = find_tu_and_remove(owner);
  241. if (!tu) {
  242. return false;
  243. }
  244. tu->delay = ticks;
  245. tu->autoload_delay = ticks;
  246. NODE_DBG("arm(%x): ticks=%d\n", owner, ticks);
  247. LOCK();
  248. adjust_root();
  249. insert_active_tu(tu);
  250. UNLOCK();
  251. return true;
  252. }
  253. /******************************************************************************
  254. * FunctionName : platform_hw_timer_arm_us
  255. * Description : set a trigger timer delay for this timer.
  256. * Parameters : os_param_t owner
  257. * uint32 microseconds :
  258. * in autoload mode
  259. * 50 ~ 0x7fffff; for FRC1 source.
  260. * 100 ~ 0x7fffff; for NMI source.
  261. * in non autoload mode:
  262. * 10 ~ 0x7fffff;
  263. * Returns : true if it worked
  264. *******************************************************************************/
  265. bool ICACHE_RAM_ATTR platform_hw_timer_arm_us(os_param_t owner, uint32_t microseconds)
  266. {
  267. return platform_hw_timer_arm_ticks(owner, US_TO_RTC_TIMER_TICKS(microseconds));
  268. }
  269. /******************************************************************************
  270. * FunctionName : platform_hw_timer_set_func
  271. * Description : set the func, when trigger timer is up.
  272. * Parameters : os_param_t owner
  273. * void (* user_hw_timer_cb_set)(os_param_t):
  274. timer callback function
  275. * os_param_t arg
  276. * Returns : true if it worked
  277. *******************************************************************************/
  278. bool platform_hw_timer_set_func(os_param_t owner, void (* user_hw_timer_cb_set)(os_param_t), os_param_t arg)
  279. {
  280. if (reserved_exclusively) return false;
  281. timer_user *tu = find_tu(owner);
  282. if (!tu) {
  283. return false;
  284. }
  285. tu->callback_arg = arg;
  286. tu->user_hw_timer_cb = user_hw_timer_cb_set;
  287. NODE_DBG("set-CB(%x): %x, %x\n", tu->owner, tu->user_hw_timer_cb, tu->callback_arg);
  288. return true;
  289. }
  290. /*
  291. * This is the timer ISR. It has to find the timer that was running and trigger the callback
  292. * for that timer. By this stage, the next timer may have expired as well, and so the process
  293. * iterates. Note that if there is an autoload timer, then it should be restarted immediately.
  294. * Also, the callbacks typically do re-arm the timer, so we have to be careful not to
  295. * assume that nothing changes during the callback.
  296. */
  297. static void ICACHE_RAM_ATTR hw_timer_isr_cb(void *arg)
  298. {
  299. bool keep_going = true;
  300. adjust_root();
  301. timer_running = 0;
  302. while (keep_going && active) {
  303. keep_going = false;
  304. timer_user *fired = active;
  305. active = fired->next;
  306. if (fired->autoload) {
  307. fired->expected_interrupt_time += fired->autoload_delay;
  308. fired->delay = fired->expected_interrupt_time - (time_next_expiry - last_timer_load);
  309. insert_active_tu(fired);
  310. if (active->delay <= 0) {
  311. keep_going = true;
  312. }
  313. } else {
  314. fired->next = inactive;
  315. inactive = fired;
  316. if (active) {
  317. active->delay += fired->delay;
  318. if (active->delay <= 0) {
  319. keep_going = true;
  320. }
  321. }
  322. }
  323. if (fired->user_hw_timer_cb) {
  324. #ifdef DEBUG_HW_TIMER
  325. fired->cb_count++;
  326. #endif
  327. NODE_DBG("CB(%x): %x, %x\n", fired->owner, fired->user_hw_timer_cb, fired->callback_arg);
  328. (*(fired->user_hw_timer_cb))(fired->callback_arg);
  329. }
  330. }
  331. if (active && !timer_running) {
  332. set_timer(active->delay, "isr");
  333. }
  334. }
  335. static void ICACHE_RAM_ATTR hw_timer_nmi_cb(void)
  336. {
  337. hw_timer_isr_cb(NULL);
  338. }
  339. /******************************************************************************
  340. * FunctionName : platform_hw_timer_get_delay_ticks
  341. * Description : figure out how long since th last timer interrupt
  342. * Parameters : os_param_t owner
  343. * Returns : the number of ticks
  344. *******************************************************************************/
  345. uint32_t ICACHE_RAM_ATTR platform_hw_timer_get_delay_ticks(os_param_t owner)
  346. {
  347. if (reserved_exclusively) return 0;
  348. timer_user *tu = find_tu(owner);
  349. if (!tu) {
  350. return 0;
  351. }
  352. LOCK();
  353. adjust_root();
  354. UNLOCK();
  355. int ret = (time_next_expiry - last_timer_load) - tu->expected_interrupt_time;
  356. if (ret < 0) {
  357. NODE_DBG("delay ticks = %d, last_timer_load=%d, tu->expected_int=%d, next_exp=%d\n", ret, last_timer_load, tu->expected_interrupt_time, time_next_expiry);
  358. }
  359. return ret < 0 ? 0 : ret;
  360. }
  361. /******************************************************************************
  362. * FunctionName : platform_hw_timer_init
  363. * Description : initialize the hardware isr timer for shared use i.e. multiple owners.
  364. * Parameters : os_param_t owner
  365. * FRC1_TIMER_SOURCE_TYPE source_type:
  366. * FRC1_SOURCE, timer use frc1 isr as isr source.
  367. * NMI_SOURCE, timer use nmi isr as isr source.
  368. * bool autoload:
  369. * 0, not autoload,
  370. * 1, autoload mode,
  371. * Returns : true if it worked
  372. *******************************************************************************/
  373. bool platform_hw_timer_init(os_param_t owner, FRC1_TIMER_SOURCE_TYPE source_type, bool autoload)
  374. {
  375. if (reserved_exclusively) return false;
  376. timer_user *tu = find_tu_and_remove(owner);
  377. if (!tu) {
  378. tu = (timer_user *) malloc(sizeof(*tu));
  379. if (!tu) {
  380. return false;
  381. }
  382. memset(tu, 0, sizeof(*tu));
  383. tu->owner = owner;
  384. }
  385. tu->autoload = autoload;
  386. if (!active && !inactive) {
  387. RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
  388. DIVIDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
  389. ETS_FRC_TIMER1_INTR_ATTACH(hw_timer_isr_cb, NULL);
  390. TM1_EDGE_INT_ENABLE();
  391. ETS_FRC1_INTR_ENABLE();
  392. }
  393. LOCK();
  394. tu->next = inactive;
  395. inactive = tu;
  396. UNLOCK();
  397. return true;
  398. }
  399. /******************************************************************************
  400. * FunctionName : platform_hw_timer_close
  401. * Description : ends use of the hardware isr timer.
  402. * Parameters : os_param_t owner.
  403. * Returns : true if it worked
  404. *******************************************************************************/
  405. bool ICACHE_RAM_ATTR platform_hw_timer_close(os_param_t owner)
  406. {
  407. if (reserved_exclusively) return false;
  408. timer_user *tu = find_tu_and_remove(owner);
  409. if (tu) {
  410. if (tu == inactive) {
  411. inactive == NULL;
  412. } else {
  413. LOCK();
  414. tu->next = inactive;
  415. inactive = tu;
  416. UNLOCK();
  417. }
  418. }
  419. // This will never actually run....
  420. if (!active && !inactive) {
  421. /* Set no reload mode */
  422. RTC_REG_WRITE(FRC1_CTRL_ADDRESS,
  423. DIVIDED_BY_16 | TM_EDGE_INT);
  424. TM1_EDGE_INT_DISABLE();
  425. ETS_FRC1_INTR_DISABLE();
  426. }
  427. return true;
  428. }
  429. /******************************************************************************
  430. * FunctionName : platform_hw_timer_init_exclusive
  431. * Description : initialize the hardware isr timer for exclusive use by the caller.
  432. * Parameters : FRC1_TIMER_SOURCE_TYPE source_type:
  433. * FRC1_SOURCE, timer use frc1 isr as isr source.
  434. * NMI_SOURCE, timer use nmi isr as isr source.
  435. * bool autoload:
  436. * 0, not autoload,
  437. * 1, autoload mode,
  438. * void (* frc1_timer_cb)(os_param_t): timer callback function when FRC1_SOURCE is being used
  439. * os_param_t arg : argument passed to frc1_timer_cb or NULL
  440. * void (* nmi_timer_cb)(void) : timer callback function when NMI_SOURCE is being used
  441. * Returns : true if it worked, false if the timer is already served for shared or exclusive use
  442. *******************************************************************************/
  443. bool platform_hw_timer_init_exclusive(
  444. FRC1_TIMER_SOURCE_TYPE source_type,
  445. bool autoload,
  446. void (* frc1_timer_cb)(os_param_t),
  447. os_param_t arg,
  448. void (*nmi_timer_cb)(void)
  449. )
  450. {
  451. if (active || inactive) return false;
  452. if (reserved_exclusively) return false;
  453. reserved_exclusively = true;
  454. RTC_REG_WRITE(FRC1_CTRL_ADDRESS, (autoload ? FRC1_AUTO_LOAD : 0) | DIVIDED_BY_16 | FRC1_ENABLE_TIMER | TM_EDGE_INT);
  455. if (source_type == NMI_SOURCE) {
  456. ETS_FRC_TIMER1_NMI_INTR_ATTACH(nmi_timer_cb);
  457. } else {
  458. ETS_FRC_TIMER1_INTR_ATTACH((void (*)(void *))frc1_timer_cb, (void*)arg);
  459. }
  460. TM1_EDGE_INT_ENABLE();
  461. ETS_FRC1_INTR_ENABLE();
  462. return true;
  463. }
  464. /******************************************************************************
  465. * FunctionName : platform_hw_timer_close_exclusive
  466. * Description : ends use of the hardware isr timer in exclusive mode.
  467. * Parameters :
  468. * Returns : true if it worked
  469. *******************************************************************************/
  470. bool ICACHE_RAM_ATTR platform_hw_timer_close_exclusive()
  471. {
  472. if (!reserved_exclusively) return true;
  473. reserved_exclusively = false;
  474. /* Set no reload mode */
  475. RTC_REG_WRITE(FRC1_CTRL_ADDRESS, DIVIDED_BY_16 | TM_EDGE_INT);
  476. TM1_EDGE_INT_DISABLE();
  477. ETS_FRC1_INTR_DISABLE();
  478. return true;
  479. }
  480. /******************************************************************************
  481. * FunctionName : platform_hw_timer_arm_ticks_exclusive
  482. * Description : set a trigger timer delay for this timer.
  483. * Parameters : uint32 ticks :
  484. * Returns : true if it worked
  485. *******************************************************************************/
  486. bool ICACHE_RAM_ATTR platform_hw_timer_arm_ticks_exclusive(uint32_t ticks)
  487. {
  488. RTC_REG_WRITE(FRC1_LOAD_ADDRESS, ticks);
  489. return true;
  490. }
  491. /******************************************************************************
  492. * FunctionName : platform_hw_timer_arm_us_exclusive
  493. * Description : set a trigger timer delay for this timer.
  494. * Parameters : uint32 microseconds :
  495. * in autoload mode
  496. * 50 ~ 0x7fffff; for FRC1 source.
  497. * 100 ~ 0x7fffff; for NMI source.
  498. * in non autoload mode:
  499. * 10 ~ 0x7fffff;
  500. * Returns : true if it worked
  501. *******************************************************************************/
  502. bool ICACHE_RAM_ATTR platform_hw_timer_arm_us_exclusive(uint32_t microseconds)
  503. {
  504. RTC_REG_WRITE(FRC1_LOAD_ADDRESS, US_TO_RTC_TIMER_TICKS(microseconds));
  505. return true;
  506. }