platform.c 24 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940
  1. // Platform-dependent functions and includes
  2. #include "platform.h"
  3. #include "common.h"
  4. #include "c_stdio.h"
  5. #include "c_string.h"
  6. #include "c_stdlib.h"
  7. #include "llimits.h"
  8. #include "gpio.h"
  9. #include "user_interface.h"
  10. #include "driver/gpio16.h"
  11. #include "driver/i2c_master.h"
  12. #include "driver/spi.h"
  13. #include "driver/uart.h"
  14. #include "driver/sigma_delta.h"
  15. #ifdef GPIO_INTERRUPT_ENABLE
  16. static task_handle_t gpio_task_handle;
  17. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  18. struct gpio_hook_entry {
  19. platform_hook_function func;
  20. uint32_t bits;
  21. };
  22. struct gpio_hook {
  23. struct gpio_hook_entry *entry;
  24. uint32_t all_bits;
  25. uint32_t count;
  26. };
  27. static struct gpio_hook platform_gpio_hook;
  28. #endif
  29. #endif
  30. static const int uart_bitrates[] = {
  31. BIT_RATE_300,
  32. BIT_RATE_600,
  33. BIT_RATE_1200,
  34. BIT_RATE_2400,
  35. BIT_RATE_4800,
  36. BIT_RATE_9600,
  37. BIT_RATE_19200,
  38. BIT_RATE_38400,
  39. BIT_RATE_57600,
  40. BIT_RATE_74880,
  41. BIT_RATE_115200,
  42. BIT_RATE_230400,
  43. BIT_RATE_256000,
  44. BIT_RATE_460800,
  45. BIT_RATE_921600,
  46. BIT_RATE_1843200,
  47. BIT_RATE_3686400
  48. };
  49. int platform_init()
  50. {
  51. // Setup the various forward and reverse mappings for the pins
  52. get_pin_map();
  53. cmn_platform_init();
  54. // All done
  55. return PLATFORM_OK;
  56. }
  57. // ****************************************************************************
  58. // KEY_LED functions
  59. uint8_t platform_key_led( uint8_t level){
  60. uint8_t temp;
  61. gpio16_output_set(1); // set to high first, for reading key low level
  62. gpio16_input_conf();
  63. temp = gpio16_input_get();
  64. gpio16_output_conf();
  65. gpio16_output_set(level);
  66. return temp;
  67. }
  68. // ****************************************************************************
  69. // GPIO functions
  70. /*
  71. * Set GPIO mode to output. Optionally in RAM helper because interrupts are dsabled
  72. */
  73. static void NO_INTR_CODE set_gpio_no_interrupt(uint8 pin, uint8_t push_pull) {
  74. unsigned pnum = pin_num[pin];
  75. ETS_GPIO_INTR_DISABLE();
  76. #ifdef GPIO_INTERRUPT_ENABLE
  77. pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
  78. #endif
  79. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  80. //disable interrupt
  81. gpio_pin_intr_state_set(GPIO_ID_PIN(pnum), GPIO_PIN_INTR_DISABLE);
  82. //clear interrupt status
  83. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pnum));
  84. // configure push-pull vs open-drain
  85. if (push_pull) {
  86. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  87. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) &
  88. (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
  89. } else {
  90. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  91. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) |
  92. GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //enable open drain;
  93. }
  94. ETS_GPIO_INTR_ENABLE();
  95. }
  96. /*
  97. * Set GPIO mode to interrupt. Optionally RAM helper because interrupts are dsabled
  98. */
  99. #ifdef GPIO_INTERRUPT_ENABLE
  100. static void NO_INTR_CODE set_gpio_interrupt(uint8 pin) {
  101. ETS_GPIO_INTR_DISABLE();
  102. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  103. GPIO_DIS_OUTPUT(pin_num[pin]);
  104. gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  105. GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
  106. | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
  107. | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
  108. ETS_GPIO_INTR_ENABLE();
  109. }
  110. #endif
  111. int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
  112. {
  113. NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n", pin_mux[pin], pin_func[pin]);
  114. if (pin >= NUM_GPIO)
  115. return -1;
  116. if(pin == 0){
  117. if(mode==PLATFORM_GPIO_INPUT)
  118. gpio16_input_conf();
  119. else
  120. gpio16_output_conf();
  121. return 1;
  122. }
  123. #ifdef LUA_USE_MODULES_PWM
  124. platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
  125. #endif
  126. if (pull == PLATFORM_GPIO_PULLUP) {
  127. PIN_PULLUP_EN(pin_mux[pin]);
  128. } else {
  129. PIN_PULLUP_DIS(pin_mux[pin]);
  130. }
  131. switch(mode){
  132. case PLATFORM_GPIO_INPUT:
  133. GPIO_DIS_OUTPUT(pin_num[pin]);
  134. /* run on */
  135. case PLATFORM_GPIO_OUTPUT:
  136. set_gpio_no_interrupt(pin, TRUE);
  137. break;
  138. case PLATFORM_GPIO_OPENDRAIN:
  139. set_gpio_no_interrupt(pin, FALSE);
  140. break;
  141. #ifdef GPIO_INTERRUPT_ENABLE
  142. case PLATFORM_GPIO_INT:
  143. set_gpio_interrupt(pin);
  144. break;
  145. #endif
  146. default:
  147. break;
  148. }
  149. return 1;
  150. }
  151. int platform_gpio_write( unsigned pin, unsigned level )
  152. {
  153. // NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
  154. if (pin >= NUM_GPIO)
  155. return -1;
  156. if(pin == 0){
  157. gpio16_output_conf();
  158. gpio16_output_set(level);
  159. return 1;
  160. }
  161. GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
  162. }
  163. int platform_gpio_read( unsigned pin )
  164. {
  165. // NODE_DBG("Function platform_gpio_read() is called. pin:%d\n",GPIO_ID_PIN(pin_num[pin]));
  166. if (pin >= NUM_GPIO)
  167. return -1;
  168. if(pin == 0){
  169. // gpio16_input_conf();
  170. return 0x1 & gpio16_input_get();
  171. }
  172. // GPIO_DIS_OUTPUT(pin_num[pin]);
  173. return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
  174. }
  175. #ifdef GPIO_INTERRUPT_ENABLE
  176. static void ICACHE_RAM_ATTR platform_gpio_intr_dispatcher (void *dummy){
  177. uint32 j=0;
  178. uint32 gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  179. uint32 now = system_get_time();
  180. UNUSED(dummy);
  181. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  182. if (gpio_status & platform_gpio_hook.all_bits) {
  183. for (j = 0; j < platform_gpio_hook.count; j++) {
  184. if (gpio_status & platform_gpio_hook.entry[j].bits)
  185. gpio_status = (platform_gpio_hook.entry[j].func)(gpio_status);
  186. }
  187. }
  188. #endif
  189. /*
  190. * gpio_status is a bit map where bit 0 is set if unmapped gpio pin 0 (pin3) has
  191. * triggered the ISR. bit 1 if unmapped gpio pin 1 (pin10=U0TXD), etc. Since this
  192. * is the ISR, it makes sense to optimize this by doing a fast scan of the status
  193. * and reverse mapping any set bits.
  194. */
  195. for (j = 0; gpio_status>0; j++, gpio_status >>= 1) {
  196. if (gpio_status&1) {
  197. int i = pin_num_inv[j];
  198. if (pin_int_type[i]) {
  199. //disable interrupt
  200. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  201. //clear interrupt status
  202. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  203. uint32 level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(j));
  204. task_post_high (gpio_task_handle, (now << 8) + (i<<1) + level);
  205. // We re-enable the interrupt when we execute the callback
  206. }
  207. }
  208. }
  209. }
  210. void platform_gpio_init( task_handle_t gpio_task )
  211. {
  212. gpio_task_handle = gpio_task;
  213. ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, NULL);
  214. }
  215. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  216. /*
  217. * Register an ISR hook to be called from the GPIO ISR for a given GPIO bitmask.
  218. * This routine is only called a few times so has been optimised for size and
  219. * the unregister is a special case when the bits are 0.
  220. *
  221. * Each hook function can only be registered once. If it is re-registered
  222. * then the hooked bits are just updated to the new value.
  223. */
  224. int platform_gpio_register_intr_hook(uint32_t bits, platform_hook_function hook)
  225. {
  226. struct gpio_hook nh, oh = platform_gpio_hook;
  227. int i, j;
  228. if (!hook) {
  229. // Cannot register or unregister null hook
  230. return 0;
  231. }
  232. int delete_slot = -1;
  233. // If hook already registered, just update the bits
  234. for (i=0; i<oh.count; i++) {
  235. if (hook == oh.entry[i].func) {
  236. if (!bits) {
  237. // Unregister if move to zero bits
  238. delete_slot = i;
  239. break;
  240. }
  241. if (bits & (oh.all_bits & ~oh.entry[i].bits)) {
  242. // Attempt to hook an already hooked bit
  243. return 0;
  244. }
  245. // Update the hooked bits (in the right order)
  246. uint32_t old_bits = oh.entry[i].bits;
  247. *(volatile uint32_t *) &oh.entry[i].bits = bits;
  248. *(volatile uint32_t *) &oh.all_bits = (oh.all_bits & ~old_bits) | bits;
  249. return 1;
  250. }
  251. }
  252. // This must be the register new hook / delete old hook
  253. if (delete_slot < 0) {
  254. if (bits & oh.all_bits) {
  255. return 0; // Attempt to hook already hooked bits
  256. }
  257. nh.count = oh.count + 1; // register a new hook
  258. } else {
  259. nh.count = oh.count - 1; // unregister an old hook
  260. }
  261. // These return NULL if the count = 0 so only error check if > 0)
  262. nh.entry = c_malloc( nh.count * sizeof(*(nh.entry)) );
  263. if (nh.count && !(nh.entry)) {
  264. return 0; // Allocation failure
  265. }
  266. for (i=0, j=0; i<oh.count; i++) {
  267. // Don't copy if this is the entry to delete
  268. if (i != delete_slot) {
  269. nh.entry[j++] = oh.entry[i];
  270. }
  271. }
  272. if (delete_slot < 0) { // for a register add the hook to the tail and set the all bits
  273. nh.entry[j].bits = bits;
  274. nh.entry[j].func = hook;
  275. nh.all_bits = oh.all_bits | bits;
  276. } else { // for an unregister clear the matching all bits
  277. nh.all_bits = oh.all_bits & (~oh.entry[delete_slot].bits);
  278. }
  279. ETS_GPIO_INTR_DISABLE();
  280. // This is a structure copy, so interrupts need to be disabled
  281. platform_gpio_hook = nh;
  282. ETS_GPIO_INTR_ENABLE();
  283. c_free(oh.entry);
  284. return 1;
  285. }
  286. #endif // GPIO_INTERRUPT_HOOK_ENABLE
  287. /*
  288. * Initialise GPIO interrupt mode. Optionally in RAM because interrupts are dsabled
  289. */
  290. void NO_INTR_CODE platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
  291. {
  292. if (platform_gpio_exists(pin)) {
  293. ETS_GPIO_INTR_DISABLE();
  294. //clear interrupt status
  295. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  296. pin_int_type[pin] = type;
  297. //enable interrupt
  298. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
  299. ETS_GPIO_INTR_ENABLE();
  300. }
  301. }
  302. #endif
  303. // ****************************************************************************
  304. // UART
  305. // TODO: Support timeouts.
  306. // UartDev is defined and initialized in rom code.
  307. extern UartDevice UartDev;
  308. uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits )
  309. {
  310. switch( baud )
  311. {
  312. case BIT_RATE_300:
  313. case BIT_RATE_600:
  314. case BIT_RATE_1200:
  315. case BIT_RATE_2400:
  316. case BIT_RATE_4800:
  317. case BIT_RATE_9600:
  318. case BIT_RATE_19200:
  319. case BIT_RATE_38400:
  320. case BIT_RATE_57600:
  321. case BIT_RATE_74880:
  322. case BIT_RATE_115200:
  323. case BIT_RATE_230400:
  324. case BIT_RATE_256000:
  325. case BIT_RATE_460800:
  326. case BIT_RATE_921600:
  327. case BIT_RATE_1843200:
  328. case BIT_RATE_3686400:
  329. UartDev.baut_rate = baud;
  330. break;
  331. default:
  332. UartDev.baut_rate = BIT_RATE_9600;
  333. break;
  334. }
  335. switch( databits )
  336. {
  337. case 5:
  338. UartDev.data_bits = FIVE_BITS;
  339. break;
  340. case 6:
  341. UartDev.data_bits = SIX_BITS;
  342. break;
  343. case 7:
  344. UartDev.data_bits = SEVEN_BITS;
  345. break;
  346. case 8:
  347. UartDev.data_bits = EIGHT_BITS;
  348. break;
  349. default:
  350. UartDev.data_bits = EIGHT_BITS;
  351. break;
  352. }
  353. switch (stopbits)
  354. {
  355. case PLATFORM_UART_STOPBITS_1_5:
  356. UartDev.stop_bits = ONE_HALF_STOP_BIT;
  357. break;
  358. case PLATFORM_UART_STOPBITS_2:
  359. UartDev.stop_bits = TWO_STOP_BIT;
  360. break;
  361. default:
  362. UartDev.stop_bits = ONE_STOP_BIT;
  363. break;
  364. }
  365. switch (parity)
  366. {
  367. case PLATFORM_UART_PARITY_EVEN:
  368. UartDev.parity = EVEN_BITS;
  369. UartDev.exist_parity = STICK_PARITY_EN;
  370. break;
  371. case PLATFORM_UART_PARITY_ODD:
  372. UartDev.parity = ODD_BITS;
  373. UartDev.exist_parity = STICK_PARITY_EN;
  374. break;
  375. default:
  376. UartDev.parity = NONE_BITS;
  377. UartDev.exist_parity = STICK_PARITY_DIS;
  378. break;
  379. }
  380. uart_setup(id);
  381. return baud;
  382. }
  383. void platform_uart_get_config(unsigned id, uint32_t *baudp, uint32_t *databitsp, uint32_t *parityp, uint32_t *stopbitsp) {
  384. UartConfig config = uart_get_config(id);
  385. int i;
  386. int offset = config.baut_rate;
  387. for (i = 0; i < sizeof(uart_bitrates) / sizeof(uart_bitrates[0]); i++) {
  388. int diff = config.baut_rate - uart_bitrates[i];
  389. if (diff < 0) {
  390. diff = -diff;
  391. }
  392. if (diff < offset) {
  393. offset = diff;
  394. *baudp = uart_bitrates[i];
  395. }
  396. }
  397. switch( config.data_bits )
  398. {
  399. case FIVE_BITS:
  400. *databitsp = 5;
  401. break;
  402. case SIX_BITS:
  403. *databitsp = 6;
  404. break;
  405. case SEVEN_BITS:
  406. *databitsp = 7;
  407. break;
  408. case EIGHT_BITS:
  409. default:
  410. *databitsp = 8;
  411. break;
  412. }
  413. switch (config.stop_bits)
  414. {
  415. case ONE_HALF_STOP_BIT:
  416. *stopbitsp = PLATFORM_UART_STOPBITS_1_5;
  417. break;
  418. case TWO_STOP_BIT:
  419. *stopbitsp = PLATFORM_UART_STOPBITS_2;
  420. break;
  421. default:
  422. *stopbitsp = PLATFORM_UART_STOPBITS_1;
  423. break;
  424. }
  425. if (config.exist_parity == STICK_PARITY_DIS) {
  426. *parityp = PLATFORM_UART_PARITY_NONE;
  427. } else if (config.parity == EVEN_BITS) {
  428. *parityp = PLATFORM_UART_PARITY_EVEN;
  429. } else {
  430. *parityp = PLATFORM_UART_PARITY_ODD;
  431. }
  432. }
  433. // if set=1, then alternate serial output pins are used. (15=rx, 13=tx)
  434. void platform_uart_alt( int set )
  435. {
  436. uart0_alt( set );
  437. return;
  438. }
  439. // Send: version with and without mux
  440. void platform_uart_send( unsigned id, u8 data )
  441. {
  442. uart_tx_one_char(id, data);
  443. }
  444. // ****************************************************************************
  445. // PWMs
  446. static uint16_t pwms_duty[NUM_PWM] = {0};
  447. void platform_pwm_init()
  448. {
  449. int i;
  450. for(i=0;i<NUM_PWM;i++){
  451. pwms_duty[i] = DUTY(0);
  452. }
  453. pwm_init(500, NULL);
  454. // NODE_DBG("Function pwms_init() is called.\n");
  455. }
  456. // Return the PWM clock
  457. // NOTE: Can't find a function to query for the period set for the timer,
  458. // therefore using the struct.
  459. // This may require adjustment if driver libraries are updated.
  460. uint32_t platform_pwm_get_clock( unsigned pin )
  461. {
  462. // NODE_DBG("Function platform_pwm_get_clock() is called.\n");
  463. if( pin >= NUM_PWM)
  464. return 0;
  465. if(!pwm_exist(pin))
  466. return 0;
  467. return (uint32_t)pwm_get_freq(pin);
  468. }
  469. // Set the PWM clock
  470. uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
  471. {
  472. // NODE_DBG("Function platform_pwm_set_clock() is called.\n");
  473. if( pin >= NUM_PWM)
  474. return 0;
  475. if(!pwm_exist(pin))
  476. return 0;
  477. pwm_set_freq((uint16_t)clock, pin);
  478. pwm_start();
  479. return (uint32_t)pwm_get_freq( pin );
  480. }
  481. uint32_t platform_pwm_get_duty( unsigned pin )
  482. {
  483. // NODE_DBG("Function platform_pwm_get_duty() is called.\n");
  484. if( pin < NUM_PWM){
  485. if(!pwm_exist(pin))
  486. return 0;
  487. // return NORMAL_DUTY(pwm_get_duty(pin));
  488. return pwms_duty[pin];
  489. }
  490. return 0;
  491. }
  492. // Set the PWM duty
  493. uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
  494. {
  495. // NODE_DBG("Function platform_pwm_set_duty() is called.\n");
  496. if ( pin < NUM_PWM)
  497. {
  498. if(!pwm_exist(pin))
  499. return 0;
  500. pwm_set_duty(DUTY(duty), pin);
  501. } else {
  502. return 0;
  503. }
  504. pwm_start();
  505. pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
  506. return pwms_duty[pin];
  507. }
  508. uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
  509. {
  510. uint32_t clock;
  511. if ( pin < NUM_PWM)
  512. {
  513. platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
  514. if(!pwm_add(pin))
  515. return 0;
  516. // pwm_set_duty(DUTY(duty), pin);
  517. pwm_set_duty(0, pin);
  518. pwms_duty[pin] = duty;
  519. pwm_set_freq((uint16_t)frequency, pin);
  520. } else {
  521. return 0;
  522. }
  523. clock = platform_pwm_get_clock( pin );
  524. if (!pwm_start()) {
  525. return 0;
  526. }
  527. return clock;
  528. }
  529. void platform_pwm_close( unsigned pin )
  530. {
  531. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  532. if ( pin < NUM_PWM)
  533. {
  534. pwm_delete(pin);
  535. pwm_start();
  536. }
  537. }
  538. bool platform_pwm_start( unsigned pin )
  539. {
  540. // NODE_DBG("Function platform_pwm_start() is called.\n");
  541. if ( pin < NUM_PWM)
  542. {
  543. if(!pwm_exist(pin))
  544. return FALSE;
  545. pwm_set_duty(DUTY(pwms_duty[pin]), pin);
  546. return pwm_start();
  547. }
  548. return FALSE;
  549. }
  550. void platform_pwm_stop( unsigned pin )
  551. {
  552. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  553. if ( pin < NUM_PWM)
  554. {
  555. if(!pwm_exist(pin))
  556. return;
  557. pwm_set_duty(0, pin);
  558. pwm_start();
  559. }
  560. }
  561. // *****************************************************************************
  562. // Sigma-Delta platform interface
  563. uint8_t platform_sigma_delta_setup( uint8_t pin )
  564. {
  565. if (pin < 1 || pin > NUM_GPIO)
  566. return 0;
  567. sigma_delta_setup();
  568. // set GPIO output mode for this pin
  569. platform_gpio_mode( pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT );
  570. platform_gpio_write( pin, PLATFORM_GPIO_LOW );
  571. // enable sigma-delta on this pin
  572. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  573. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  574. GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
  575. return 1;
  576. }
  577. uint8_t platform_sigma_delta_close( uint8_t pin )
  578. {
  579. if (pin < 1 || pin > NUM_GPIO)
  580. return 0;
  581. sigma_delta_stop();
  582. // set GPIO input mode for this pin
  583. platform_gpio_mode( pin, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP );
  584. // CONNECT GPIO TO PIN PAD
  585. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  586. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  587. GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
  588. return 1;
  589. }
  590. void platform_sigma_delta_set_pwmduty( uint8_t duty )
  591. {
  592. uint8_t target = 0, prescale = 0;
  593. target = duty > 128 ? 256 - duty : duty;
  594. prescale = target == 0 ? 0 : target-1;
  595. //freq = 80000 (khz) /256 /duty_target * (prescale+1)
  596. sigma_delta_set_prescale_target( prescale, duty );
  597. }
  598. void platform_sigma_delta_set_prescale( uint8_t prescale )
  599. {
  600. sigma_delta_set_prescale_target( prescale, -1 );
  601. }
  602. void ICACHE_RAM_ATTR platform_sigma_delta_set_target( uint8_t target )
  603. {
  604. sigma_delta_set_prescale_target( -1, target );
  605. }
  606. // *****************************************************************************
  607. // I2C platform interface
  608. uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed ){
  609. if (sda >= NUM_GPIO || scl >= NUM_GPIO)
  610. return 0;
  611. // platform_pwm_close(sda);
  612. // platform_pwm_close(scl);
  613. // disable gpio interrupt first
  614. platform_gpio_mode(sda, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // inside this func call platform_pwm_close
  615. platform_gpio_mode(scl, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // disable gpio interrupt first
  616. i2c_master_gpio_init(sda, scl);
  617. return PLATFORM_I2C_SPEED_SLOW;
  618. }
  619. void platform_i2c_send_start( unsigned id ){
  620. i2c_master_start();
  621. }
  622. void platform_i2c_send_stop( unsigned id ){
  623. i2c_master_stop();
  624. }
  625. int platform_i2c_send_address( unsigned id, uint16_t address, int direction ){
  626. // Convert enum codes to R/w bit value.
  627. // If TX == 0 and RX == 1, this test will be removed by the compiler
  628. if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
  629. PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
  630. direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
  631. }
  632. i2c_master_writeByte( (uint8_t) ((address << 1) | direction ));
  633. // Low-level returns nack (0=acked); we return ack (1=acked).
  634. return ! i2c_master_getAck();
  635. }
  636. int platform_i2c_send_byte( unsigned id, uint8_t data ){
  637. i2c_master_writeByte(data);
  638. // Low-level returns nack (0=acked); we return ack (1=acked).
  639. return ! i2c_master_getAck();
  640. }
  641. int platform_i2c_recv_byte( unsigned id, int ack ){
  642. uint8_t r = i2c_master_readByte();
  643. i2c_master_setAck( !ack );
  644. return r;
  645. }
  646. // *****************************************************************************
  647. // SPI platform interface
  648. uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div )
  649. {
  650. spi_master_init( id, cpol, cpha, clock_div );
  651. return 1;
  652. }
  653. int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
  654. {
  655. if (bitlen > 32)
  656. return PLATFORM_ERR;
  657. spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
  658. return PLATFORM_OK;
  659. }
  660. spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data )
  661. {
  662. if (bitlen > 32)
  663. return 0;
  664. spi_mast_set_mosi( id, 0, bitlen, data );
  665. spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
  666. return spi_mast_get_miso( id, 0, bitlen );
  667. }
  668. int platform_spi_blkwrite( uint8_t id, size_t len, const uint8_t *data )
  669. {
  670. spi_mast_byte_order( id, SPI_ORDER_LSB );
  671. while (len > 0) {
  672. size_t chunk_len = len > 64 ? 64 : len;
  673. spi_mast_blkset( id, chunk_len * 8, data );
  674. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, 0 );
  675. data = &(data[chunk_len]);
  676. len -= chunk_len;
  677. }
  678. spi_mast_byte_order( id, SPI_ORDER_MSB );
  679. return PLATFORM_OK;
  680. }
  681. int platform_spi_blkread( uint8_t id, size_t len, uint8_t *data )
  682. {
  683. uint8_t mosi_idle[64];
  684. os_memset( (void *)mosi_idle, 0xff, len > 64 ? 64 : len );
  685. spi_mast_byte_order( id, SPI_ORDER_LSB );
  686. while (len > 0 ) {
  687. size_t chunk_len = len > 64 ? 64 : len;
  688. spi_mast_blkset( id, chunk_len * 8, mosi_idle );
  689. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, -1 );
  690. spi_mast_blkget( id, chunk_len * 8, data );
  691. data = &(data[chunk_len]);
  692. len -= chunk_len;
  693. }
  694. spi_mast_byte_order( id, SPI_ORDER_MSB );
  695. return PLATFORM_OK;
  696. }
  697. int platform_spi_set_mosi( uint8_t id, uint16_t offset, uint8_t bitlen, spi_data_type data )
  698. {
  699. if (offset + bitlen > 512)
  700. return PLATFORM_ERR;
  701. spi_mast_set_mosi( id, offset, bitlen, data );
  702. return PLATFORM_OK;
  703. }
  704. spi_data_type platform_spi_get_miso( uint8_t id, uint16_t offset, uint8_t bitlen )
  705. {
  706. if (offset + bitlen > 512)
  707. return 0;
  708. return spi_mast_get_miso( id, offset, bitlen );
  709. }
  710. int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
  711. uint8_t addr_bitlen, spi_data_type addr_data,
  712. uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen )
  713. {
  714. if ((cmd_bitlen > 16) ||
  715. (addr_bitlen > 32) ||
  716. (mosi_bitlen > 512) ||
  717. (dummy_bitlen > 256) ||
  718. (miso_bitlen > 512))
  719. return PLATFORM_ERR;
  720. spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
  721. return PLATFORM_OK;
  722. }
  723. // ****************************************************************************
  724. // Flash access functions
  725. /*
  726. * Assumptions:
  727. * > toaddr is INTERNAL_FLASH_WRITE_UNIT_SIZE aligned
  728. * > size is a multiple of INTERNAL_FLASH_WRITE_UNIT_SIZE
  729. */
  730. uint32_t platform_s_flash_write( const void *from, uint32_t toaddr, uint32_t size )
  731. {
  732. SpiFlashOpResult r;
  733. const uint32_t blkmask = INTERNAL_FLASH_WRITE_UNIT_SIZE - 1;
  734. uint32_t *apbuf = NULL;
  735. uint32_t fromaddr = (uint32_t)from;
  736. if( (fromaddr & blkmask ) || (fromaddr >= INTERNAL_FLASH_MAPPED_ADDRESS)) {
  737. apbuf = (uint32_t *)c_malloc(size);
  738. if(!apbuf)
  739. return 0;
  740. c_memcpy(apbuf, from, size);
  741. }
  742. system_soft_wdt_feed ();
  743. r = flash_write(toaddr, apbuf?(uint32 *)apbuf:(uint32 *)from, size);
  744. if(apbuf)
  745. c_free(apbuf);
  746. if(SPI_FLASH_RESULT_OK == r)
  747. return size;
  748. else{
  749. NODE_ERR( "ERROR in flash_write: r=%d at %08X\n", ( int )r, ( unsigned )toaddr);
  750. return 0;
  751. }
  752. }
  753. /*
  754. * Assumptions:
  755. * > fromaddr is INTERNAL_FLASH_READ_UNIT_SIZE aligned
  756. * > size is a multiple of INTERNAL_FLASH_READ_UNIT_SIZE
  757. */
  758. uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
  759. {
  760. if (size==0)
  761. return 0;
  762. SpiFlashOpResult r;
  763. system_soft_wdt_feed ();
  764. const uint32_t blkmask = (INTERNAL_FLASH_READ_UNIT_SIZE - 1);
  765. if( ((uint32_t)to) & blkmask )
  766. {
  767. uint32_t size2=size-INTERNAL_FLASH_READ_UNIT_SIZE;
  768. uint32* to2=(uint32*)((((uint32_t)to)&(~blkmask))+INTERNAL_FLASH_READ_UNIT_SIZE);
  769. r = flash_read(fromaddr, to2, size2);
  770. if(SPI_FLASH_RESULT_OK == r)
  771. {
  772. os_memmove(to,to2,size2);
  773. char back[ INTERNAL_FLASH_READ_UNIT_SIZE ] __attribute__ ((aligned(INTERNAL_FLASH_READ_UNIT_SIZE)));
  774. r=flash_read(fromaddr+size2,(uint32*)back,INTERNAL_FLASH_READ_UNIT_SIZE);
  775. os_memcpy((uint8_t*)to+size2,back,INTERNAL_FLASH_READ_UNIT_SIZE);
  776. }
  777. }
  778. else
  779. r = flash_read(fromaddr, (uint32 *)to, size);
  780. if(SPI_FLASH_RESULT_OK == r)
  781. return size;
  782. else{
  783. NODE_ERR( "ERROR in flash_read: r=%d at %08X\n", ( int )r, ( unsigned )fromaddr);
  784. return 0;
  785. }
  786. }
  787. int platform_flash_erase_sector( uint32_t sector_id )
  788. {
  789. system_soft_wdt_feed ();
  790. return flash_erase( sector_id ) == SPI_FLASH_RESULT_OK ? PLATFORM_OK : PLATFORM_ERR;
  791. }
  792. uint32_t platform_flash_mapped2phys (uint32_t mapped_addr)
  793. {
  794. uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
  795. if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
  796. return -1;
  797. bool b0 = (cache_ctrl & CACHE_FLASH_MAPPED0) ? 1 : 0;
  798. bool b1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 1 : 0;
  799. uint32_t meg = (b1 << 1) | b0;
  800. return mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg * 0x100000;
  801. }