eagle_soc.h 5.4 KB

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  1. #ifndef _SDK_OVERRIDE_EAGLE_SOC_H_
  2. #define _SDK_OVERRIDE_EAGLE_SOC_H_
  3. #include_next "eagle_soc.h"
  4. #define GPIO_AS_PIN_SOURCE 0
  5. #define SIGMA_AS_PIN_SOURCE (~GPIO_AS_PIN_SOURCE)
  6. #define GPIO_SIGMA_DELTA 0x00000068 //defined in gpio register.xls
  7. #define GPIO_SIGMA_DELTA_SETTING_MASK (0x00000001ff)
  8. #define GPIO_SIGMA_DELTA_ENABLE 1
  9. #define GPIO_SIGMA_DELTA_DISABLE (~GPIO_SIGMA_DELTA_ENABLE)
  10. #define GPIO_SIGMA_DELTA_MSB 16
  11. #define GPIO_SIGMA_DELTA_LSB 16
  12. #define GPIO_SIGMA_DELTA_MASK (0x00000001<<GPIO_SIGMA_DELTA_LSB)
  13. #define GPIO_SIGMA_DELTA_GET(x) (((x) & GPIO_SIGMA_DELTA_MASK) >> GPIO_SIGMA_DELTA_LSB)
  14. #define GPIO_SIGMA_DELTA_SET(x) (((x) << GPIO_SIGMA_DELTA_LSB) & GPIO_SIGMA_DELTA_MASK)
  15. #define GPIO_SIGMA_DELTA_TARGET_MSB 7
  16. #define GPIO_SIGMA_DELTA_TARGET_LSB 0
  17. #define GPIO_SIGMA_DELTA_TARGET_MASK (0x000000FF<<GPIO_SIGMA_DELTA_TARGET_LSB)
  18. #define GPIO_SIGMA_DELTA_TARGET_GET(x) (((x) & GPIO_SIGMA_DELTA_TARGET_MASK) >> GPIO_SIGMA_DELTA_TARGET_LSB)
  19. #define GPIO_SIGMA_DELTA_TARGET_SET(x) (((x) << GPIO_SIGMA_DELTA_TARGET_LSB) & GPIO_SIGMA_DELTA_TARGET_MASK)
  20. #define GPIO_SIGMA_DELTA_PRESCALE_MSB 15
  21. #define GPIO_SIGMA_DELTA_PRESCALE_LSB 8
  22. #define GPIO_SIGMA_DELTA_PRESCALE_MASK (0x000000FF<<GPIO_SIGMA_DELTA_PRESCALE_LSB)
  23. #define GPIO_SIGMA_DELTA_PRESCALE_GET(x) (((x) & GPIO_SIGMA_DELTA_PRESCALE_MASK) >> GPIO_SIGMA_DELTA_PRESCALE_LSB)
  24. #define GPIO_SIGMA_DELTA_PRESCALE_SET(x) (((x) << GPIO_SIGMA_DELTA_PRESCALE_LSB) & GPIO_SIGMA_DELTA_PRESCALE_MASK)
  25. //Peripheral device base address define{{
  26. #define PERIPHS_DPORT_BASEADDR 0x3ff00000
  27. #define PERIPHS_GPIO_BASEADDR 0x60000300
  28. #define PERIPHS_TIMER_BASEDDR 0x60000600
  29. #define PERIPHS_RTC_BASEADDR 0x60000700
  30. #define PERIPHS_IO_MUX 0x60000800
  31. //}}
  32. // TIMER reg {{
  33. #define RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr)
  34. #define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val)
  35. #define RTC_CLR_REG_MASK(reg, mask) CLEAR_PERI_REG_MASK(PERIPHS_TIMER_BASEDDR +reg, mask)
  36. /* Returns the current time according to the timer timer. */
  37. #define NOW() RTC_REG_READ(FRC2_COUNT_ADDRESS)
  38. //load initial_value to timer1
  39. #define FRC1_LOAD_ADDRESS 0x00
  40. //timer1's counter value(count from initial_value to 0)
  41. #define FRC1_COUNT_ADDRESS 0x04
  42. #define FRC1_CTRL_ADDRESS 0x08
  43. //clear timer1's interrupt when write this address
  44. #define FRC1_INT_ADDRESS 0x0c
  45. #define FRC1_INT_CLR_MASK 0x00000001
  46. //timer2's counter value(count from initial_value to 0)
  47. #define FRC2_COUNT_ADDRESS 0x24
  48. // }}
  49. #define RTC_REG_READ(addr) READ_PERI_REG(PERIPHS_TIMER_BASEDDR + addr)
  50. #define RTC_REG_WRITE(addr, val) WRITE_PERI_REG(PERIPHS_TIMER_BASEDDR + addr, val)
  51. #define PERIPHS_IO_MUX_CONF_U (PERIPHS_IO_MUX + 0x00)
  52. #define SPI0_CLK_EQU_SYS_CLK BIT8
  53. #define SPI1_CLK_EQU_SYS_CLK BIT9
  54. #define PERIPHS_IO_MUX_MTDI_U (PERIPHS_IO_MUX + 0x04)
  55. #define FUNC_GPIO12 3
  56. #define PERIPHS_IO_MUX_MTCK_U (PERIPHS_IO_MUX + 0x08)
  57. #define FUNC_GPIO13 3
  58. #define PERIPHS_IO_MUX_MTMS_U (PERIPHS_IO_MUX + 0x0C)
  59. #define FUNC_GPIO14 3
  60. #define PERIPHS_IO_MUX_MTDO_U (PERIPHS_IO_MUX + 0x10)
  61. #define FUNC_GPIO15 3
  62. #define FUNC_U0RTS 4
  63. #define PERIPHS_IO_MUX_U0RXD_U (PERIPHS_IO_MUX + 0x14)
  64. #define FUNC_GPIO3 3
  65. #define PERIPHS_IO_MUX_U0TXD_U (PERIPHS_IO_MUX + 0x18)
  66. #define FUNC_U0TXD 0
  67. #define FUNC_GPIO1 3
  68. #define PERIPHS_IO_MUX_SD_CLK_U (PERIPHS_IO_MUX + 0x1c)
  69. #define FUNC_SDCLK 0
  70. #define FUNC_SPICLK 1
  71. #define PERIPHS_IO_MUX_SD_DATA0_U (PERIPHS_IO_MUX + 0x20)
  72. #define FUNC_SDDATA0 0
  73. #define FUNC_SPIQ 1
  74. #define FUNC_U1TXD 4
  75. #define PERIPHS_IO_MUX_SD_DATA1_U (PERIPHS_IO_MUX + 0x24)
  76. #define FUNC_SDDATA1 0
  77. #define FUNC_SPID 1
  78. #define FUNC_U1RXD 4
  79. #define FUNC_SDDATA1_U1RXD 7
  80. #define PERIPHS_IO_MUX_SD_DATA2_U (PERIPHS_IO_MUX + 0x28)
  81. #define FUNC_SDDATA2 0
  82. #define FUNC_SPIHD 1
  83. #define FUNC_GPIO9 3
  84. #define PERIPHS_IO_MUX_SD_DATA3_U (PERIPHS_IO_MUX + 0x2c)
  85. #define FUNC_SDDATA3 0
  86. #define FUNC_SPIWP 1
  87. #define FUNC_GPIO10 3
  88. #define PERIPHS_IO_MUX_SD_CMD_U (PERIPHS_IO_MUX + 0x30)
  89. #define FUNC_SDCMD 0
  90. #define FUNC_SPICS0 1
  91. #define PERIPHS_IO_MUX_GPIO0_U (PERIPHS_IO_MUX + 0x34)
  92. #define FUNC_GPIO0 0
  93. #define PERIPHS_IO_MUX_GPIO2_U (PERIPHS_IO_MUX + 0x38)
  94. #define FUNC_GPIO2 0
  95. #define FUNC_U1TXD_BK 2
  96. #define FUNC_U0TXD_BK 4
  97. #define PERIPHS_IO_MUX_GPIO4_U (PERIPHS_IO_MUX + 0x3C)
  98. #define FUNC_GPIO4 0
  99. #define PERIPHS_IO_MUX_GPIO5_U (PERIPHS_IO_MUX + 0x40)
  100. #define FUNC_GPIO5 0
  101. #endif