platform.c 24 KB

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  1. // Platform-dependent functions and includes
  2. #include "platform.h"
  3. #include "common.h"
  4. #include "c_stdio.h"
  5. #include "c_string.h"
  6. #include "c_stdlib.h"
  7. #include "llimits.h"
  8. #include "gpio.h"
  9. #include "user_interface.h"
  10. #include "driver/gpio16.h"
  11. #include "driver/i2c_master.h"
  12. #include "driver/spi.h"
  13. #include "driver/uart.h"
  14. #include "driver/sigma_delta.h"
  15. #define INTERRUPT_TYPE_IS_LEVEL(x) ((x) >= GPIO_PIN_INTR_LOLEVEL)
  16. #ifdef GPIO_INTERRUPT_ENABLE
  17. static task_handle_t gpio_task_handle;
  18. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  19. struct gpio_hook_entry {
  20. platform_hook_function func;
  21. uint32_t bits;
  22. };
  23. struct gpio_hook {
  24. struct gpio_hook_entry *entry;
  25. uint32_t all_bits;
  26. uint32_t count;
  27. };
  28. static struct gpio_hook platform_gpio_hook;
  29. #endif
  30. #endif
  31. static const int uart_bitrates[] = {
  32. BIT_RATE_300,
  33. BIT_RATE_600,
  34. BIT_RATE_1200,
  35. BIT_RATE_2400,
  36. BIT_RATE_4800,
  37. BIT_RATE_9600,
  38. BIT_RATE_19200,
  39. BIT_RATE_31250,
  40. BIT_RATE_38400,
  41. BIT_RATE_57600,
  42. BIT_RATE_74880,
  43. BIT_RATE_115200,
  44. BIT_RATE_230400,
  45. BIT_RATE_256000,
  46. BIT_RATE_460800,
  47. BIT_RATE_921600,
  48. BIT_RATE_1843200,
  49. BIT_RATE_3686400
  50. };
  51. int platform_init()
  52. {
  53. // Setup the various forward and reverse mappings for the pins
  54. get_pin_map();
  55. cmn_platform_init();
  56. // All done
  57. return PLATFORM_OK;
  58. }
  59. // ****************************************************************************
  60. // KEY_LED functions
  61. uint8_t platform_key_led( uint8_t level){
  62. uint8_t temp;
  63. gpio16_output_set(1); // set to high first, for reading key low level
  64. gpio16_input_conf();
  65. temp = gpio16_input_get();
  66. gpio16_output_conf();
  67. gpio16_output_set(level);
  68. return temp;
  69. }
  70. // ****************************************************************************
  71. // GPIO functions
  72. /*
  73. * Set GPIO mode to output. Optionally in RAM helper because interrupts are dsabled
  74. */
  75. static void NO_INTR_CODE set_gpio_no_interrupt(uint8 pin, uint8_t push_pull) {
  76. unsigned pnum = pin_num[pin];
  77. ETS_GPIO_INTR_DISABLE();
  78. #ifdef GPIO_INTERRUPT_ENABLE
  79. pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
  80. #endif
  81. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  82. //disable interrupt
  83. gpio_pin_intr_state_set(GPIO_ID_PIN(pnum), GPIO_PIN_INTR_DISABLE);
  84. //clear interrupt status
  85. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pnum));
  86. // configure push-pull vs open-drain
  87. if (push_pull) {
  88. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  89. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) &
  90. (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
  91. } else {
  92. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  93. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) |
  94. GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //enable open drain;
  95. }
  96. ETS_GPIO_INTR_ENABLE();
  97. }
  98. /*
  99. * Set GPIO mode to interrupt. Optionally RAM helper because interrupts are dsabled
  100. */
  101. #ifdef GPIO_INTERRUPT_ENABLE
  102. static void NO_INTR_CODE set_gpio_interrupt(uint8 pin) {
  103. ETS_GPIO_INTR_DISABLE();
  104. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  105. GPIO_DIS_OUTPUT(pin_num[pin]);
  106. gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  107. GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
  108. | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
  109. | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
  110. ETS_GPIO_INTR_ENABLE();
  111. }
  112. #endif
  113. int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
  114. {
  115. NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n", pin_mux[pin], pin_func[pin]);
  116. if (pin >= NUM_GPIO)
  117. return -1;
  118. if(pin == 0){
  119. if(mode==PLATFORM_GPIO_INPUT)
  120. gpio16_input_conf();
  121. else
  122. gpio16_output_conf();
  123. return 1;
  124. }
  125. #ifdef LUA_USE_MODULES_PWM
  126. platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
  127. #endif
  128. if (pull == PLATFORM_GPIO_PULLUP) {
  129. PIN_PULLUP_EN(pin_mux[pin]);
  130. } else {
  131. PIN_PULLUP_DIS(pin_mux[pin]);
  132. }
  133. switch(mode){
  134. case PLATFORM_GPIO_INPUT:
  135. GPIO_DIS_OUTPUT(pin_num[pin]);
  136. /* run on */
  137. case PLATFORM_GPIO_OUTPUT:
  138. set_gpio_no_interrupt(pin, TRUE);
  139. break;
  140. case PLATFORM_GPIO_OPENDRAIN:
  141. set_gpio_no_interrupt(pin, FALSE);
  142. break;
  143. #ifdef GPIO_INTERRUPT_ENABLE
  144. case PLATFORM_GPIO_INT:
  145. set_gpio_interrupt(pin);
  146. break;
  147. #endif
  148. default:
  149. break;
  150. }
  151. return 1;
  152. }
  153. int platform_gpio_write( unsigned pin, unsigned level )
  154. {
  155. // NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
  156. if (pin >= NUM_GPIO)
  157. return -1;
  158. if(pin == 0){
  159. gpio16_output_conf();
  160. gpio16_output_set(level);
  161. return 1;
  162. }
  163. GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
  164. }
  165. int platform_gpio_read( unsigned pin )
  166. {
  167. // NODE_DBG("Function platform_gpio_read() is called. pin:%d\n",GPIO_ID_PIN(pin_num[pin]));
  168. if (pin >= NUM_GPIO)
  169. return -1;
  170. if(pin == 0){
  171. // gpio16_input_conf();
  172. return 0x1 & gpio16_input_get();
  173. }
  174. // GPIO_DIS_OUTPUT(pin_num[pin]);
  175. return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
  176. }
  177. #ifdef GPIO_INTERRUPT_ENABLE
  178. static void ICACHE_RAM_ATTR platform_gpio_intr_dispatcher (void *dummy){
  179. uint32 j=0;
  180. uint32 gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  181. uint32 now = system_get_time();
  182. UNUSED(dummy);
  183. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  184. if (gpio_status & platform_gpio_hook.all_bits) {
  185. for (j = 0; j < platform_gpio_hook.count; j++) {
  186. if (gpio_status & platform_gpio_hook.entry[j].bits)
  187. gpio_status = (platform_gpio_hook.entry[j].func)(gpio_status);
  188. }
  189. }
  190. #endif
  191. /*
  192. * gpio_status is a bit map where bit 0 is set if unmapped gpio pin 0 (pin3) has
  193. * triggered the ISR. bit 1 if unmapped gpio pin 1 (pin10=U0TXD), etc. Since this
  194. * is the ISR, it makes sense to optimize this by doing a fast scan of the status
  195. * and reverse mapping any set bits.
  196. */
  197. for (j = 0; gpio_status>0; j++, gpio_status >>= 1) {
  198. if (gpio_status&1) {
  199. int i = pin_num_inv[j];
  200. if (pin_int_type[i]) {
  201. uint16_t diff = pin_counter[i].seen ^ pin_counter[i].reported;
  202. pin_counter[i].seen = 0x7fff & (pin_counter[i].seen + 1);
  203. if (INTERRUPT_TYPE_IS_LEVEL(pin_int_type[i])) {
  204. //disable interrupt
  205. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  206. }
  207. //clear interrupt status
  208. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  209. if (diff == 0 || diff & 0x8000) {
  210. uint32 level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(j));
  211. if (!task_post_high (gpio_task_handle, (now << 8) + (i<<1) + level)) {
  212. // If we fail to post, then try on the next interrupt
  213. pin_counter[i].seen |= 0x8000;
  214. }
  215. // We re-enable the interrupt when we execute the callback (if level)
  216. }
  217. } else {
  218. // this is an unexpected interrupt so shut it off for now
  219. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  220. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  221. }
  222. }
  223. }
  224. }
  225. void platform_gpio_init( task_handle_t gpio_task )
  226. {
  227. gpio_task_handle = gpio_task;
  228. ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, NULL);
  229. }
  230. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  231. /*
  232. * Register an ISR hook to be called from the GPIO ISR for a given GPIO bitmask.
  233. * This routine is only called a few times so has been optimised for size and
  234. * the unregister is a special case when the bits are 0.
  235. *
  236. * Each hook function can only be registered once. If it is re-registered
  237. * then the hooked bits are just updated to the new value.
  238. */
  239. int platform_gpio_register_intr_hook(uint32_t bits, platform_hook_function hook)
  240. {
  241. struct gpio_hook nh, oh = platform_gpio_hook;
  242. int i, j;
  243. if (!hook) {
  244. // Cannot register or unregister null hook
  245. return 0;
  246. }
  247. int delete_slot = -1;
  248. // If hook already registered, just update the bits
  249. for (i=0; i<oh.count; i++) {
  250. if (hook == oh.entry[i].func) {
  251. if (!bits) {
  252. // Unregister if move to zero bits
  253. delete_slot = i;
  254. break;
  255. }
  256. if (bits & (oh.all_bits & ~oh.entry[i].bits)) {
  257. // Attempt to hook an already hooked bit
  258. return 0;
  259. }
  260. // Update the hooked bits (in the right order)
  261. uint32_t old_bits = oh.entry[i].bits;
  262. *(volatile uint32_t *) &oh.entry[i].bits = bits;
  263. *(volatile uint32_t *) &oh.all_bits = (oh.all_bits & ~old_bits) | bits;
  264. return 1;
  265. }
  266. }
  267. // This must be the register new hook / delete old hook
  268. if (delete_slot < 0) {
  269. if (bits & oh.all_bits) {
  270. return 0; // Attempt to hook already hooked bits
  271. }
  272. nh.count = oh.count + 1; // register a new hook
  273. } else {
  274. nh.count = oh.count - 1; // unregister an old hook
  275. }
  276. // These return NULL if the count = 0 so only error check if > 0)
  277. nh.entry = c_malloc( nh.count * sizeof(*(nh.entry)) );
  278. if (nh.count && !(nh.entry)) {
  279. return 0; // Allocation failure
  280. }
  281. for (i=0, j=0; i<oh.count; i++) {
  282. // Don't copy if this is the entry to delete
  283. if (i != delete_slot) {
  284. nh.entry[j++] = oh.entry[i];
  285. }
  286. }
  287. if (delete_slot < 0) { // for a register add the hook to the tail and set the all bits
  288. nh.entry[j].bits = bits;
  289. nh.entry[j].func = hook;
  290. nh.all_bits = oh.all_bits | bits;
  291. } else { // for an unregister clear the matching all bits
  292. nh.all_bits = oh.all_bits & (~oh.entry[delete_slot].bits);
  293. }
  294. ETS_GPIO_INTR_DISABLE();
  295. // This is a structure copy, so interrupts need to be disabled
  296. platform_gpio_hook = nh;
  297. ETS_GPIO_INTR_ENABLE();
  298. c_free(oh.entry);
  299. return 1;
  300. }
  301. #endif // GPIO_INTERRUPT_HOOK_ENABLE
  302. /*
  303. * Initialise GPIO interrupt mode. Optionally in RAM because interrupts are disabled
  304. */
  305. void NO_INTR_CODE platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
  306. {
  307. if (platform_gpio_exists(pin)) {
  308. ETS_GPIO_INTR_DISABLE();
  309. //clear interrupt status
  310. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  311. pin_int_type[pin] = type;
  312. //enable interrupt
  313. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
  314. ETS_GPIO_INTR_ENABLE();
  315. }
  316. }
  317. #endif
  318. // ****************************************************************************
  319. // UART
  320. // TODO: Support timeouts.
  321. // UartDev is defined and initialized in rom code.
  322. extern UartDevice UartDev;
  323. uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits )
  324. {
  325. switch( baud )
  326. {
  327. case BIT_RATE_300:
  328. case BIT_RATE_600:
  329. case BIT_RATE_1200:
  330. case BIT_RATE_2400:
  331. case BIT_RATE_4800:
  332. case BIT_RATE_9600:
  333. case BIT_RATE_19200:
  334. case BIT_RATE_31250:
  335. case BIT_RATE_38400:
  336. case BIT_RATE_57600:
  337. case BIT_RATE_74880:
  338. case BIT_RATE_115200:
  339. case BIT_RATE_230400:
  340. case BIT_RATE_256000:
  341. case BIT_RATE_460800:
  342. case BIT_RATE_921600:
  343. case BIT_RATE_1843200:
  344. case BIT_RATE_3686400:
  345. UartDev.baut_rate = baud;
  346. break;
  347. default:
  348. UartDev.baut_rate = BIT_RATE_9600;
  349. break;
  350. }
  351. switch( databits )
  352. {
  353. case 5:
  354. UartDev.data_bits = FIVE_BITS;
  355. break;
  356. case 6:
  357. UartDev.data_bits = SIX_BITS;
  358. break;
  359. case 7:
  360. UartDev.data_bits = SEVEN_BITS;
  361. break;
  362. case 8:
  363. UartDev.data_bits = EIGHT_BITS;
  364. break;
  365. default:
  366. UartDev.data_bits = EIGHT_BITS;
  367. break;
  368. }
  369. switch (stopbits)
  370. {
  371. case PLATFORM_UART_STOPBITS_1_5:
  372. UartDev.stop_bits = ONE_HALF_STOP_BIT;
  373. break;
  374. case PLATFORM_UART_STOPBITS_2:
  375. UartDev.stop_bits = TWO_STOP_BIT;
  376. break;
  377. default:
  378. UartDev.stop_bits = ONE_STOP_BIT;
  379. break;
  380. }
  381. switch (parity)
  382. {
  383. case PLATFORM_UART_PARITY_EVEN:
  384. UartDev.parity = EVEN_BITS;
  385. UartDev.exist_parity = STICK_PARITY_EN;
  386. break;
  387. case PLATFORM_UART_PARITY_ODD:
  388. UartDev.parity = ODD_BITS;
  389. UartDev.exist_parity = STICK_PARITY_EN;
  390. break;
  391. default:
  392. UartDev.parity = NONE_BITS;
  393. UartDev.exist_parity = STICK_PARITY_DIS;
  394. break;
  395. }
  396. uart_setup(id);
  397. return baud;
  398. }
  399. void platform_uart_get_config(unsigned id, uint32_t *baudp, uint32_t *databitsp, uint32_t *parityp, uint32_t *stopbitsp) {
  400. UartConfig config = uart_get_config(id);
  401. int i;
  402. int offset = config.baut_rate;
  403. for (i = 0; i < sizeof(uart_bitrates) / sizeof(uart_bitrates[0]); i++) {
  404. int diff = config.baut_rate - uart_bitrates[i];
  405. if (diff < 0) {
  406. diff = -diff;
  407. }
  408. if (diff < offset) {
  409. offset = diff;
  410. *baudp = uart_bitrates[i];
  411. }
  412. }
  413. switch( config.data_bits )
  414. {
  415. case FIVE_BITS:
  416. *databitsp = 5;
  417. break;
  418. case SIX_BITS:
  419. *databitsp = 6;
  420. break;
  421. case SEVEN_BITS:
  422. *databitsp = 7;
  423. break;
  424. case EIGHT_BITS:
  425. default:
  426. *databitsp = 8;
  427. break;
  428. }
  429. switch (config.stop_bits)
  430. {
  431. case ONE_HALF_STOP_BIT:
  432. *stopbitsp = PLATFORM_UART_STOPBITS_1_5;
  433. break;
  434. case TWO_STOP_BIT:
  435. *stopbitsp = PLATFORM_UART_STOPBITS_2;
  436. break;
  437. default:
  438. *stopbitsp = PLATFORM_UART_STOPBITS_1;
  439. break;
  440. }
  441. if (config.exist_parity == STICK_PARITY_DIS) {
  442. *parityp = PLATFORM_UART_PARITY_NONE;
  443. } else if (config.parity == EVEN_BITS) {
  444. *parityp = PLATFORM_UART_PARITY_EVEN;
  445. } else {
  446. *parityp = PLATFORM_UART_PARITY_ODD;
  447. }
  448. }
  449. // if set=1, then alternate serial output pins are used. (15=rx, 13=tx)
  450. void platform_uart_alt( int set )
  451. {
  452. uart0_alt( set );
  453. return;
  454. }
  455. // Send: version with and without mux
  456. void platform_uart_send( unsigned id, u8 data )
  457. {
  458. uart_tx_one_char(id, data);
  459. }
  460. // ****************************************************************************
  461. // PWMs
  462. static uint16_t pwms_duty[NUM_PWM] = {0};
  463. void platform_pwm_init()
  464. {
  465. int i;
  466. for(i=0;i<NUM_PWM;i++){
  467. pwms_duty[i] = DUTY(0);
  468. }
  469. pwm_init(500, NULL);
  470. // NODE_DBG("Function pwms_init() is called.\n");
  471. }
  472. // Return the PWM clock
  473. // NOTE: Can't find a function to query for the period set for the timer,
  474. // therefore using the struct.
  475. // This may require adjustment if driver libraries are updated.
  476. uint32_t platform_pwm_get_clock( unsigned pin )
  477. {
  478. // NODE_DBG("Function platform_pwm_get_clock() is called.\n");
  479. if( pin >= NUM_PWM)
  480. return 0;
  481. if(!pwm_exist(pin))
  482. return 0;
  483. return (uint32_t)pwm_get_freq(pin);
  484. }
  485. // Set the PWM clock
  486. uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
  487. {
  488. // NODE_DBG("Function platform_pwm_set_clock() is called.\n");
  489. if( pin >= NUM_PWM)
  490. return 0;
  491. if(!pwm_exist(pin))
  492. return 0;
  493. pwm_set_freq((uint16_t)clock, pin);
  494. pwm_start();
  495. return (uint32_t)pwm_get_freq( pin );
  496. }
  497. uint32_t platform_pwm_get_duty( unsigned pin )
  498. {
  499. // NODE_DBG("Function platform_pwm_get_duty() is called.\n");
  500. if( pin < NUM_PWM){
  501. if(!pwm_exist(pin))
  502. return 0;
  503. // return NORMAL_DUTY(pwm_get_duty(pin));
  504. return pwms_duty[pin];
  505. }
  506. return 0;
  507. }
  508. // Set the PWM duty
  509. uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
  510. {
  511. // NODE_DBG("Function platform_pwm_set_duty() is called.\n");
  512. if ( pin < NUM_PWM)
  513. {
  514. if(!pwm_exist(pin))
  515. return 0;
  516. pwm_set_duty(DUTY(duty), pin);
  517. } else {
  518. return 0;
  519. }
  520. pwm_start();
  521. pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
  522. return pwms_duty[pin];
  523. }
  524. uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
  525. {
  526. uint32_t clock;
  527. if ( pin < NUM_PWM)
  528. {
  529. platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
  530. if(!pwm_add(pin))
  531. return 0;
  532. // pwm_set_duty(DUTY(duty), pin);
  533. pwm_set_duty(0, pin);
  534. pwms_duty[pin] = duty;
  535. pwm_set_freq((uint16_t)frequency, pin);
  536. } else {
  537. return 0;
  538. }
  539. clock = platform_pwm_get_clock( pin );
  540. if (!pwm_start()) {
  541. return 0;
  542. }
  543. return clock;
  544. }
  545. void platform_pwm_close( unsigned pin )
  546. {
  547. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  548. if ( pin < NUM_PWM)
  549. {
  550. pwm_delete(pin);
  551. pwm_start();
  552. }
  553. }
  554. bool platform_pwm_start( unsigned pin )
  555. {
  556. // NODE_DBG("Function platform_pwm_start() is called.\n");
  557. if ( pin < NUM_PWM)
  558. {
  559. if(!pwm_exist(pin))
  560. return FALSE;
  561. pwm_set_duty(DUTY(pwms_duty[pin]), pin);
  562. return pwm_start();
  563. }
  564. return FALSE;
  565. }
  566. void platform_pwm_stop( unsigned pin )
  567. {
  568. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  569. if ( pin < NUM_PWM)
  570. {
  571. if(!pwm_exist(pin))
  572. return;
  573. pwm_set_duty(0, pin);
  574. pwm_start();
  575. }
  576. }
  577. // *****************************************************************************
  578. // Sigma-Delta platform interface
  579. uint8_t platform_sigma_delta_setup( uint8_t pin )
  580. {
  581. if (pin < 1 || pin > NUM_GPIO)
  582. return 0;
  583. sigma_delta_setup();
  584. // set GPIO output mode for this pin
  585. platform_gpio_mode( pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT );
  586. platform_gpio_write( pin, PLATFORM_GPIO_LOW );
  587. // enable sigma-delta on this pin
  588. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  589. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  590. GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
  591. return 1;
  592. }
  593. uint8_t platform_sigma_delta_close( uint8_t pin )
  594. {
  595. if (pin < 1 || pin > NUM_GPIO)
  596. return 0;
  597. sigma_delta_stop();
  598. // set GPIO input mode for this pin
  599. platform_gpio_mode( pin, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP );
  600. // CONNECT GPIO TO PIN PAD
  601. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  602. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  603. GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
  604. return 1;
  605. }
  606. void platform_sigma_delta_set_pwmduty( uint8_t duty )
  607. {
  608. uint8_t target = 0, prescale = 0;
  609. target = duty > 128 ? 256 - duty : duty;
  610. prescale = target == 0 ? 0 : target-1;
  611. //freq = 80000 (khz) /256 /duty_target * (prescale+1)
  612. sigma_delta_set_prescale_target( prescale, duty );
  613. }
  614. void platform_sigma_delta_set_prescale( uint8_t prescale )
  615. {
  616. sigma_delta_set_prescale_target( prescale, -1 );
  617. }
  618. void ICACHE_RAM_ATTR platform_sigma_delta_set_target( uint8_t target )
  619. {
  620. sigma_delta_set_prescale_target( -1, target );
  621. }
  622. // *****************************************************************************
  623. // I2C platform interface
  624. uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed ){
  625. if (sda >= NUM_GPIO || scl >= NUM_GPIO)
  626. return 0;
  627. // platform_pwm_close(sda);
  628. // platform_pwm_close(scl);
  629. // disable gpio interrupt first
  630. platform_gpio_mode(sda, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // inside this func call platform_pwm_close
  631. platform_gpio_mode(scl, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // disable gpio interrupt first
  632. i2c_master_gpio_init(sda, scl);
  633. return PLATFORM_I2C_SPEED_SLOW;
  634. }
  635. void platform_i2c_send_start( unsigned id ){
  636. i2c_master_start();
  637. }
  638. void platform_i2c_send_stop( unsigned id ){
  639. i2c_master_stop();
  640. }
  641. int platform_i2c_send_address( unsigned id, uint16_t address, int direction ){
  642. // Convert enum codes to R/w bit value.
  643. // If TX == 0 and RX == 1, this test will be removed by the compiler
  644. if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
  645. PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
  646. direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
  647. }
  648. i2c_master_writeByte( (uint8_t) ((address << 1) | direction ));
  649. // Low-level returns nack (0=acked); we return ack (1=acked).
  650. return ! i2c_master_getAck();
  651. }
  652. int platform_i2c_send_byte( unsigned id, uint8_t data ){
  653. i2c_master_writeByte(data);
  654. // Low-level returns nack (0=acked); we return ack (1=acked).
  655. return ! i2c_master_getAck();
  656. }
  657. int platform_i2c_recv_byte( unsigned id, int ack ){
  658. uint8_t r = i2c_master_readByte();
  659. i2c_master_setAck( !ack );
  660. return r;
  661. }
  662. // *****************************************************************************
  663. // SPI platform interface
  664. uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div )
  665. {
  666. spi_master_init( id, cpol, cpha, clock_div );
  667. // all platform functions assume LSB order for MOSI & MISO buffer
  668. spi_mast_byte_order( id, SPI_ORDER_LSB );
  669. return 1;
  670. }
  671. int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
  672. {
  673. if (bitlen > 32)
  674. return PLATFORM_ERR;
  675. spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
  676. return PLATFORM_OK;
  677. }
  678. spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data )
  679. {
  680. if (bitlen > 32)
  681. return 0;
  682. spi_mast_set_mosi( id, 0, bitlen, data );
  683. spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
  684. return spi_mast_get_miso( id, 0, bitlen );
  685. }
  686. int platform_spi_blkwrite( uint8_t id, size_t len, const uint8_t *data )
  687. {
  688. while (len > 0) {
  689. size_t chunk_len = len > 64 ? 64 : len;
  690. spi_mast_blkset( id, chunk_len * 8, data );
  691. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, 0 );
  692. data = &(data[chunk_len]);
  693. len -= chunk_len;
  694. }
  695. return PLATFORM_OK;
  696. }
  697. int platform_spi_blkread( uint8_t id, size_t len, uint8_t *data )
  698. {
  699. uint8_t mosi_idle[64];
  700. os_memset( (void *)mosi_idle, 0xff, len > 64 ? 64 : len );
  701. while (len > 0 ) {
  702. size_t chunk_len = len > 64 ? 64 : len;
  703. spi_mast_blkset( id, chunk_len * 8, mosi_idle );
  704. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, -1 );
  705. spi_mast_blkget( id, chunk_len * 8, data );
  706. data = &(data[chunk_len]);
  707. len -= chunk_len;
  708. }
  709. return PLATFORM_OK;
  710. }
  711. int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
  712. uint8_t addr_bitlen, spi_data_type addr_data,
  713. uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen )
  714. {
  715. if ((cmd_bitlen > 16) ||
  716. (addr_bitlen > 32) ||
  717. (mosi_bitlen > 512) ||
  718. (dummy_bitlen > 256) ||
  719. (miso_bitlen > 512))
  720. return PLATFORM_ERR;
  721. spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
  722. return PLATFORM_OK;
  723. }
  724. // ****************************************************************************
  725. // Flash access functions
  726. /*
  727. * Assumptions:
  728. * > toaddr is INTERNAL_FLASH_WRITE_UNIT_SIZE aligned
  729. * > size is a multiple of INTERNAL_FLASH_WRITE_UNIT_SIZE
  730. */
  731. uint32_t platform_s_flash_write( const void *from, uint32_t toaddr, uint32_t size )
  732. {
  733. SpiFlashOpResult r;
  734. const uint32_t blkmask = INTERNAL_FLASH_WRITE_UNIT_SIZE - 1;
  735. uint32_t *apbuf = NULL;
  736. uint32_t fromaddr = (uint32_t)from;
  737. if( (fromaddr & blkmask ) || (fromaddr >= INTERNAL_FLASH_MAPPED_ADDRESS)) {
  738. apbuf = (uint32_t *)c_malloc(size);
  739. if(!apbuf)
  740. return 0;
  741. c_memcpy(apbuf, from, size);
  742. }
  743. system_soft_wdt_feed ();
  744. r = flash_write(toaddr, apbuf?(uint32 *)apbuf:(uint32 *)from, size);
  745. if(apbuf)
  746. c_free(apbuf);
  747. if(SPI_FLASH_RESULT_OK == r)
  748. return size;
  749. else{
  750. NODE_ERR( "ERROR in flash_write: r=%d at %08X\n", ( int )r, ( unsigned )toaddr);
  751. return 0;
  752. }
  753. }
  754. /*
  755. * Assumptions:
  756. * > fromaddr is INTERNAL_FLASH_READ_UNIT_SIZE aligned
  757. * > size is a multiple of INTERNAL_FLASH_READ_UNIT_SIZE
  758. */
  759. uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
  760. {
  761. if (size==0)
  762. return 0;
  763. SpiFlashOpResult r;
  764. system_soft_wdt_feed ();
  765. const uint32_t blkmask = (INTERNAL_FLASH_READ_UNIT_SIZE - 1);
  766. if( ((uint32_t)to) & blkmask )
  767. {
  768. uint32_t size2=size-INTERNAL_FLASH_READ_UNIT_SIZE;
  769. uint32* to2=(uint32*)((((uint32_t)to)&(~blkmask))+INTERNAL_FLASH_READ_UNIT_SIZE);
  770. r = flash_read(fromaddr, to2, size2);
  771. if(SPI_FLASH_RESULT_OK == r)
  772. {
  773. os_memmove(to,to2,size2);
  774. char back[ INTERNAL_FLASH_READ_UNIT_SIZE ] __attribute__ ((aligned(INTERNAL_FLASH_READ_UNIT_SIZE)));
  775. r=flash_read(fromaddr+size2,(uint32*)back,INTERNAL_FLASH_READ_UNIT_SIZE);
  776. os_memcpy((uint8_t*)to+size2,back,INTERNAL_FLASH_READ_UNIT_SIZE);
  777. }
  778. }
  779. else
  780. r = flash_read(fromaddr, (uint32 *)to, size);
  781. if(SPI_FLASH_RESULT_OK == r)
  782. return size;
  783. else{
  784. NODE_ERR( "ERROR in flash_read: r=%d at %08X\n", ( int )r, ( unsigned )fromaddr);
  785. return 0;
  786. }
  787. }
  788. int platform_flash_erase_sector( uint32_t sector_id )
  789. {
  790. system_soft_wdt_feed ();
  791. return flash_erase( sector_id ) == SPI_FLASH_RESULT_OK ? PLATFORM_OK : PLATFORM_ERR;
  792. }
  793. uint32_t platform_flash_mapped2phys (uint32_t mapped_addr)
  794. {
  795. uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
  796. if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
  797. return -1;
  798. bool b0 = (cache_ctrl & CACHE_FLASH_MAPPED0) ? 1 : 0;
  799. bool b1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 1 : 0;
  800. uint32_t meg = (b1 << 1) | b0;
  801. return mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg * 0x100000;
  802. }
  803. void* platform_print_deprecation_note( const char *msg, const char *time_frame)
  804. {
  805. c_printf( "Warning, deprecated API! %s. It will be removed %s. See documentation for details.\n", msg, time_frame );
  806. }