platform.c 22 KB

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  1. // Platform-dependent functions and includes
  2. #include "platform.h"
  3. #include "common.h"
  4. #include <stdio.h>
  5. #include <string.h>
  6. #include <stdlib.h>
  7. #include "llimits.h"
  8. #include "gpio.h"
  9. #include "user_interface.h"
  10. #include "driver/gpio16.h"
  11. #include "driver/i2c_master.h"
  12. #include "driver/spi.h"
  13. #include "driver/uart.h"
  14. #include "driver/sigma_delta.h"
  15. #ifdef GPIO_INTERRUPT_ENABLE
  16. static task_handle_t gpio_task_handle;
  17. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  18. struct gpio_hook_entry {
  19. platform_hook_function func;
  20. uint32_t bits;
  21. };
  22. struct gpio_hook {
  23. struct gpio_hook_entry *entry;
  24. uint32_t all_bits;
  25. uint32_t count;
  26. };
  27. static struct gpio_hook platform_gpio_hook;
  28. #endif
  29. #endif
  30. int platform_init()
  31. {
  32. // Setup the various forward and reverse mappings for the pins
  33. get_pin_map();
  34. cmn_platform_init();
  35. // All done
  36. return PLATFORM_OK;
  37. }
  38. #ifdef __ESP2866__
  39. // ****************************************************************************
  40. // KEY_LED functions
  41. uint8_t platform_key_led( uint8_t level){
  42. uint8_t temp;
  43. gpio16_output_set(1); // set to high first, for reading key low level
  44. gpio16_input_conf();
  45. temp = gpio16_input_get();
  46. gpio16_output_conf();
  47. gpio16_output_set(level);
  48. return temp;
  49. }
  50. #endif
  51. // ****************************************************************************
  52. // GPIO functions
  53. /*
  54. * Set GPIO mode to output. Optionally in RAM helper because interrupts are dsabled
  55. */
  56. static void NO_INTR_CODE set_gpio_no_interrupt(uint8 pin, uint8_t push_pull) {
  57. unsigned pnum = pin_num[pin];
  58. ETS_GPIO_INTR_DISABLE();
  59. #ifdef GPIO_INTERRUPT_ENABLE
  60. pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
  61. #endif
  62. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  63. //disable interrupt
  64. gpio_pin_intr_state_set(GPIO_ID_PIN(pnum), GPIO_PIN_INTR_DISABLE);
  65. //clear interrupt status
  66. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pnum));
  67. // configure push-pull vs open-drain
  68. if (push_pull) {
  69. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  70. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) &
  71. (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
  72. } else {
  73. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  74. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) |
  75. GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //enable open drain;
  76. }
  77. ETS_GPIO_INTR_ENABLE();
  78. }
  79. /*
  80. * Set GPIO mode to interrupt. Optionally RAM helper because interrupts are dsabled
  81. */
  82. #ifdef GPIO_INTERRUPT_ENABLE
  83. static void NO_INTR_CODE set_gpio_interrupt(uint8 pin) {
  84. ETS_GPIO_INTR_DISABLE();
  85. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  86. GPIO_DIS_OUTPUT(pin_num[pin]);
  87. gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  88. GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
  89. | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
  90. | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
  91. ETS_GPIO_INTR_ENABLE();
  92. }
  93. #endif
  94. int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
  95. {
  96. NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n", pin_mux[pin], pin_func[pin]);
  97. if (pin >= NUM_GPIO)
  98. return -1;
  99. #ifdef __ESP8266__
  100. if(pin == 0){
  101. if(mode==PLATFORM_GPIO_INPUT)
  102. gpio16_input_conf();
  103. else
  104. gpio16_output_conf();
  105. return 1;
  106. }
  107. #endif
  108. #ifdef LUA_USE_MODULES_PWM
  109. platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
  110. #endif
  111. if (pull == PLATFORM_GPIO_PULLUP) {
  112. PIN_PULLUP_EN(pin_mux[pin]);
  113. } else {
  114. PIN_PULLUP_DIS(pin_mux[pin]);
  115. }
  116. switch(mode){
  117. case PLATFORM_GPIO_INPUT:
  118. GPIO_DIS_OUTPUT(pin_num[pin]);
  119. /* run on */
  120. case PLATFORM_GPIO_OUTPUT:
  121. set_gpio_no_interrupt(pin, TRUE);
  122. break;
  123. case PLATFORM_GPIO_OPENDRAIN:
  124. set_gpio_no_interrupt(pin, FALSE);
  125. break;
  126. #ifdef GPIO_INTERRUPT_ENABLE
  127. case PLATFORM_GPIO_INT:
  128. set_gpio_interrupt(pin);
  129. break;
  130. #endif
  131. default:
  132. break;
  133. }
  134. return 1;
  135. }
  136. int platform_gpio_write( unsigned pin, unsigned level )
  137. {
  138. // NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
  139. if (pin >= NUM_GPIO)
  140. return -1;
  141. #ifdef __ESP8266__
  142. if(pin == 0){
  143. gpio16_output_conf();
  144. gpio16_output_set(level);
  145. return 1;
  146. }
  147. #endif
  148. GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
  149. }
  150. int platform_gpio_read( unsigned pin )
  151. {
  152. // NODE_DBG("Function platform_gpio_read() is called. pin:%d\n",GPIO_ID_PIN(pin_num[pin]));
  153. if (pin >= NUM_GPIO)
  154. return -1;
  155. #ifdef __ESP8266__
  156. if(pin == 0){
  157. // gpio16_input_conf();
  158. return 0x1 & gpio16_input_get();
  159. }
  160. #endif
  161. // GPIO_DIS_OUTPUT(pin_num[pin]);
  162. return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
  163. }
  164. #ifdef GPIO_INTERRUPT_ENABLE
  165. static void ICACHE_RAM_ATTR platform_gpio_intr_dispatcher (void *dummy){
  166. uint32 j=0;
  167. uint32 gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  168. UNUSED(dummy);
  169. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  170. if (gpio_status & platform_gpio_hook.all_bits) {
  171. for (j = 0; j < platform_gpio_hook.count; j++) {
  172. if (gpio_status & platform_gpio_hook.entry[j].bits)
  173. gpio_status = (platform_gpio_hook.entry[j].func)(gpio_status);
  174. }
  175. }
  176. #endif
  177. /*
  178. * gpio_status is a bit map where bit 0 is set if unmapped gpio pin 0 (pin3) has
  179. * triggered the ISR. bit 1 if unmapped gpio pin 1 (pin10=U0TXD), etc. Since this
  180. * is the ISR, it makes sense to optimize this by doing a fast scan of the status
  181. * and reverse mapping any set bits.
  182. */
  183. for (j = 0; gpio_status>0; j++, gpio_status >>= 1) {
  184. if (gpio_status&1) {
  185. int i = pin_num_inv[j];
  186. if (pin_int_type[i]) {
  187. //disable interrupt
  188. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  189. //clear interrupt status
  190. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  191. uint32 level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(j));
  192. task_post_high (gpio_task_handle, (i<<1) + level);
  193. // We re-enable the interrupt when we execute the callback
  194. }
  195. }
  196. }
  197. }
  198. void platform_gpio_init( task_handle_t gpio_task )
  199. {
  200. gpio_task_handle = gpio_task;
  201. ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, NULL);
  202. }
  203. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  204. /*
  205. * Register an ISR hook to be called from the GPIO ISR for a given GPIO bitmask.
  206. * This routine is only called a few times so has been optimised for size and
  207. * the unregister is a special case when the bits are 0.
  208. *
  209. * Each hook function can only be registered once. If it is re-registered
  210. * then the hooked bits are just updated to the new value.
  211. */
  212. int platform_gpio_register_intr_hook(uint32_t bits, platform_hook_function hook)
  213. {
  214. struct gpio_hook nh, oh = platform_gpio_hook;
  215. int i, j;
  216. if (!hook) {
  217. // Cannot register or unregister null hook
  218. return 0;
  219. }
  220. int delete_slot = -1;
  221. // If hook already registered, just update the bits
  222. for (i=0; i<oh.count; i++) {
  223. if (hook == oh.entry[i].func) {
  224. if (!bits) {
  225. // Unregister if move to zero bits
  226. delete_slot = i;
  227. break;
  228. }
  229. if (bits & (oh.all_bits & ~oh.entry[i].bits)) {
  230. // Attempt to hook an already hooked bit
  231. return 0;
  232. }
  233. // Update the hooked bits (in the right order)
  234. uint32_t old_bits = oh.entry[i].bits;
  235. *(volatile uint32_t *) &oh.entry[i].bits = bits;
  236. *(volatile uint32_t *) &oh.all_bits = (oh.all_bits & ~old_bits) | bits;
  237. return 1;
  238. }
  239. }
  240. // This must be the register new hook / delete old hook
  241. if (delete_slot < 0) {
  242. if (bits & oh.all_bits) {
  243. return 0; // Attempt to hook already hooked bits
  244. }
  245. nh.count = oh.count + 1; // register a new hook
  246. } else {
  247. nh.count = oh.count - 1; // unregister an old hook
  248. }
  249. // These return NULL if the count = 0 so only error check if > 0)
  250. nh.entry = malloc( nh.count * sizeof(*(nh.entry)) );
  251. if (nh.count && !(nh.entry)) {
  252. return 0; // Allocation failure
  253. }
  254. for (i=0, j=0; i<oh.count; i++) {
  255. // Don't copy if this is the entry to delete
  256. if (i != delete_slot) {
  257. nh.entry[j++] = oh.entry[i];
  258. }
  259. }
  260. if (delete_slot < 0) { // for a register add the hook to the tail and set the all bits
  261. nh.entry[j].bits = bits;
  262. nh.entry[j].func = hook;
  263. nh.all_bits = oh.all_bits | bits;
  264. } else { // for an unregister clear the matching all bits
  265. nh.all_bits = oh.all_bits & (~oh.entry[delete_slot].bits);
  266. }
  267. ETS_GPIO_INTR_DISABLE();
  268. // This is a structure copy, so interrupts need to be disabled
  269. platform_gpio_hook = nh;
  270. ETS_GPIO_INTR_ENABLE();
  271. free(oh.entry);
  272. return 1;
  273. }
  274. #endif // GPIO_INTERRUPT_HOOK_ENABLE
  275. /*
  276. * Initialise GPIO interrupt mode. Optionally in RAM because interrupts are dsabled
  277. */
  278. void NO_INTR_CODE platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
  279. {
  280. if (platform_gpio_exists(pin)) {
  281. ETS_GPIO_INTR_DISABLE();
  282. //clear interrupt status
  283. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  284. pin_int_type[pin] = type;
  285. //enable interrupt
  286. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
  287. ETS_GPIO_INTR_ENABLE();
  288. }
  289. }
  290. #endif
  291. // ****************************************************************************
  292. // UART
  293. // TODO: Support timeouts.
  294. uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits )
  295. {
  296. UART_ConfigTypeDef cfg;
  297. switch( baud )
  298. {
  299. case BIT_RATE_300:
  300. case BIT_RATE_600:
  301. case BIT_RATE_1200:
  302. case BIT_RATE_2400:
  303. case BIT_RATE_4800:
  304. case BIT_RATE_9600:
  305. case BIT_RATE_19200:
  306. case BIT_RATE_38400:
  307. case BIT_RATE_57600:
  308. case BIT_RATE_74880:
  309. case BIT_RATE_115200:
  310. case BIT_RATE_230400:
  311. case BIT_RATE_460800:
  312. case BIT_RATE_921600:
  313. case BIT_RATE_1843200:
  314. case BIT_RATE_3686400:
  315. cfg.baud_rate = baud;
  316. break;
  317. default:
  318. cfg.baud_rate = BIT_RATE_9600;
  319. break;
  320. }
  321. switch( databits )
  322. {
  323. case 5:
  324. cfg.data_bits = UART_WordLength_5b;
  325. break;
  326. case 6:
  327. cfg.data_bits = UART_WordLength_6b;
  328. break;
  329. case 7:
  330. cfg.data_bits = UART_WordLength_7b;
  331. break;
  332. case 8:
  333. default:
  334. cfg.data_bits = UART_WordLength_8b;
  335. break;
  336. }
  337. switch (stopbits)
  338. {
  339. case PLATFORM_UART_STOPBITS_1_5:
  340. cfg.stop_bits = USART_StopBits_1_5;
  341. break;
  342. case PLATFORM_UART_STOPBITS_2:
  343. cfg.stop_bits = USART_StopBits_2;
  344. break;
  345. default:
  346. cfg.stop_bits = USART_StopBits_1;
  347. break;
  348. }
  349. switch (parity)
  350. {
  351. case PLATFORM_UART_PARITY_EVEN:
  352. cfg.parity = USART_Parity_Even;
  353. break;
  354. case PLATFORM_UART_PARITY_ODD:
  355. cfg.parity = USART_Parity_Odd;
  356. break;
  357. default:
  358. cfg.parity = USART_Parity_None;
  359. break;
  360. }
  361. UART_ParamConfig (id, &cfg);
  362. return baud;
  363. }
  364. // if set=1, then alternate serial output pins are used. (15=rx, 13=tx)
  365. void platform_uart_alt( int set )
  366. {
  367. uart0_alt( set );
  368. return;
  369. }
  370. // Send: version with and without mux
  371. void platform_uart_send( unsigned id, u8 data )
  372. {
  373. uart_tx_one_char(id, data);
  374. }
  375. // ****************************************************************************
  376. // PWMs
  377. static uint16_t pwms_duty[NUM_PWM] = {0};
  378. void platform_pwm_init()
  379. {
  380. int i;
  381. for(i=0;i<NUM_PWM;i++){
  382. pwms_duty[i] = DUTY(0);
  383. }
  384. pwm_init(500, NULL);
  385. // NODE_DBG("Function pwms_init() is called.\n");
  386. }
  387. // Return the PWM clock
  388. // NOTE: Can't find a function to query for the period set for the timer,
  389. // therefore using the struct.
  390. // This may require adjustment if driver libraries are updated.
  391. uint32_t platform_pwm_get_clock( unsigned pin )
  392. {
  393. // NODE_DBG("Function platform_pwm_get_clock() is called.\n");
  394. if( pin >= NUM_PWM)
  395. return 0;
  396. #ifdef __ESP8266__ // FIXME
  397. if(!pwm_exist(pin))
  398. return 0;
  399. return (uint32_t)pwm_get_freq(pin);
  400. #else
  401. return 0;
  402. #endif
  403. }
  404. // Set the PWM clock
  405. uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
  406. {
  407. #ifdef __ESP8266__ // FIXME
  408. // NODE_DBG("Function platform_pwm_set_clock() is called.\n");
  409. if( pin >= NUM_PWM)
  410. return 0;
  411. if(!pwm_exist(pin))
  412. return 0;
  413. pwm_set_freq((uint16_t)clock, pin);
  414. pwm_start();
  415. return (uint32_t)pwm_get_freq( pin );
  416. #else
  417. return 0;
  418. #endif
  419. }
  420. uint32_t platform_pwm_get_duty( unsigned pin )
  421. {
  422. #ifdef __ESP8266__ // FIXME
  423. // NODE_DBG("Function platform_pwm_get_duty() is called.\n");
  424. if( pin < NUM_PWM){
  425. if(!pwm_exist(pin))
  426. return 0;
  427. // return NORMAL_DUTY(pwm_get_duty(pin));
  428. return pwms_duty[pin];
  429. }
  430. #endif
  431. return 0;
  432. }
  433. // Set the PWM duty
  434. uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
  435. {
  436. #ifdef __ESP8266__ // FIXME
  437. // NODE_DBG("Function platform_pwm_set_duty() is called.\n");
  438. if ( pin < NUM_PWM)
  439. {
  440. if(!pwm_exist(pin))
  441. return 0;
  442. pwm_set_duty(DUTY(duty), pin);
  443. } else {
  444. return 0;
  445. }
  446. pwm_start();
  447. pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
  448. #endif
  449. return pwms_duty[pin];
  450. }
  451. uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
  452. {
  453. uint32_t clock;
  454. #ifdef __ESP8266__ // FIXME
  455. if ( pin < NUM_PWM)
  456. {
  457. platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
  458. if(!pwm_add(pin))
  459. return 0;
  460. // pwm_set_duty(DUTY(duty), pin);
  461. pwm_set_duty(0, pin);
  462. pwms_duty[pin] = duty;
  463. pwm_set_freq((uint16_t)frequency, pin);
  464. } else {
  465. return 0;
  466. }
  467. clock = platform_pwm_get_clock( pin );
  468. if (!pwm_start()) {
  469. return 0;
  470. }
  471. #endif
  472. return clock;
  473. }
  474. void platform_pwm_close( unsigned pin )
  475. {
  476. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  477. if ( pin < NUM_PWM)
  478. {
  479. #ifdef __ESP8266__ // FIXME
  480. pwm_delete(pin);
  481. #endif
  482. pwm_start();
  483. }
  484. }
  485. bool platform_pwm_start( unsigned pin )
  486. {
  487. #ifdef __ESP8266__ // FIXME
  488. // NODE_DBG("Function platform_pwm_start() is called.\n");
  489. if ( pin < NUM_PWM)
  490. {
  491. if(!pwm_exist(pin))
  492. return FALSE;
  493. pwm_set_duty(DUTY(pwms_duty[pin]), pin);
  494. return pwm_start();
  495. }
  496. #endif
  497. return FALSE;
  498. }
  499. void platform_pwm_stop( unsigned pin )
  500. {
  501. #ifdef __ESP8266__ // FIXME
  502. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  503. if ( pin < NUM_PWM)
  504. {
  505. if(!pwm_exist(pin))
  506. return;
  507. pwm_set_duty(0, pin);
  508. pwm_start();
  509. }
  510. #endif
  511. }
  512. // *****************************************************************************
  513. // Sigma-Delta platform interface
  514. uint8_t platform_sigma_delta_setup( uint8_t pin )
  515. {
  516. #ifdef __ESP8266__ // FIXME
  517. if (pin < 1 || pin > NUM_GPIO)
  518. return 0;
  519. sigma_delta_setup();
  520. // set GPIO output mode for this pin
  521. platform_gpio_mode( pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT );
  522. platform_gpio_write( pin, PLATFORM_GPIO_LOW );
  523. // enable sigma-delta on this pin
  524. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  525. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  526. GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
  527. #endif
  528. return 1;
  529. }
  530. uint8_t platform_sigma_delta_close( uint8_t pin )
  531. {
  532. #ifdef __ESP8266__ // FIXME
  533. if (pin < 1 || pin > NUM_GPIO)
  534. return 0;
  535. sigma_delta_stop();
  536. // set GPIO input mode for this pin
  537. platform_gpio_mode( pin, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP );
  538. // CONNECT GPIO TO PIN PAD
  539. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  540. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  541. GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
  542. #endif
  543. return 1;
  544. }
  545. void platform_sigma_delta_set_pwmduty( uint8_t duty )
  546. {
  547. #ifdef __ESP8266__ // FIXME
  548. uint8_t target = 0, prescale = 0;
  549. target = duty > 128 ? 256 - duty : duty;
  550. prescale = target == 0 ? 0 : target-1;
  551. //freq = 80000 (khz) /256 /duty_target * (prescale+1)
  552. sigma_delta_set_prescale_target( prescale, duty );
  553. #endif
  554. }
  555. void platform_sigma_delta_set_prescale( uint8_t prescale )
  556. {
  557. #ifdef __ESP8266__ // FIXME
  558. sigma_delta_set_prescale_target( prescale, -1 );
  559. #endif
  560. }
  561. void platform_sigma_delta_set_target( uint8_t target )
  562. {
  563. #ifdef __ESP8266__ // FIXME
  564. sigma_delta_set_prescale_target( -1, target );
  565. #endif
  566. }
  567. // *****************************************************************************
  568. // I2C platform interface
  569. uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed ){
  570. if (sda >= NUM_GPIO || scl >= NUM_GPIO)
  571. return 0;
  572. // platform_pwm_close(sda);
  573. // platform_pwm_close(scl);
  574. // disable gpio interrupt first
  575. platform_gpio_mode(sda, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // inside this func call platform_pwm_close
  576. platform_gpio_mode(scl, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // disable gpio interrupt first
  577. i2c_master_gpio_init(sda, scl);
  578. return PLATFORM_I2C_SPEED_SLOW;
  579. }
  580. void platform_i2c_send_start( unsigned id ){
  581. i2c_master_start();
  582. }
  583. void platform_i2c_send_stop( unsigned id ){
  584. i2c_master_stop();
  585. }
  586. int platform_i2c_send_address( unsigned id, uint16_t address, int direction ){
  587. // Convert enum codes to R/w bit value.
  588. // If TX == 0 and RX == 1, this test will be removed by the compiler
  589. if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
  590. PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
  591. direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
  592. }
  593. i2c_master_writeByte( (uint8_t) ((address << 1) | direction ));
  594. // Low-level returns nack (0=acked); we return ack (1=acked).
  595. return ! i2c_master_getAck();
  596. }
  597. int platform_i2c_send_byte( unsigned id, uint8_t data ){
  598. i2c_master_writeByte(data);
  599. // Low-level returns nack (0=acked); we return ack (1=acked).
  600. return ! i2c_master_getAck();
  601. }
  602. int platform_i2c_recv_byte( unsigned id, int ack ){
  603. uint8_t r = i2c_master_readByte();
  604. i2c_master_setAck( !ack );
  605. return r;
  606. }
  607. // *****************************************************************************
  608. // SPI platform interface
  609. uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div)
  610. {
  611. #ifdef __ESP8266__ // FIXME
  612. spi_master_init( id, cpol, cpha, clock_div );
  613. #endif
  614. return 1;
  615. }
  616. int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
  617. {
  618. if (bitlen > 32)
  619. return PLATFORM_ERR;
  620. #ifdef __ESP8266__ // FIXME
  621. spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
  622. #endif
  623. return PLATFORM_OK;
  624. }
  625. spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data )
  626. {
  627. if (bitlen > 32)
  628. return 0;
  629. #ifdef __ESP8266__ // FIXME
  630. spi_mast_set_mosi( id, 0, bitlen, data );
  631. spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
  632. return spi_mast_get_miso( id, 0, bitlen );
  633. #else
  634. return 0;
  635. #endif
  636. }
  637. int platform_spi_set_mosi( uint8_t id, uint16_t offset, uint8_t bitlen, spi_data_type data )
  638. {
  639. if (offset + bitlen > 512)
  640. return PLATFORM_ERR;
  641. #ifdef __ESP8266__ // FIXME
  642. spi_mast_set_mosi( id, offset, bitlen, data );
  643. #endif
  644. return PLATFORM_OK;
  645. }
  646. spi_data_type platform_spi_get_miso( uint8_t id, uint16_t offset, uint8_t bitlen )
  647. {
  648. if (offset + bitlen > 512)
  649. return 0;
  650. #ifdef __ESP8266__ // FIXME
  651. return spi_mast_get_miso( id, offset, bitlen );
  652. #else
  653. return 0;
  654. #endif
  655. }
  656. int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
  657. uint8_t addr_bitlen, spi_data_type addr_data,
  658. uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen )
  659. {
  660. if ((cmd_bitlen > 16) ||
  661. (addr_bitlen > 32) ||
  662. (mosi_bitlen > 512) ||
  663. (dummy_bitlen > 256) ||
  664. (miso_bitlen > 512))
  665. return PLATFORM_ERR;
  666. #ifdef __ESP8266__ // FIXME
  667. spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
  668. #endif
  669. return PLATFORM_OK;
  670. }
  671. // ****************************************************************************
  672. // Flash access functions
  673. /*
  674. * Assumptions:
  675. * > toaddr is INTERNAL_FLASH_WRITE_UNIT_SIZE aligned
  676. * > size is a multiple of INTERNAL_FLASH_WRITE_UNIT_SIZE
  677. */
  678. uint32_t platform_s_flash_write( const void *from, uint32_t toaddr, uint32_t size )
  679. {
  680. SpiFlashOpResult r;
  681. const uint32_t blkmask = INTERNAL_FLASH_WRITE_UNIT_SIZE - 1;
  682. uint32_t *apbuf = NULL;
  683. uint32_t fromaddr = (uint32_t)from;
  684. if( (fromaddr & blkmask ) || (fromaddr >= INTERNAL_FLASH_MAPPED_ADDRESS)) {
  685. apbuf = (uint32_t *)malloc(size);
  686. if(!apbuf)
  687. return 0;
  688. memcpy(apbuf, from, size);
  689. }
  690. system_soft_wdt_feed ();
  691. r = flash_write(toaddr, apbuf?(uint32 *)apbuf:(uint32 *)from, size);
  692. if(apbuf)
  693. free(apbuf);
  694. if(SPI_FLASH_RESULT_OK == r)
  695. return size;
  696. else{
  697. NODE_ERR( "ERROR in flash_write: r=%d at %08X\n", ( int )r, ( unsigned )toaddr);
  698. return 0;
  699. }
  700. }
  701. /*
  702. * Assumptions:
  703. * > fromaddr is INTERNAL_FLASH_READ_UNIT_SIZE aligned
  704. * > size is a multiple of INTERNAL_FLASH_READ_UNIT_SIZE
  705. */
  706. uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
  707. {
  708. if (size==0)
  709. return 0;
  710. SpiFlashOpResult r;
  711. system_soft_wdt_feed ();
  712. const uint32_t blkmask = (INTERNAL_FLASH_READ_UNIT_SIZE - 1);
  713. if( ((uint32_t)to) & blkmask )
  714. {
  715. uint32_t size2=size-INTERNAL_FLASH_READ_UNIT_SIZE;
  716. uint32* to2=(uint32*)((((uint32_t)to)&(~blkmask))+INTERNAL_FLASH_READ_UNIT_SIZE);
  717. r = flash_read(fromaddr, to2, size2);
  718. if(SPI_FLASH_RESULT_OK == r)
  719. {
  720. memmove(to,to2,size2);
  721. char back[ INTERNAL_FLASH_READ_UNIT_SIZE ] __attribute__ ((aligned(INTERNAL_FLASH_READ_UNIT_SIZE)));
  722. r=flash_read(fromaddr+size2,(uint32*)back,INTERNAL_FLASH_READ_UNIT_SIZE);
  723. os_memcpy((uint8_t*)to+size2,back,INTERNAL_FLASH_READ_UNIT_SIZE);
  724. }
  725. }
  726. else
  727. r = flash_read(fromaddr, (uint32 *)to, size);
  728. if(SPI_FLASH_RESULT_OK == r)
  729. return size;
  730. else{
  731. NODE_ERR( "ERROR in flash_read: r=%d at %08X\n", ( int )r, ( unsigned )fromaddr);
  732. return 0;
  733. }
  734. }
  735. int platform_flash_erase_sector( uint32_t sector_id )
  736. {
  737. system_soft_wdt_feed ();
  738. return flash_erase( sector_id ) == SPI_FLASH_RESULT_OK ? PLATFORM_OK : PLATFORM_ERR;
  739. }
  740. uint32_t platform_flash_mapped2phys (uint32_t mapped_addr)
  741. {
  742. #if defined(__ESP8266__)
  743. uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
  744. if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
  745. return -1;
  746. bool b0 = (cache_ctrl & CACHE_FLASH_MAPPED0) ? 1 : 0;
  747. bool b1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 1 : 0;
  748. uint32_t meg = (b1 << 1) | b0;
  749. return mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg * 0x100000;
  750. #elif defined(__ESP32__)
  751. // TODO: need to handle drom0 addresses too?
  752. return mapped_addr - IROM0_START_MAPPED_ADDR + IROM0_START_FLASH_ADDR;
  753. #else
  754. # error "unknown board"
  755. #endif
  756. }