Since | Origin / Contributor | Maintainer | Source |
---|---|---|---|
2017-05-04 | Arnim Läuger | Arnim Läuger | spi.c |
The ESP32 contains 4 SPI bus hosts called SPI
, SPI1
, HSPI
, and VSPI
. SPI
is locked to flash communication and is not available for the application. SPI1
is currently also tied to flash support, but might be available in the future. Applications can currently only use the HSPI
and VSPI
hosts.
The host signals can be mapped to any suitable GPIO pins.
!!! note
The API on ESP32 differs from the API on ESP8266. For backwards compatibility please refer to [`lua_compat/spi_compat.lua`](../../../lua_compat/spi_compat.lua`).
Initializes a bus in master mode and returns a bus master object.
spi.master(host, config)
host
id, one of
spi.SPI1
. not supported yetspi.HSPI
spi.VSPI
config
table listing the assigned GPIOs. All signal assignment are optional.
sclk
mosi
miso
quadwp
quadhd
SPI bus master object
busmaster_config = {sclk = 19, mosi = 23, miso = 25}
busmaster = spi.master(spi.HSPI, busmaster_config)
Close the bus host. This fails if there are still devices registered on this bus.
!!! caution
The bus is also closed when the bus master object is automatically destroyed during garbage collection. Registered devices inherently prevent garbage collection of the bus master object.
busmaster:close()
none
nil
Adds a device on the given master bus. Up to three devices per bus are supported.
busmaster:device(config)
config
table describing the device parameters:
cs
GPIO connected to device’s chip-select pin, optionalmode
SPI mode used for this device (0-3), mandatoryfreq
clock frequency used for this device [Hz], mandatorycommand_bits
amount of bits in command phase (0-16), defaults to 0 if omittedaddress_bits
amount of bits in address phase (0-64), defaults to 0 if omitteddummy_bits
amount of dummy bits to insert address and data phase, defaults to 0 if omittedcs_ena_pretrans
, optionalcs_ena_posttrans
, optionalduty_cycle_pos
, optionaltx_lsb_first
transmit command/address/data LSB first if true
, MSB first otherwiserx_lsb_first
receive data LSB first if true
, MSB first otherwisewire3
use spiq for both transmit and receive if true
, use mosi and miso otherwisepositive_cs
chip-select is active high during a transaction if true
, cs is active low otherwisehalfduplex
transmit data before receiving data if true
, transmit and receive simultaneously otherwiseclk_as_cs
output clock on cs line when cs is active if true
SPI device object
device_config = {mode = 0, freq = 1000000}
device_config.cs = 22
dev1 = busmaster:device(device_config)
device_config.cs = 4
dev2 = busmaster:device(device_config)
Removes a device from the related bus master.
!!! caution
The device is also removed when the device object is automatically destroyed during garbage collection.
device:remove()
none
nil
Initiate an SPI transaction consisting of
The function returns after the transaction is completed.
device:transfer(trans)
device:transfer(txdata)
trans
table containing the elements of the transaction:
command
data for command phase, amount of bits was defined during device creation, optionaladdress
data for address phase, amount of bits was defined during device creation, optionaltxdata
string of data to be sent to the device, optionalrxlen
number of bytes to be received, optionalmode
optional, one of
sio
transmit in SIO mode, default if omitteddio
transmit in DIO modeqio
transmit in QIO modeaddr_mode
transmit address also in selected mode
if true
, transmit address in SIO otherwise.txdata
string of data to be sent to the device
String of rxlen
length, or #txdata
length if rxlen
is omitted.
Initializes a bus in slave mode and returns a slave object. Not yet supported.