platform.c 33 KB

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  1. // Platform-dependent functions and includes
  2. #include "platform.h"
  3. #include "common.h"
  4. #include <stdio.h>
  5. #include <string.h>
  6. #include <stdlib.h>
  7. #include "llimits.h"
  8. #include "gpio.h"
  9. #include "user_interface.h"
  10. #include "driver/gpio16.h"
  11. #include "driver/i2c_master.h"
  12. #include "driver/spi.h"
  13. #include "driver/uart.h"
  14. #include "driver/sigma_delta.h"
  15. #define INTERRUPT_TYPE_IS_LEVEL(x) ((x) >= GPIO_PIN_INTR_LOLEVEL)
  16. #ifdef GPIO_INTERRUPT_ENABLE
  17. static platform_task_handle_t gpio_task_handle;
  18. static int task_init_handler(void);
  19. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  20. struct gpio_hook_entry {
  21. platform_hook_function func;
  22. uint32_t bits;
  23. };
  24. struct gpio_hook {
  25. struct gpio_hook_entry *entry;
  26. uint32_t all_bits;
  27. uint32_t count;
  28. };
  29. static struct gpio_hook platform_gpio_hook;
  30. #endif
  31. #endif
  32. static const int uart_bitrates[] = {
  33. BIT_RATE_300,
  34. BIT_RATE_600,
  35. BIT_RATE_1200,
  36. BIT_RATE_2400,
  37. BIT_RATE_4800,
  38. BIT_RATE_9600,
  39. BIT_RATE_19200,
  40. BIT_RATE_31250,
  41. BIT_RATE_38400,
  42. BIT_RATE_57600,
  43. BIT_RATE_74880,
  44. BIT_RATE_115200,
  45. BIT_RATE_230400,
  46. BIT_RATE_256000,
  47. BIT_RATE_460800,
  48. BIT_RATE_921600,
  49. BIT_RATE_1843200,
  50. BIT_RATE_3686400
  51. };
  52. int platform_init ()
  53. {
  54. // Setup the various forward and reverse mappings for the pins
  55. get_pin_map();
  56. (void) task_init_handler();
  57. cmn_platform_init();
  58. // All done
  59. return PLATFORM_OK;
  60. }
  61. // ****************************************************************************
  62. // KEY_LED functions
  63. uint8_t platform_key_led( uint8_t level){
  64. uint8_t temp;
  65. gpio16_output_set(1); // set to high first, for reading key low level
  66. gpio16_input_conf();
  67. temp = gpio16_input_get();
  68. gpio16_output_conf();
  69. gpio16_output_set(level);
  70. return temp;
  71. }
  72. // ****************************************************************************
  73. // GPIO functions
  74. /*
  75. * Set GPIO mode to output. Optionally in RAM helper because interrupts are dsabled
  76. */
  77. static void NO_INTR_CODE set_gpio_no_interrupt(uint8_t pin, uint8_t push_pull) {
  78. unsigned pnum = pin_num[pin];
  79. ETS_GPIO_INTR_DISABLE();
  80. #ifdef GPIO_INTERRUPT_ENABLE
  81. pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
  82. #endif
  83. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  84. //disable interrupt
  85. gpio_pin_intr_state_set(GPIO_ID_PIN(pnum), GPIO_PIN_INTR_DISABLE);
  86. //clear interrupt status
  87. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pnum));
  88. // configure push-pull vs open-drain
  89. if (push_pull) {
  90. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  91. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) &
  92. (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
  93. } else {
  94. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  95. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) |
  96. GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //enable open drain;
  97. }
  98. ETS_GPIO_INTR_ENABLE();
  99. }
  100. /*
  101. * Set GPIO mode to interrupt. Optionally RAM helper because interrupts are dsabled
  102. */
  103. #ifdef GPIO_INTERRUPT_ENABLE
  104. static void NO_INTR_CODE set_gpio_interrupt(uint8_t pin) {
  105. ETS_GPIO_INTR_DISABLE();
  106. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  107. GPIO_DIS_OUTPUT(pin_num[pin]);
  108. gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  109. GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
  110. | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
  111. | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
  112. ETS_GPIO_INTR_ENABLE();
  113. }
  114. #endif
  115. int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
  116. {
  117. NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n", pin_mux[pin], pin_func[pin]);
  118. if (pin >= NUM_GPIO)
  119. return -1;
  120. if(pin == 0){
  121. if(mode==PLATFORM_GPIO_INPUT)
  122. gpio16_input_conf();
  123. else
  124. gpio16_output_conf();
  125. return 1;
  126. }
  127. #ifdef LUA_USE_MODULES_PWM
  128. platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
  129. #endif
  130. if (pull == PLATFORM_GPIO_PULLUP) {
  131. PIN_PULLUP_EN(pin_mux[pin]);
  132. } else {
  133. PIN_PULLUP_DIS(pin_mux[pin]);
  134. }
  135. switch(mode){
  136. case PLATFORM_GPIO_INPUT:
  137. GPIO_DIS_OUTPUT(pin_num[pin]);
  138. set_gpio_no_interrupt(pin, TRUE);
  139. break;
  140. case PLATFORM_GPIO_OUTPUT:
  141. set_gpio_no_interrupt(pin, TRUE);
  142. GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, BIT(pin_num[pin]));
  143. break;
  144. case PLATFORM_GPIO_OPENDRAIN:
  145. set_gpio_no_interrupt(pin, FALSE);
  146. GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, BIT(pin_num[pin]));
  147. break;
  148. #ifdef GPIO_INTERRUPT_ENABLE
  149. case PLATFORM_GPIO_INT:
  150. set_gpio_interrupt(pin);
  151. break;
  152. #endif
  153. default:
  154. break;
  155. }
  156. return 1;
  157. }
  158. int platform_gpio_write( unsigned pin, unsigned level )
  159. {
  160. // NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
  161. if (pin >= NUM_GPIO)
  162. return -1;
  163. if(pin == 0){
  164. gpio16_output_conf();
  165. gpio16_output_set(level);
  166. return 1;
  167. }
  168. GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
  169. }
  170. int platform_gpio_read( unsigned pin )
  171. {
  172. // NODE_DBG("Function platform_gpio_read() is called. pin:%d\n",GPIO_ID_PIN(pin_num[pin]));
  173. if (pin >= NUM_GPIO)
  174. return -1;
  175. if(pin == 0){
  176. // gpio16_input_conf();
  177. return 0x1 & gpio16_input_get();
  178. }
  179. // GPIO_DIS_OUTPUT(pin_num[pin]);
  180. return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
  181. }
  182. #ifdef GPIO_INTERRUPT_ENABLE
  183. static void ICACHE_RAM_ATTR platform_gpio_intr_dispatcher (void *dummy){
  184. uint32_t j=0;
  185. uint32_t gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  186. uint32_t now = system_get_time();
  187. UNUSED(dummy);
  188. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  189. if (gpio_status & platform_gpio_hook.all_bits) {
  190. for (j = 0; j < platform_gpio_hook.count; j++) {
  191. if (gpio_status & platform_gpio_hook.entry[j].bits)
  192. gpio_status = (platform_gpio_hook.entry[j].func)(gpio_status);
  193. }
  194. }
  195. #endif
  196. /*
  197. * gpio_status is a bit map where bit 0 is set if unmapped gpio pin 0 (pin3) has
  198. * triggered the ISR. bit 1 if unmapped gpio pin 1 (pin10=U0TXD), etc. Since this
  199. * is the ISR, it makes sense to optimize this by doing a fast scan of the status
  200. * and reverse mapping any set bits.
  201. */
  202. for (j = 0; gpio_status>0; j++, gpio_status >>= 1) {
  203. if (gpio_status&1) {
  204. int i = pin_num_inv[j];
  205. if (pin_int_type[i]) {
  206. uint16_t diff = pin_counter[i].seen ^ pin_counter[i].reported;
  207. pin_counter[i].seen = 0x7fff & (pin_counter[i].seen + 1);
  208. if (INTERRUPT_TYPE_IS_LEVEL(pin_int_type[i])) {
  209. //disable interrupt
  210. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  211. }
  212. //clear interrupt status
  213. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  214. if (diff == 0 || diff & 0x8000) {
  215. uint32_t level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(j));
  216. if (!platform_post_high (gpio_task_handle, (now << 8) + (i<<1) + level)) {
  217. // If we fail to post, then try on the next interrupt
  218. pin_counter[i].seen |= 0x8000;
  219. }
  220. // We re-enable the interrupt when we execute the callback (if level)
  221. }
  222. } else {
  223. // this is an unexpected interrupt so shut it off for now
  224. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  225. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  226. }
  227. }
  228. }
  229. }
  230. void platform_gpio_init( platform_task_handle_t gpio_task )
  231. {
  232. gpio_task_handle = gpio_task;
  233. ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, NULL);
  234. }
  235. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  236. /*
  237. * Register an ISR hook to be called from the GPIO ISR for a given GPIO bitmask.
  238. * This routine is only called a few times so has been optimised for size and
  239. * the unregister is a special case when the bits are 0.
  240. *
  241. * Each hook function can only be registered once. If it is re-registered
  242. * then the hooked bits are just updated to the new value.
  243. */
  244. int platform_gpio_register_intr_hook(uint32_t bits, platform_hook_function hook)
  245. {
  246. struct gpio_hook nh, oh = platform_gpio_hook;
  247. int i, j;
  248. if (!hook) {
  249. // Cannot register or unregister null hook
  250. return 0;
  251. }
  252. int delete_slot = -1;
  253. // If hook already registered, just update the bits
  254. for (i=0; i<oh.count; i++) {
  255. if (hook == oh.entry[i].func) {
  256. if (!bits) {
  257. // Unregister if move to zero bits
  258. delete_slot = i;
  259. break;
  260. }
  261. if (bits & (oh.all_bits & ~oh.entry[i].bits)) {
  262. // Attempt to hook an already hooked bit
  263. return 0;
  264. }
  265. // Update the hooked bits (in the right order)
  266. uint32_t old_bits = oh.entry[i].bits;
  267. *(volatile uint32_t *) &oh.entry[i].bits = bits;
  268. *(volatile uint32_t *) &oh.all_bits = (oh.all_bits & ~old_bits) | bits;
  269. return 1;
  270. }
  271. }
  272. // This must be the register new hook / delete old hook
  273. if (delete_slot < 0) {
  274. if (bits & oh.all_bits) {
  275. return 0; // Attempt to hook already hooked bits
  276. }
  277. nh.count = oh.count + 1; // register a new hook
  278. } else {
  279. nh.count = oh.count - 1; // unregister an old hook
  280. }
  281. // These return NULL if the count = 0 so only error check if > 0)
  282. nh.entry = malloc( nh.count * sizeof(*(nh.entry)) );
  283. if (nh.count && !(nh.entry)) {
  284. return 0; // Allocation failure
  285. }
  286. for (i=0, j=0; i<oh.count; i++) {
  287. // Don't copy if this is the entry to delete
  288. if (i != delete_slot) {
  289. nh.entry[j++] = oh.entry[i];
  290. }
  291. }
  292. if (delete_slot < 0) { // for a register add the hook to the tail and set the all bits
  293. nh.entry[j].bits = bits;
  294. nh.entry[j].func = hook;
  295. nh.all_bits = oh.all_bits | bits;
  296. } else { // for an unregister clear the matching all bits
  297. nh.all_bits = oh.all_bits & (~oh.entry[delete_slot].bits);
  298. }
  299. ETS_GPIO_INTR_DISABLE();
  300. // This is a structure copy, so interrupts need to be disabled
  301. platform_gpio_hook = nh;
  302. ETS_GPIO_INTR_ENABLE();
  303. free(oh.entry);
  304. return 1;
  305. }
  306. #endif // GPIO_INTERRUPT_HOOK_ENABLE
  307. /*
  308. * Initialise GPIO interrupt mode. Optionally in RAM because interrupts are disabled
  309. */
  310. void NO_INTR_CODE platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
  311. {
  312. if (platform_gpio_exists(pin)) {
  313. ETS_GPIO_INTR_DISABLE();
  314. //clear interrupt status
  315. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  316. pin_int_type[pin] = type;
  317. //enable interrupt
  318. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
  319. ETS_GPIO_INTR_ENABLE();
  320. }
  321. }
  322. #endif
  323. // ****************************************************************************
  324. // UART
  325. // TODO: Support timeouts.
  326. // UartDev is defined and initialized in rom code.
  327. extern UartDevice UartDev;
  328. uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits )
  329. {
  330. switch( baud )
  331. {
  332. case BIT_RATE_300:
  333. case BIT_RATE_600:
  334. case BIT_RATE_1200:
  335. case BIT_RATE_2400:
  336. case BIT_RATE_4800:
  337. case BIT_RATE_9600:
  338. case BIT_RATE_19200:
  339. case BIT_RATE_31250:
  340. case BIT_RATE_38400:
  341. case BIT_RATE_57600:
  342. case BIT_RATE_74880:
  343. case BIT_RATE_115200:
  344. case BIT_RATE_230400:
  345. case BIT_RATE_256000:
  346. case BIT_RATE_460800:
  347. case BIT_RATE_921600:
  348. case BIT_RATE_1843200:
  349. case BIT_RATE_3686400:
  350. UartDev.baut_rate = baud;
  351. break;
  352. default:
  353. UartDev.baut_rate = BIT_RATE_9600;
  354. break;
  355. }
  356. switch( databits )
  357. {
  358. case 5:
  359. UartDev.data_bits = FIVE_BITS;
  360. break;
  361. case 6:
  362. UartDev.data_bits = SIX_BITS;
  363. break;
  364. case 7:
  365. UartDev.data_bits = SEVEN_BITS;
  366. break;
  367. case 8:
  368. UartDev.data_bits = EIGHT_BITS;
  369. break;
  370. default:
  371. UartDev.data_bits = EIGHT_BITS;
  372. break;
  373. }
  374. switch (stopbits)
  375. {
  376. case PLATFORM_UART_STOPBITS_1_5:
  377. UartDev.stop_bits = ONE_HALF_STOP_BIT;
  378. break;
  379. case PLATFORM_UART_STOPBITS_2:
  380. UartDev.stop_bits = TWO_STOP_BIT;
  381. break;
  382. default:
  383. UartDev.stop_bits = ONE_STOP_BIT;
  384. break;
  385. }
  386. switch (parity)
  387. {
  388. case PLATFORM_UART_PARITY_EVEN:
  389. UartDev.parity = EVEN_BITS;
  390. UartDev.exist_parity = STICK_PARITY_EN;
  391. break;
  392. case PLATFORM_UART_PARITY_ODD:
  393. UartDev.parity = ODD_BITS;
  394. UartDev.exist_parity = STICK_PARITY_EN;
  395. break;
  396. default:
  397. UartDev.parity = NONE_BITS;
  398. UartDev.exist_parity = STICK_PARITY_DIS;
  399. break;
  400. }
  401. uart_setup(id);
  402. return baud;
  403. }
  404. void platform_uart_get_config(unsigned id, uint32_t *baudp, uint32_t *databitsp, uint32_t *parityp, uint32_t *stopbitsp) {
  405. UartConfig config = uart_get_config(id);
  406. int i;
  407. int offset = config.baut_rate;
  408. for (i = 0; i < sizeof(uart_bitrates) / sizeof(uart_bitrates[0]); i++) {
  409. int diff = config.baut_rate - uart_bitrates[i];
  410. if (diff < 0) {
  411. diff = -diff;
  412. }
  413. if (diff < offset) {
  414. offset = diff;
  415. *baudp = uart_bitrates[i];
  416. }
  417. }
  418. switch( config.data_bits )
  419. {
  420. case FIVE_BITS:
  421. *databitsp = 5;
  422. break;
  423. case SIX_BITS:
  424. *databitsp = 6;
  425. break;
  426. case SEVEN_BITS:
  427. *databitsp = 7;
  428. break;
  429. case EIGHT_BITS:
  430. default:
  431. *databitsp = 8;
  432. break;
  433. }
  434. switch (config.stop_bits)
  435. {
  436. case ONE_HALF_STOP_BIT:
  437. *stopbitsp = PLATFORM_UART_STOPBITS_1_5;
  438. break;
  439. case TWO_STOP_BIT:
  440. *stopbitsp = PLATFORM_UART_STOPBITS_2;
  441. break;
  442. default:
  443. *stopbitsp = PLATFORM_UART_STOPBITS_1;
  444. break;
  445. }
  446. if (config.exist_parity == STICK_PARITY_DIS) {
  447. *parityp = PLATFORM_UART_PARITY_NONE;
  448. } else if (config.parity == EVEN_BITS) {
  449. *parityp = PLATFORM_UART_PARITY_EVEN;
  450. } else {
  451. *parityp = PLATFORM_UART_PARITY_ODD;
  452. }
  453. }
  454. // if set=1, then alternate serial output pins are used. (15=rx, 13=tx)
  455. void platform_uart_alt( int set )
  456. {
  457. uart0_alt( set );
  458. return;
  459. }
  460. // Send: version with and without mux
  461. void platform_uart_send( unsigned id, u8 data )
  462. {
  463. uart_tx_one_char(id, data);
  464. }
  465. // ****************************************************************************
  466. // PWMs
  467. static uint16_t pwms_duty[NUM_PWM] = {0};
  468. void platform_pwm_init()
  469. {
  470. int i;
  471. for(i=0;i<NUM_PWM;i++){
  472. pwms_duty[i] = DUTY(0);
  473. }
  474. pwm_init(500, NULL);
  475. // NODE_DBG("Function pwms_init() is called.\n");
  476. }
  477. // Return the PWM clock
  478. // NOTE: Can't find a function to query for the period set for the timer,
  479. // therefore using the struct.
  480. // This may require adjustment if driver libraries are updated.
  481. uint32_t platform_pwm_get_clock( unsigned pin )
  482. {
  483. // NODE_DBG("Function platform_pwm_get_clock() is called.\n");
  484. if( pin >= NUM_PWM)
  485. return 0;
  486. if(!pwm_exist(pin))
  487. return 0;
  488. return (uint32_t)pwm_get_freq(pin);
  489. }
  490. // Set the PWM clock
  491. uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
  492. {
  493. // NODE_DBG("Function platform_pwm_set_clock() is called.\n");
  494. if( pin >= NUM_PWM)
  495. return 0;
  496. if(!pwm_exist(pin))
  497. return 0;
  498. pwm_set_freq((uint16_t)clock, pin);
  499. pwm_start();
  500. return (uint32_t)pwm_get_freq( pin );
  501. }
  502. uint32_t platform_pwm_get_duty( unsigned pin )
  503. {
  504. // NODE_DBG("Function platform_pwm_get_duty() is called.\n");
  505. if( pin < NUM_PWM){
  506. if(!pwm_exist(pin))
  507. return 0;
  508. // return NORMAL_DUTY(pwm_get_duty(pin));
  509. return pwms_duty[pin];
  510. }
  511. return 0;
  512. }
  513. // Set the PWM duty
  514. uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
  515. {
  516. // NODE_DBG("Function platform_pwm_set_duty() is called.\n");
  517. if ( pin < NUM_PWM)
  518. {
  519. if(!pwm_exist(pin))
  520. return 0;
  521. pwm_set_duty(DUTY(duty), pin);
  522. } else {
  523. return 0;
  524. }
  525. pwm_start();
  526. pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
  527. return pwms_duty[pin];
  528. }
  529. uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
  530. {
  531. uint32_t clock;
  532. if ( pin < NUM_PWM)
  533. {
  534. platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
  535. if(!pwm_add(pin))
  536. return 0;
  537. // pwm_set_duty(DUTY(duty), pin);
  538. pwm_set_duty(0, pin);
  539. pwms_duty[pin] = duty;
  540. pwm_set_freq((uint16_t)frequency, pin);
  541. } else {
  542. return 0;
  543. }
  544. clock = platform_pwm_get_clock( pin );
  545. if (!pwm_start()) {
  546. return 0;
  547. }
  548. return clock;
  549. }
  550. void platform_pwm_close( unsigned pin )
  551. {
  552. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  553. if ( pin < NUM_PWM)
  554. {
  555. pwm_delete(pin);
  556. pwm_start();
  557. }
  558. }
  559. bool platform_pwm_start( unsigned pin )
  560. {
  561. // NODE_DBG("Function platform_pwm_start() is called.\n");
  562. if ( pin < NUM_PWM)
  563. {
  564. if(!pwm_exist(pin))
  565. return FALSE;
  566. pwm_set_duty(DUTY(pwms_duty[pin]), pin);
  567. return pwm_start();
  568. }
  569. return FALSE;
  570. }
  571. void platform_pwm_stop( unsigned pin )
  572. {
  573. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  574. if ( pin < NUM_PWM)
  575. {
  576. if(!pwm_exist(pin))
  577. return;
  578. pwm_set_duty(0, pin);
  579. pwm_start();
  580. }
  581. }
  582. // *****************************************************************************
  583. // Sigma-Delta platform interface
  584. uint8_t platform_sigma_delta_setup( uint8_t pin )
  585. {
  586. if (pin < 1 || pin > NUM_GPIO)
  587. return 0;
  588. sigma_delta_setup();
  589. // set GPIO output mode for this pin
  590. platform_gpio_mode( pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT );
  591. platform_gpio_write( pin, PLATFORM_GPIO_LOW );
  592. // enable sigma-delta on this pin
  593. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  594. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  595. GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
  596. return 1;
  597. }
  598. uint8_t platform_sigma_delta_close( uint8_t pin )
  599. {
  600. if (pin < 1 || pin > NUM_GPIO)
  601. return 0;
  602. sigma_delta_stop();
  603. // set GPIO input mode for this pin
  604. platform_gpio_mode( pin, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP );
  605. // CONNECT GPIO TO PIN PAD
  606. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  607. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  608. GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
  609. return 1;
  610. }
  611. void platform_sigma_delta_set_pwmduty( uint8_t duty )
  612. {
  613. uint8_t target = 0, prescale = 0;
  614. target = duty > 128 ? 256 - duty : duty;
  615. prescale = target == 0 ? 0 : target-1;
  616. //freq = 80000 (khz) /256 /duty_target * (prescale+1)
  617. sigma_delta_set_prescale_target( prescale, duty );
  618. }
  619. void platform_sigma_delta_set_prescale( uint8_t prescale )
  620. {
  621. sigma_delta_set_prescale_target( prescale, -1 );
  622. }
  623. void ICACHE_RAM_ATTR platform_sigma_delta_set_target( uint8_t target )
  624. {
  625. sigma_delta_set_prescale_target( -1, target );
  626. }
  627. // *****************************************************************************
  628. // I2C platform interface
  629. uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed ){
  630. if (sda >= NUM_GPIO || scl >= NUM_GPIO)
  631. return 0;
  632. // platform_pwm_close(sda);
  633. // platform_pwm_close(scl);
  634. // disable gpio interrupt first
  635. platform_gpio_mode(sda, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // inside this func call platform_pwm_close
  636. platform_gpio_mode(scl, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // disable gpio interrupt first
  637. return i2c_master_setup(id, sda, scl, speed);
  638. }
  639. bool platform_i2c_configured( unsigned id ){
  640. return i2c_master_configured(id);
  641. }
  642. void platform_i2c_send_start( unsigned id ){
  643. i2c_master_start(id);
  644. }
  645. void platform_i2c_send_stop( unsigned id ){
  646. i2c_master_stop(id);
  647. }
  648. int platform_i2c_send_address( unsigned id, uint16_t address, int direction ){
  649. // Convert enum codes to R/w bit value.
  650. // If TX == 0 and RX == 1, this test will be removed by the compiler
  651. if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
  652. PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
  653. direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
  654. }
  655. return i2c_master_writeByte(id,
  656. (uint8_t) ((address << 1) + (direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ? 0 : 1))
  657. );
  658. }
  659. int platform_i2c_send_byte(unsigned id, uint8_t data ){
  660. return i2c_master_writeByte(id, data);
  661. }
  662. int platform_i2c_recv_byte( unsigned id, int ack ){
  663. return i2c_master_readByte(id, ack);
  664. }
  665. // *****************************************************************************
  666. // SPI platform interface
  667. uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div )
  668. {
  669. spi_master_init( id, cpol, cpha, clock_div );
  670. // all platform functions assume LSB order for MOSI & MISO buffer
  671. spi_mast_byte_order( id, SPI_ORDER_LSB );
  672. return 1;
  673. }
  674. int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
  675. {
  676. if (bitlen > 32)
  677. return PLATFORM_ERR;
  678. spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
  679. return PLATFORM_OK;
  680. }
  681. spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data )
  682. {
  683. if (bitlen > 32)
  684. return 0;
  685. spi_mast_set_mosi( id, 0, bitlen, data );
  686. spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
  687. return spi_mast_get_miso( id, 0, bitlen );
  688. }
  689. int platform_spi_blkwrite( uint8_t id, size_t len, const uint8_t *data )
  690. {
  691. while (len > 0) {
  692. size_t chunk_len = len > 64 ? 64 : len;
  693. spi_mast_blkset( id, chunk_len * 8, data );
  694. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, 0 );
  695. data = &(data[chunk_len]);
  696. len -= chunk_len;
  697. }
  698. return PLATFORM_OK;
  699. }
  700. int platform_spi_blkread( uint8_t id, size_t len, uint8_t *data )
  701. {
  702. uint8_t mosi_idle[64];
  703. os_memset( (void *)mosi_idle, 0xff, len > 64 ? 64 : len );
  704. while (len > 0 ) {
  705. size_t chunk_len = len > 64 ? 64 : len;
  706. spi_mast_blkset( id, chunk_len * 8, mosi_idle );
  707. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, -1 );
  708. spi_mast_blkget( id, chunk_len * 8, data );
  709. data = &(data[chunk_len]);
  710. len -= chunk_len;
  711. }
  712. return PLATFORM_OK;
  713. }
  714. int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
  715. uint8_t addr_bitlen, spi_data_type addr_data,
  716. uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen )
  717. {
  718. if ((cmd_bitlen > 16) ||
  719. (addr_bitlen > 32) ||
  720. (mosi_bitlen > 512) ||
  721. (dummy_bitlen > 256) ||
  722. (miso_bitlen > 512))
  723. return PLATFORM_ERR;
  724. spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
  725. return PLATFORM_OK;
  726. }
  727. // ****************************************************************************
  728. // Flash access functions
  729. /*
  730. * Assumptions:
  731. * > toaddr is INTERNAL_FLASH_WRITE_UNIT_SIZE aligned
  732. * > size is a multiple of INTERNAL_FLASH_WRITE_UNIT_SIZE
  733. */
  734. uint32_t platform_s_flash_write( const void *from, uint32_t toaddr, uint32_t size )
  735. {
  736. SpiFlashOpResult r;
  737. const uint32_t blkmask = INTERNAL_FLASH_WRITE_UNIT_SIZE - 1;
  738. uint32_t *apbuf = NULL;
  739. uint32_t fromaddr = (uint32_t)from;
  740. if( (fromaddr & blkmask ) || (fromaddr >= INTERNAL_FLASH_MAPPED_ADDRESS)) {
  741. apbuf = (uint32_t *)malloc(size);
  742. if(!apbuf)
  743. return 0;
  744. memcpy(apbuf, from, size);
  745. }
  746. system_soft_wdt_feed ();
  747. r = flash_write(toaddr, apbuf?(uint32_t *)apbuf:(uint32_t *)from, size);
  748. if(apbuf)
  749. free(apbuf);
  750. if(SPI_FLASH_RESULT_OK == r)
  751. return size;
  752. else{
  753. NODE_ERR( "ERROR in flash_write: r=%d at %p\n", r, toaddr);
  754. return 0;
  755. }
  756. }
  757. /*
  758. * Assumptions:
  759. * > fromaddr is INTERNAL_FLASH_READ_UNIT_SIZE aligned
  760. * > size is a multiple of INTERNAL_FLASH_READ_UNIT_SIZE
  761. */
  762. uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
  763. {
  764. if (size==0)
  765. return 0;
  766. SpiFlashOpResult r;
  767. system_soft_wdt_feed ();
  768. const uint32_t blkmask = (INTERNAL_FLASH_READ_UNIT_SIZE - 1);
  769. if( ((uint32_t)to) & blkmask )
  770. {
  771. uint32_t size2=size-INTERNAL_FLASH_READ_UNIT_SIZE;
  772. uint32_t* to2=(uint32_t*)((((uint32_t)to)&(~blkmask))+INTERNAL_FLASH_READ_UNIT_SIZE);
  773. r = flash_read(fromaddr, to2, size2);
  774. if(SPI_FLASH_RESULT_OK == r)
  775. {
  776. memmove(to,to2,size2); // This is overlapped so must be memmove and not memcpy
  777. char back[ INTERNAL_FLASH_READ_UNIT_SIZE ] __attribute__ ((aligned(INTERNAL_FLASH_READ_UNIT_SIZE)));
  778. r=flash_read(fromaddr+size2,(uint32*)back,INTERNAL_FLASH_READ_UNIT_SIZE);
  779. memcpy((uint8_t*)to+size2,back,INTERNAL_FLASH_READ_UNIT_SIZE);
  780. }
  781. }
  782. else
  783. r = flash_read(fromaddr, (uint32_t *)to, size);
  784. if(SPI_FLASH_RESULT_OK == r)
  785. return size;
  786. else{
  787. NODE_ERR( "ERROR in flash_read: r=%d at %p\n", r, fromaddr);
  788. return 0;
  789. }
  790. }
  791. int platform_flash_erase_sector( uint32_t sector_id )
  792. {
  793. NODE_DBG( "flash_erase_sector(%u)\n", sector_id);
  794. return flash_erase( sector_id ) == SPI_FLASH_RESULT_OK ? PLATFORM_OK : PLATFORM_ERR;
  795. }
  796. static uint32_t flash_map_meg_offset (void) {
  797. uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
  798. if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
  799. return -1;
  800. uint32_t m0 = (cache_ctrl & CACHE_FLASH_MAPPED0) ? 0x100000 : 0;
  801. uint32_t m1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 0x200000 : 0;
  802. return m0 + m1;
  803. }
  804. uint32_t platform_flash_mapped2phys (uint32_t mapped_addr) {
  805. uint32_t meg = flash_map_meg_offset();
  806. return (meg&1) ? -1 : mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg ;
  807. }
  808. uint32_t platform_flash_phys2mapped (uint32_t phys_addr) {
  809. uint32_t meg = flash_map_meg_offset();
  810. return (meg&1) ? -1 : phys_addr + INTERNAL_FLASH_MAPPED_ADDRESS - meg;
  811. }
  812. uint32_t platform_flash_get_partition (uint32_t part_id, uint32_t *addr) {
  813. partition_item_t pt = {0,0,0};
  814. system_partition_get_item(SYSTEM_PARTITION_CUSTOMER_BEGIN + part_id, &pt);
  815. if (addr) {
  816. *addr = pt.addr;
  817. }
  818. return pt.type == 0 ? 0 : pt.size;
  819. }
  820. /*
  821. * The Reboot Config Records are stored in the 4K flash page at offset 0x10000 (in
  822. * the linker section .irom0.ptable) and is used for configuration changes that
  823. * persist across reboots. This page contains a sequence of records, each of which
  824. * is word-aligned and comprises a header and body of length 0-64 words. The 4-byte
  825. * header comprises a length, a RCR id, and two zero fill bytes. These are written
  826. * using flash NAND writing rules, so any unused area (all 0xFF) can be overwritten
  827. * by a new record without needing to erase the RCR page. Ditto any existing
  828. * record can be marked as deleted by over-writing the header with the id set to
  829. * PLATFORM_RCR_DELETED (0x0). Note that the last word is not used additions so a
  830. * scan for PLATFORM_RCR_FREE will always terminate.
  831. *
  832. * The number of updates is extremely low, so it is unlikely (but possible) that
  833. * the page might fill with the churn of new RCRs, so in this case the write function
  834. * compacts the page by eliminating all deleted records. This does require a flash
  835. * sector erase.
  836. *
  837. * NOTE THAT THIS ALGO ISN'T 100% ROBUST, eg. a powerfail between the erase and the
  838. * wite-back will leave the page unitialised; ditto a powerfail between the record
  839. * appned and old deletion will leave two records. However this is better than the
  840. * general integrity of SPIFFS, for example and the vulnerable window is typically
  841. * less than 1 mSec every configuration change.
  842. */
  843. extern uint32_t _irom0_text_start[];
  844. #define RCR_WORD(i) (_irom0_text_start[i])
  845. #define WORDSIZE sizeof(uint32_t)
  846. #define FLASH_SECTOR_WORDS (INTERNAL_FLASH_SECTOR_SIZE/WORDSIZE)
  847. uint32_t platform_rcr_read (uint8_t rec_id, void **rec) {
  848. //DEBUG os_printf("platform_rcr_read(%d,%08x)\n",rec_id,rec);
  849. platform_rcr_t *rcr = (platform_rcr_t *) &RCR_WORD(0);
  850. uint32_t i = 0;
  851. /*
  852. * Chain down the RCR page looking for a record that matches the record
  853. * ID. If found return the size of the record and optionally its address.
  854. */
  855. while (1) {
  856. // copy RCR header into RAM to avoid unaligned exceptions
  857. platform_rcr_t r = (platform_rcr_t) RCR_WORD(i);
  858. if (r.id == rec_id) {
  859. if (rec) *rec = &RCR_WORD(i+1);
  860. return r.len * WORDSIZE;
  861. } else if (r.id == PLATFORM_RCR_FREE) {
  862. break;
  863. }
  864. i += 1 + r.len;
  865. }
  866. return ~0;
  867. }
  868. /*
  869. * Chain down the RCR page and look for an existing record that matches the record
  870. * ID and the first free record. If there is enough room, then append the new
  871. * record and mark any previous record as deleted. If the page is full then GC,
  872. * erase the page and rewrite with the GCed content.
  873. */
  874. #define MAXREC 65
  875. uint32_t platform_rcr_write (uint8_t rec_id, const void *inrec, uint8_t n) {
  876. uint32_t nwords = (n+WORDSIZE-1) / WORDSIZE;
  877. uint32_t reclen = (nwords+1)*WORDSIZE;
  878. uint32_t *prev=NULL, *new = NULL;
  879. // make local stack copy of inrec including header and any trailing fill bytes
  880. uint32_t rec[MAXREC];
  881. if (nwords >= MAXREC)
  882. return ~0;
  883. rec[0] = 0; rec[nwords] = 0;
  884. ((platform_rcr_t *) rec)->id = rec_id;
  885. ((platform_rcr_t *) rec)->len = nwords;
  886. memcpy(rec+1, inrec, n); // let memcpy handle 0 and odd byte cases
  887. // find previous copy if any and exit if the replacement is the same value
  888. uint8_t np = platform_rcr_read (rec_id, (void **) &prev);
  889. if (prev && !os_memcmp(prev-1, rec, reclen))
  890. return n;
  891. // find next free slot
  892. platform_rcr_read (PLATFORM_RCR_FREE, (void **) &new);
  893. uint32_t nfree = &RCR_WORD(FLASH_SECTOR_WORDS) - new;
  894. // Is there enough room to fit the rec in the RCR page?
  895. if (nwords < nfree) { // Note inequality needed to leave at least one all set word
  896. uint32_t addr = platform_flash_mapped2phys((uint32_t)&new[-1]);
  897. platform_s_flash_write(rec, addr, reclen);
  898. if (prev) { // If a previous exists, then overwrite the hdr as DELETED
  899. platform_rcr_t rcr = {0};
  900. addr = platform_flash_mapped2phys((uint32_t)&prev[-1]);
  901. rcr.id = PLATFORM_RCR_DELETED; rcr.len = np/WORDSIZE;
  902. platform_s_flash_write(&rcr, addr, WORDSIZE);
  903. }
  904. } else {
  905. platform_rcr_t *rcr = (platform_rcr_t *) &RCR_WORD(0), newrcr = {0};
  906. uint32_t flash_addr = platform_flash_mapped2phys((uint32_t)&RCR_WORD(0));
  907. uint32_t *buf, i, l, pass;
  908. for (pass = 1; pass <= 2; pass++) {
  909. for (i = 0, l = 0; i < FLASH_SECTOR_WORDS - nfree; ) {
  910. platform_rcr_t r = rcr[i]; // again avoid unaligned exceptions
  911. if (r.id == PLATFORM_RCR_FREE)
  912. break;
  913. if (r.id != PLATFORM_RCR_DELETED && r.id != rec_id) {
  914. if (pass == 2) memcpy(buf + l, rcr + i, (r.len + 1)*WORDSIZE);
  915. l += r.len + 1;
  916. }
  917. i += r.len + 1;
  918. }
  919. if (pass == 2) memcpy(buf + l, rec, reclen);
  920. l += nwords + 1;
  921. if (pass == 1) buf = malloc(l * WORDSIZE);
  922. if (l >= FLASH_SECTOR_WORDS || !buf)
  923. return ~0;
  924. }
  925. platform_flash_erase_sector(flash_addr/INTERNAL_FLASH_SECTOR_SIZE);
  926. platform_s_flash_write(buf, flash_addr, l*WORDSIZE);
  927. free(buf);
  928. }
  929. return nwords*WORDSIZE;
  930. }
  931. void* platform_print_deprecation_note( const char *msg, const char *time_frame)
  932. {
  933. printf( "Warning, deprecated API! %s. It will be removed %s. See documentation for details.\n", msg, time_frame );
  934. }
  935. #define TH_MONIKER 0x68680000
  936. #define TH_MASK 0xFFF80000
  937. #define TH_UNMASK (~TH_MASK)
  938. #define TH_SHIFT 2
  939. #define TH_ALLOCATION_BRICK 4 // must be a power of 2
  940. #define TASK_DEFAULT_QUEUE_LEN 8
  941. #define TASK_PRIORITY_MASK 3
  942. #define TASK_PRIORITY_COUNT 3
  943. /*
  944. * Private struct to hold the 3 event task queues and the dispatch callbacks
  945. */
  946. static struct taskQblock {
  947. os_event_t *task_Q[TASK_PRIORITY_COUNT];
  948. platform_task_callback_t *task_func;
  949. int task_count;
  950. } TQB = {0};
  951. static void platform_task_dispatch (os_event_t *e) {
  952. platform_task_handle_t handle = e->sig;
  953. if ( (handle & TH_MASK) == TH_MONIKER) {
  954. uint16_t entry = (handle & TH_UNMASK) >> TH_SHIFT;
  955. uint8_t priority = handle & TASK_PRIORITY_MASK;
  956. if ( priority <= PLATFORM_TASK_PRIORITY_HIGH &&
  957. TQB.task_func &&
  958. entry < TQB.task_count ){
  959. /* call the registered task handler with the specified parameter and priority */
  960. TQB.task_func[entry](e->par, priority);
  961. return;
  962. }
  963. }
  964. /* Invalid signals are ignored */
  965. NODE_DBG ( "Invalid signal issued: %08x", handle);
  966. }
  967. /*
  968. * Initialise the task handle callback for a given priority.
  969. */
  970. static int task_init_handler (void) {
  971. int p, qlen = TASK_DEFAULT_QUEUE_LEN;
  972. for (p = 0; p < TASK_PRIORITY_COUNT; p++){
  973. TQB.task_Q[p] = (os_event_t *) malloc( sizeof(os_event_t)*qlen );
  974. if (TQB.task_Q[p]) {
  975. os_memset(TQB.task_Q[p], 0, sizeof(os_event_t)*qlen);
  976. system_os_task(platform_task_dispatch, p, TQB.task_Q[p], TASK_DEFAULT_QUEUE_LEN);
  977. } else {
  978. NODE_DBG ( "Malloc failure in platform_task_init_handler" );
  979. return PLATFORM_ERR;
  980. }
  981. }
  982. }
  983. /*
  984. * Allocate a task handle in the relevant TCB.task_Q. Note that these Qs are resized
  985. * as needed growing in 4 unit bricks. No GC is adopted so handles are permanently
  986. * allocated during boot life. This isn't an issue in practice as only a few handles
  987. * are created per priority during application init and the more volitile Lua tasks
  988. * are allocated in the Lua registery using the luaX interface which is layered on
  989. * this mechanism.
  990. */
  991. platform_task_handle_t platform_task_get_id (platform_task_callback_t t) {
  992. if ( (TQB.task_count & (TH_ALLOCATION_BRICK - 1)) == 0 ) {
  993. TQB.task_func = (platform_task_callback_t *) realloc(
  994. TQB.task_func,
  995. sizeof(platform_task_callback_t) * (TQB.task_count+TH_ALLOCATION_BRICK));
  996. if (!TQB.task_func) {
  997. NODE_DBG ( "Malloc failure in platform_task_get_id");
  998. return 0;
  999. }
  1000. os_memset (TQB.task_func+TQB.task_count, 0,
  1001. sizeof(platform_task_callback_t)*TH_ALLOCATION_BRICK);
  1002. }
  1003. TQB.task_func[TQB.task_count++] = t;
  1004. return TH_MONIKER + ((TQB.task_count-1) << TH_SHIFT);
  1005. }
  1006. bool platform_post (uint8 prio, platform_task_handle_t handle, platform_task_param_t par) {
  1007. return system_os_post(prio, handle | prio, par);
  1008. }