platform.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954
  1. // Platform-dependent functions and includes
  2. #include "platform.h"
  3. #include "common.h"
  4. #include "c_stdio.h"
  5. #include "c_string.h"
  6. #include "c_stdlib.h"
  7. #include "llimits.h"
  8. #include "gpio.h"
  9. #include "user_interface.h"
  10. #include "driver/gpio16.h"
  11. #include "driver/i2c_master.h"
  12. #include "driver/spi.h"
  13. #include "driver/uart.h"
  14. #include "driver/sigma_delta.h"
  15. #define INTERRUPT_TYPE_IS_LEVEL(x) ((x) >= GPIO_PIN_INTR_LOLEVEL)
  16. #ifdef GPIO_INTERRUPT_ENABLE
  17. static task_handle_t gpio_task_handle;
  18. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  19. struct gpio_hook_entry {
  20. platform_hook_function func;
  21. uint32_t bits;
  22. };
  23. struct gpio_hook {
  24. struct gpio_hook_entry *entry;
  25. uint32_t all_bits;
  26. uint32_t count;
  27. };
  28. static struct gpio_hook platform_gpio_hook;
  29. #endif
  30. #endif
  31. static const int uart_bitrates[] = {
  32. BIT_RATE_300,
  33. BIT_RATE_600,
  34. BIT_RATE_1200,
  35. BIT_RATE_2400,
  36. BIT_RATE_4800,
  37. BIT_RATE_9600,
  38. BIT_RATE_19200,
  39. BIT_RATE_31250,
  40. BIT_RATE_38400,
  41. BIT_RATE_57600,
  42. BIT_RATE_74880,
  43. BIT_RATE_115200,
  44. BIT_RATE_230400,
  45. BIT_RATE_256000,
  46. BIT_RATE_460800,
  47. BIT_RATE_921600,
  48. BIT_RATE_1843200,
  49. BIT_RATE_3686400
  50. };
  51. int platform_init()
  52. {
  53. // Setup the various forward and reverse mappings for the pins
  54. get_pin_map();
  55. cmn_platform_init();
  56. // All done
  57. return PLATFORM_OK;
  58. }
  59. // ****************************************************************************
  60. // KEY_LED functions
  61. uint8_t platform_key_led( uint8_t level){
  62. uint8_t temp;
  63. gpio16_output_set(1); // set to high first, for reading key low level
  64. gpio16_input_conf();
  65. temp = gpio16_input_get();
  66. gpio16_output_conf();
  67. gpio16_output_set(level);
  68. return temp;
  69. }
  70. // ****************************************************************************
  71. // GPIO functions
  72. /*
  73. * Set GPIO mode to output. Optionally in RAM helper because interrupts are dsabled
  74. */
  75. static void NO_INTR_CODE set_gpio_no_interrupt(uint8 pin, uint8_t push_pull) {
  76. unsigned pnum = pin_num[pin];
  77. ETS_GPIO_INTR_DISABLE();
  78. #ifdef GPIO_INTERRUPT_ENABLE
  79. pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
  80. #endif
  81. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  82. //disable interrupt
  83. gpio_pin_intr_state_set(GPIO_ID_PIN(pnum), GPIO_PIN_INTR_DISABLE);
  84. //clear interrupt status
  85. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pnum));
  86. // configure push-pull vs open-drain
  87. if (push_pull) {
  88. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  89. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) &
  90. (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
  91. } else {
  92. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  93. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) |
  94. GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //enable open drain;
  95. }
  96. ETS_GPIO_INTR_ENABLE();
  97. }
  98. /*
  99. * Set GPIO mode to interrupt. Optionally RAM helper because interrupts are dsabled
  100. */
  101. #ifdef GPIO_INTERRUPT_ENABLE
  102. static void NO_INTR_CODE set_gpio_interrupt(uint8 pin) {
  103. ETS_GPIO_INTR_DISABLE();
  104. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  105. GPIO_DIS_OUTPUT(pin_num[pin]);
  106. gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  107. GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
  108. | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
  109. | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
  110. ETS_GPIO_INTR_ENABLE();
  111. }
  112. #endif
  113. int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
  114. {
  115. NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n", pin_mux[pin], pin_func[pin]);
  116. if (pin >= NUM_GPIO)
  117. return -1;
  118. if(pin == 0){
  119. if(mode==PLATFORM_GPIO_INPUT)
  120. gpio16_input_conf();
  121. else
  122. gpio16_output_conf();
  123. return 1;
  124. }
  125. #ifdef LUA_USE_MODULES_PWM
  126. platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
  127. #endif
  128. if (pull == PLATFORM_GPIO_PULLUP) {
  129. PIN_PULLUP_EN(pin_mux[pin]);
  130. } else {
  131. PIN_PULLUP_DIS(pin_mux[pin]);
  132. }
  133. switch(mode){
  134. case PLATFORM_GPIO_INPUT:
  135. GPIO_DIS_OUTPUT(pin_num[pin]);
  136. set_gpio_no_interrupt(pin, TRUE);
  137. break;
  138. case PLATFORM_GPIO_OUTPUT:
  139. set_gpio_no_interrupt(pin, TRUE);
  140. GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, BIT(pin_num[pin]));
  141. break;
  142. case PLATFORM_GPIO_OPENDRAIN:
  143. set_gpio_no_interrupt(pin, FALSE);
  144. GPIO_REG_WRITE(GPIO_ENABLE_W1TS_ADDRESS, BIT(pin_num[pin]));
  145. break;
  146. #ifdef GPIO_INTERRUPT_ENABLE
  147. case PLATFORM_GPIO_INT:
  148. set_gpio_interrupt(pin);
  149. break;
  150. #endif
  151. default:
  152. break;
  153. }
  154. return 1;
  155. }
  156. int platform_gpio_write( unsigned pin, unsigned level )
  157. {
  158. // NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
  159. if (pin >= NUM_GPIO)
  160. return -1;
  161. if(pin == 0){
  162. gpio16_output_conf();
  163. gpio16_output_set(level);
  164. return 1;
  165. }
  166. GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
  167. }
  168. int platform_gpio_read( unsigned pin )
  169. {
  170. // NODE_DBG("Function platform_gpio_read() is called. pin:%d\n",GPIO_ID_PIN(pin_num[pin]));
  171. if (pin >= NUM_GPIO)
  172. return -1;
  173. if(pin == 0){
  174. // gpio16_input_conf();
  175. return 0x1 & gpio16_input_get();
  176. }
  177. // GPIO_DIS_OUTPUT(pin_num[pin]);
  178. return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
  179. }
  180. #ifdef GPIO_INTERRUPT_ENABLE
  181. static void ICACHE_RAM_ATTR platform_gpio_intr_dispatcher (void *dummy){
  182. uint32 j=0;
  183. uint32 gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  184. uint32 now = system_get_time();
  185. UNUSED(dummy);
  186. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  187. if (gpio_status & platform_gpio_hook.all_bits) {
  188. for (j = 0; j < platform_gpio_hook.count; j++) {
  189. if (gpio_status & platform_gpio_hook.entry[j].bits)
  190. gpio_status = (platform_gpio_hook.entry[j].func)(gpio_status);
  191. }
  192. }
  193. #endif
  194. /*
  195. * gpio_status is a bit map where bit 0 is set if unmapped gpio pin 0 (pin3) has
  196. * triggered the ISR. bit 1 if unmapped gpio pin 1 (pin10=U0TXD), etc. Since this
  197. * is the ISR, it makes sense to optimize this by doing a fast scan of the status
  198. * and reverse mapping any set bits.
  199. */
  200. for (j = 0; gpio_status>0; j++, gpio_status >>= 1) {
  201. if (gpio_status&1) {
  202. int i = pin_num_inv[j];
  203. if (pin_int_type[i]) {
  204. uint16_t diff = pin_counter[i].seen ^ pin_counter[i].reported;
  205. pin_counter[i].seen = 0x7fff & (pin_counter[i].seen + 1);
  206. if (INTERRUPT_TYPE_IS_LEVEL(pin_int_type[i])) {
  207. //disable interrupt
  208. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  209. }
  210. //clear interrupt status
  211. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  212. if (diff == 0 || diff & 0x8000) {
  213. uint32 level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(j));
  214. if (!task_post_high (gpio_task_handle, (now << 8) + (i<<1) + level)) {
  215. // If we fail to post, then try on the next interrupt
  216. pin_counter[i].seen |= 0x8000;
  217. }
  218. // We re-enable the interrupt when we execute the callback (if level)
  219. }
  220. } else {
  221. // this is an unexpected interrupt so shut it off for now
  222. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  223. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  224. }
  225. }
  226. }
  227. }
  228. void platform_gpio_init( task_handle_t gpio_task )
  229. {
  230. gpio_task_handle = gpio_task;
  231. ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, NULL);
  232. }
  233. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  234. /*
  235. * Register an ISR hook to be called from the GPIO ISR for a given GPIO bitmask.
  236. * This routine is only called a few times so has been optimised for size and
  237. * the unregister is a special case when the bits are 0.
  238. *
  239. * Each hook function can only be registered once. If it is re-registered
  240. * then the hooked bits are just updated to the new value.
  241. */
  242. int platform_gpio_register_intr_hook(uint32_t bits, platform_hook_function hook)
  243. {
  244. struct gpio_hook nh, oh = platform_gpio_hook;
  245. int i, j;
  246. if (!hook) {
  247. // Cannot register or unregister null hook
  248. return 0;
  249. }
  250. int delete_slot = -1;
  251. // If hook already registered, just update the bits
  252. for (i=0; i<oh.count; i++) {
  253. if (hook == oh.entry[i].func) {
  254. if (!bits) {
  255. // Unregister if move to zero bits
  256. delete_slot = i;
  257. break;
  258. }
  259. if (bits & (oh.all_bits & ~oh.entry[i].bits)) {
  260. // Attempt to hook an already hooked bit
  261. return 0;
  262. }
  263. // Update the hooked bits (in the right order)
  264. uint32_t old_bits = oh.entry[i].bits;
  265. *(volatile uint32_t *) &oh.entry[i].bits = bits;
  266. *(volatile uint32_t *) &oh.all_bits = (oh.all_bits & ~old_bits) | bits;
  267. return 1;
  268. }
  269. }
  270. // This must be the register new hook / delete old hook
  271. if (delete_slot < 0) {
  272. if (bits & oh.all_bits) {
  273. return 0; // Attempt to hook already hooked bits
  274. }
  275. nh.count = oh.count + 1; // register a new hook
  276. } else {
  277. nh.count = oh.count - 1; // unregister an old hook
  278. }
  279. // These return NULL if the count = 0 so only error check if > 0)
  280. nh.entry = c_malloc( nh.count * sizeof(*(nh.entry)) );
  281. if (nh.count && !(nh.entry)) {
  282. return 0; // Allocation failure
  283. }
  284. for (i=0, j=0; i<oh.count; i++) {
  285. // Don't copy if this is the entry to delete
  286. if (i != delete_slot) {
  287. nh.entry[j++] = oh.entry[i];
  288. }
  289. }
  290. if (delete_slot < 0) { // for a register add the hook to the tail and set the all bits
  291. nh.entry[j].bits = bits;
  292. nh.entry[j].func = hook;
  293. nh.all_bits = oh.all_bits | bits;
  294. } else { // for an unregister clear the matching all bits
  295. nh.all_bits = oh.all_bits & (~oh.entry[delete_slot].bits);
  296. }
  297. ETS_GPIO_INTR_DISABLE();
  298. // This is a structure copy, so interrupts need to be disabled
  299. platform_gpio_hook = nh;
  300. ETS_GPIO_INTR_ENABLE();
  301. c_free(oh.entry);
  302. return 1;
  303. }
  304. #endif // GPIO_INTERRUPT_HOOK_ENABLE
  305. /*
  306. * Initialise GPIO interrupt mode. Optionally in RAM because interrupts are disabled
  307. */
  308. void NO_INTR_CODE platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
  309. {
  310. if (platform_gpio_exists(pin)) {
  311. ETS_GPIO_INTR_DISABLE();
  312. //clear interrupt status
  313. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  314. pin_int_type[pin] = type;
  315. //enable interrupt
  316. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
  317. ETS_GPIO_INTR_ENABLE();
  318. }
  319. }
  320. #endif
  321. // ****************************************************************************
  322. // UART
  323. // TODO: Support timeouts.
  324. // UartDev is defined and initialized in rom code.
  325. extern UartDevice UartDev;
  326. uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits )
  327. {
  328. switch( baud )
  329. {
  330. case BIT_RATE_300:
  331. case BIT_RATE_600:
  332. case BIT_RATE_1200:
  333. case BIT_RATE_2400:
  334. case BIT_RATE_4800:
  335. case BIT_RATE_9600:
  336. case BIT_RATE_19200:
  337. case BIT_RATE_31250:
  338. case BIT_RATE_38400:
  339. case BIT_RATE_57600:
  340. case BIT_RATE_74880:
  341. case BIT_RATE_115200:
  342. case BIT_RATE_230400:
  343. case BIT_RATE_256000:
  344. case BIT_RATE_460800:
  345. case BIT_RATE_921600:
  346. case BIT_RATE_1843200:
  347. case BIT_RATE_3686400:
  348. UartDev.baut_rate = baud;
  349. break;
  350. default:
  351. UartDev.baut_rate = BIT_RATE_9600;
  352. break;
  353. }
  354. switch( databits )
  355. {
  356. case 5:
  357. UartDev.data_bits = FIVE_BITS;
  358. break;
  359. case 6:
  360. UartDev.data_bits = SIX_BITS;
  361. break;
  362. case 7:
  363. UartDev.data_bits = SEVEN_BITS;
  364. break;
  365. case 8:
  366. UartDev.data_bits = EIGHT_BITS;
  367. break;
  368. default:
  369. UartDev.data_bits = EIGHT_BITS;
  370. break;
  371. }
  372. switch (stopbits)
  373. {
  374. case PLATFORM_UART_STOPBITS_1_5:
  375. UartDev.stop_bits = ONE_HALF_STOP_BIT;
  376. break;
  377. case PLATFORM_UART_STOPBITS_2:
  378. UartDev.stop_bits = TWO_STOP_BIT;
  379. break;
  380. default:
  381. UartDev.stop_bits = ONE_STOP_BIT;
  382. break;
  383. }
  384. switch (parity)
  385. {
  386. case PLATFORM_UART_PARITY_EVEN:
  387. UartDev.parity = EVEN_BITS;
  388. UartDev.exist_parity = STICK_PARITY_EN;
  389. break;
  390. case PLATFORM_UART_PARITY_ODD:
  391. UartDev.parity = ODD_BITS;
  392. UartDev.exist_parity = STICK_PARITY_EN;
  393. break;
  394. default:
  395. UartDev.parity = NONE_BITS;
  396. UartDev.exist_parity = STICK_PARITY_DIS;
  397. break;
  398. }
  399. uart_setup(id);
  400. return baud;
  401. }
  402. void platform_uart_get_config(unsigned id, uint32_t *baudp, uint32_t *databitsp, uint32_t *parityp, uint32_t *stopbitsp) {
  403. UartConfig config = uart_get_config(id);
  404. int i;
  405. int offset = config.baut_rate;
  406. for (i = 0; i < sizeof(uart_bitrates) / sizeof(uart_bitrates[0]); i++) {
  407. int diff = config.baut_rate - uart_bitrates[i];
  408. if (diff < 0) {
  409. diff = -diff;
  410. }
  411. if (diff < offset) {
  412. offset = diff;
  413. *baudp = uart_bitrates[i];
  414. }
  415. }
  416. switch( config.data_bits )
  417. {
  418. case FIVE_BITS:
  419. *databitsp = 5;
  420. break;
  421. case SIX_BITS:
  422. *databitsp = 6;
  423. break;
  424. case SEVEN_BITS:
  425. *databitsp = 7;
  426. break;
  427. case EIGHT_BITS:
  428. default:
  429. *databitsp = 8;
  430. break;
  431. }
  432. switch (config.stop_bits)
  433. {
  434. case ONE_HALF_STOP_BIT:
  435. *stopbitsp = PLATFORM_UART_STOPBITS_1_5;
  436. break;
  437. case TWO_STOP_BIT:
  438. *stopbitsp = PLATFORM_UART_STOPBITS_2;
  439. break;
  440. default:
  441. *stopbitsp = PLATFORM_UART_STOPBITS_1;
  442. break;
  443. }
  444. if (config.exist_parity == STICK_PARITY_DIS) {
  445. *parityp = PLATFORM_UART_PARITY_NONE;
  446. } else if (config.parity == EVEN_BITS) {
  447. *parityp = PLATFORM_UART_PARITY_EVEN;
  448. } else {
  449. *parityp = PLATFORM_UART_PARITY_ODD;
  450. }
  451. }
  452. // if set=1, then alternate serial output pins are used. (15=rx, 13=tx)
  453. void platform_uart_alt( int set )
  454. {
  455. uart0_alt( set );
  456. return;
  457. }
  458. // Send: version with and without mux
  459. void platform_uart_send( unsigned id, u8 data )
  460. {
  461. uart_tx_one_char(id, data);
  462. }
  463. // ****************************************************************************
  464. // PWMs
  465. static uint16_t pwms_duty[NUM_PWM] = {0};
  466. void platform_pwm_init()
  467. {
  468. int i;
  469. for(i=0;i<NUM_PWM;i++){
  470. pwms_duty[i] = DUTY(0);
  471. }
  472. pwm_init(500, NULL);
  473. // NODE_DBG("Function pwms_init() is called.\n");
  474. }
  475. // Return the PWM clock
  476. // NOTE: Can't find a function to query for the period set for the timer,
  477. // therefore using the struct.
  478. // This may require adjustment if driver libraries are updated.
  479. uint32_t platform_pwm_get_clock( unsigned pin )
  480. {
  481. // NODE_DBG("Function platform_pwm_get_clock() is called.\n");
  482. if( pin >= NUM_PWM)
  483. return 0;
  484. if(!pwm_exist(pin))
  485. return 0;
  486. return (uint32_t)pwm_get_freq(pin);
  487. }
  488. // Set the PWM clock
  489. uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
  490. {
  491. // NODE_DBG("Function platform_pwm_set_clock() is called.\n");
  492. if( pin >= NUM_PWM)
  493. return 0;
  494. if(!pwm_exist(pin))
  495. return 0;
  496. pwm_set_freq((uint16_t)clock, pin);
  497. pwm_start();
  498. return (uint32_t)pwm_get_freq( pin );
  499. }
  500. uint32_t platform_pwm_get_duty( unsigned pin )
  501. {
  502. // NODE_DBG("Function platform_pwm_get_duty() is called.\n");
  503. if( pin < NUM_PWM){
  504. if(!pwm_exist(pin))
  505. return 0;
  506. // return NORMAL_DUTY(pwm_get_duty(pin));
  507. return pwms_duty[pin];
  508. }
  509. return 0;
  510. }
  511. // Set the PWM duty
  512. uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
  513. {
  514. // NODE_DBG("Function platform_pwm_set_duty() is called.\n");
  515. if ( pin < NUM_PWM)
  516. {
  517. if(!pwm_exist(pin))
  518. return 0;
  519. pwm_set_duty(DUTY(duty), pin);
  520. } else {
  521. return 0;
  522. }
  523. pwm_start();
  524. pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
  525. return pwms_duty[pin];
  526. }
  527. uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
  528. {
  529. uint32_t clock;
  530. if ( pin < NUM_PWM)
  531. {
  532. platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
  533. if(!pwm_add(pin))
  534. return 0;
  535. // pwm_set_duty(DUTY(duty), pin);
  536. pwm_set_duty(0, pin);
  537. pwms_duty[pin] = duty;
  538. pwm_set_freq((uint16_t)frequency, pin);
  539. } else {
  540. return 0;
  541. }
  542. clock = platform_pwm_get_clock( pin );
  543. if (!pwm_start()) {
  544. return 0;
  545. }
  546. return clock;
  547. }
  548. void platform_pwm_close( unsigned pin )
  549. {
  550. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  551. if ( pin < NUM_PWM)
  552. {
  553. pwm_delete(pin);
  554. pwm_start();
  555. }
  556. }
  557. bool platform_pwm_start( unsigned pin )
  558. {
  559. // NODE_DBG("Function platform_pwm_start() is called.\n");
  560. if ( pin < NUM_PWM)
  561. {
  562. if(!pwm_exist(pin))
  563. return FALSE;
  564. pwm_set_duty(DUTY(pwms_duty[pin]), pin);
  565. return pwm_start();
  566. }
  567. return FALSE;
  568. }
  569. void platform_pwm_stop( unsigned pin )
  570. {
  571. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  572. if ( pin < NUM_PWM)
  573. {
  574. if(!pwm_exist(pin))
  575. return;
  576. pwm_set_duty(0, pin);
  577. pwm_start();
  578. }
  579. }
  580. // *****************************************************************************
  581. // Sigma-Delta platform interface
  582. uint8_t platform_sigma_delta_setup( uint8_t pin )
  583. {
  584. if (pin < 1 || pin > NUM_GPIO)
  585. return 0;
  586. sigma_delta_setup();
  587. // set GPIO output mode for this pin
  588. platform_gpio_mode( pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT );
  589. platform_gpio_write( pin, PLATFORM_GPIO_LOW );
  590. // enable sigma-delta on this pin
  591. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  592. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  593. GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
  594. return 1;
  595. }
  596. uint8_t platform_sigma_delta_close( uint8_t pin )
  597. {
  598. if (pin < 1 || pin > NUM_GPIO)
  599. return 0;
  600. sigma_delta_stop();
  601. // set GPIO input mode for this pin
  602. platform_gpio_mode( pin, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP );
  603. // CONNECT GPIO TO PIN PAD
  604. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  605. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  606. GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
  607. return 1;
  608. }
  609. void platform_sigma_delta_set_pwmduty( uint8_t duty )
  610. {
  611. uint8_t target = 0, prescale = 0;
  612. target = duty > 128 ? 256 - duty : duty;
  613. prescale = target == 0 ? 0 : target-1;
  614. //freq = 80000 (khz) /256 /duty_target * (prescale+1)
  615. sigma_delta_set_prescale_target( prescale, duty );
  616. }
  617. void platform_sigma_delta_set_prescale( uint8_t prescale )
  618. {
  619. sigma_delta_set_prescale_target( prescale, -1 );
  620. }
  621. void ICACHE_RAM_ATTR platform_sigma_delta_set_target( uint8_t target )
  622. {
  623. sigma_delta_set_prescale_target( -1, target );
  624. }
  625. // *****************************************************************************
  626. // I2C platform interface
  627. uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed ){
  628. if (sda >= NUM_GPIO || scl >= NUM_GPIO)
  629. return 0;
  630. // platform_pwm_close(sda);
  631. // platform_pwm_close(scl);
  632. // disable gpio interrupt first
  633. platform_gpio_mode(sda, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // inside this func call platform_pwm_close
  634. platform_gpio_mode(scl, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // disable gpio interrupt first
  635. i2c_master_gpio_init(sda, scl);
  636. return PLATFORM_I2C_SPEED_SLOW;
  637. }
  638. void platform_i2c_send_start( unsigned id ){
  639. i2c_master_start();
  640. }
  641. void platform_i2c_send_stop( unsigned id ){
  642. i2c_master_stop();
  643. }
  644. int platform_i2c_send_address( unsigned id, uint16_t address, int direction ){
  645. // Convert enum codes to R/w bit value.
  646. // If TX == 0 and RX == 1, this test will be removed by the compiler
  647. if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
  648. PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
  649. direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
  650. }
  651. i2c_master_writeByte( (uint8_t) ((address << 1) | direction ));
  652. // Low-level returns nack (0=acked); we return ack (1=acked).
  653. return ! i2c_master_getAck();
  654. }
  655. int platform_i2c_send_byte( unsigned id, uint8_t data ){
  656. i2c_master_writeByte(data);
  657. // Low-level returns nack (0=acked); we return ack (1=acked).
  658. return ! i2c_master_getAck();
  659. }
  660. int platform_i2c_recv_byte( unsigned id, int ack ){
  661. uint8_t r = i2c_master_readByte();
  662. i2c_master_setAck( !ack );
  663. return r;
  664. }
  665. // *****************************************************************************
  666. // SPI platform interface
  667. uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div )
  668. {
  669. spi_master_init( id, cpol, cpha, clock_div );
  670. // all platform functions assume LSB order for MOSI & MISO buffer
  671. spi_mast_byte_order( id, SPI_ORDER_LSB );
  672. return 1;
  673. }
  674. int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
  675. {
  676. if (bitlen > 32)
  677. return PLATFORM_ERR;
  678. spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
  679. return PLATFORM_OK;
  680. }
  681. spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data )
  682. {
  683. if (bitlen > 32)
  684. return 0;
  685. spi_mast_set_mosi( id, 0, bitlen, data );
  686. spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
  687. return spi_mast_get_miso( id, 0, bitlen );
  688. }
  689. int platform_spi_blkwrite( uint8_t id, size_t len, const uint8_t *data )
  690. {
  691. while (len > 0) {
  692. size_t chunk_len = len > 64 ? 64 : len;
  693. spi_mast_blkset( id, chunk_len * 8, data );
  694. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, 0 );
  695. data = &(data[chunk_len]);
  696. len -= chunk_len;
  697. }
  698. return PLATFORM_OK;
  699. }
  700. int platform_spi_blkread( uint8_t id, size_t len, uint8_t *data )
  701. {
  702. uint8_t mosi_idle[64];
  703. os_memset( (void *)mosi_idle, 0xff, len > 64 ? 64 : len );
  704. while (len > 0 ) {
  705. size_t chunk_len = len > 64 ? 64 : len;
  706. spi_mast_blkset( id, chunk_len * 8, mosi_idle );
  707. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, -1 );
  708. spi_mast_blkget( id, chunk_len * 8, data );
  709. data = &(data[chunk_len]);
  710. len -= chunk_len;
  711. }
  712. return PLATFORM_OK;
  713. }
  714. int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
  715. uint8_t addr_bitlen, spi_data_type addr_data,
  716. uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen )
  717. {
  718. if ((cmd_bitlen > 16) ||
  719. (addr_bitlen > 32) ||
  720. (mosi_bitlen > 512) ||
  721. (dummy_bitlen > 256) ||
  722. (miso_bitlen > 512))
  723. return PLATFORM_ERR;
  724. spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
  725. return PLATFORM_OK;
  726. }
  727. // ****************************************************************************
  728. // Flash access functions
  729. /*
  730. * Assumptions:
  731. * > toaddr is INTERNAL_FLASH_WRITE_UNIT_SIZE aligned
  732. * > size is a multiple of INTERNAL_FLASH_WRITE_UNIT_SIZE
  733. */
  734. uint32_t platform_s_flash_write( const void *from, uint32_t toaddr, uint32_t size )
  735. {
  736. SpiFlashOpResult r;
  737. const uint32_t blkmask = INTERNAL_FLASH_WRITE_UNIT_SIZE - 1;
  738. uint32_t *apbuf = NULL;
  739. uint32_t fromaddr = (uint32_t)from;
  740. if( (fromaddr & blkmask ) || (fromaddr >= INTERNAL_FLASH_MAPPED_ADDRESS)) {
  741. apbuf = (uint32_t *)c_malloc(size);
  742. if(!apbuf)
  743. return 0;
  744. c_memcpy(apbuf, from, size);
  745. }
  746. system_soft_wdt_feed ();
  747. r = flash_write(toaddr, apbuf?(uint32 *)apbuf:(uint32 *)from, size);
  748. if(apbuf)
  749. c_free(apbuf);
  750. if(SPI_FLASH_RESULT_OK == r)
  751. return size;
  752. else{
  753. NODE_ERR( "ERROR in flash_write: r=%d at %p\n", r, toaddr);
  754. return 0;
  755. }
  756. }
  757. /*
  758. * Assumptions:
  759. * > fromaddr is INTERNAL_FLASH_READ_UNIT_SIZE aligned
  760. * > size is a multiple of INTERNAL_FLASH_READ_UNIT_SIZE
  761. */
  762. uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
  763. {
  764. if (size==0)
  765. return 0;
  766. SpiFlashOpResult r;
  767. system_soft_wdt_feed ();
  768. const uint32_t blkmask = (INTERNAL_FLASH_READ_UNIT_SIZE - 1);
  769. if( ((uint32_t)to) & blkmask )
  770. {
  771. uint32_t size2=size-INTERNAL_FLASH_READ_UNIT_SIZE;
  772. uint32* to2=(uint32*)((((uint32_t)to)&(~blkmask))+INTERNAL_FLASH_READ_UNIT_SIZE);
  773. r = flash_read(fromaddr, to2, size2);
  774. if(SPI_FLASH_RESULT_OK == r)
  775. {
  776. os_memmove(to,to2,size2);
  777. char back[ INTERNAL_FLASH_READ_UNIT_SIZE ] __attribute__ ((aligned(INTERNAL_FLASH_READ_UNIT_SIZE)));
  778. r=flash_read(fromaddr+size2,(uint32*)back,INTERNAL_FLASH_READ_UNIT_SIZE);
  779. os_memcpy((uint8_t*)to+size2,back,INTERNAL_FLASH_READ_UNIT_SIZE);
  780. }
  781. }
  782. else
  783. r = flash_read(fromaddr, (uint32 *)to, size);
  784. if(SPI_FLASH_RESULT_OK == r)
  785. return size;
  786. else{
  787. NODE_ERR( "ERROR in flash_read: r=%d at %p\n", r, fromaddr);
  788. return 0;
  789. }
  790. }
  791. int platform_flash_erase_sector( uint32_t sector_id )
  792. {
  793. NODE_DBG( "flash_erase_sector(%u)\n", sector_id);
  794. system_soft_wdt_feed ();
  795. return flash_erase( sector_id ) == SPI_FLASH_RESULT_OK ? PLATFORM_OK : PLATFORM_ERR;
  796. }
  797. static uint32_t flash_map_meg_offset (void) {
  798. uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
  799. if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
  800. return -1;
  801. uint32_t m0 = (cache_ctrl & CACHE_FLASH_MAPPED0) ? 0x100000 : 0;
  802. uint32_t m1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 0x200000 : 0;
  803. return m0 + m1;
  804. }
  805. uint32_t platform_flash_mapped2phys (uint32_t mapped_addr) {
  806. uint32_t meg = flash_map_meg_offset();
  807. return (meg&1) ? -1 : mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg ;
  808. }
  809. uint32_t platform_flash_phys2mapped (uint32_t phys_addr) {
  810. uint32_t meg = flash_map_meg_offset();
  811. return (meg&1) ? -1 : phys_addr + INTERNAL_FLASH_MAPPED_ADDRESS - meg;
  812. }
  813. void* platform_print_deprecation_note( const char *msg, const char *time_frame)
  814. {
  815. c_printf( "Warning, deprecated API! %s. It will be removed %s. See documentation for details.\n", msg, time_frame );
  816. }