spi_register.h 7.1 KB

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  1. /*
  2. * Copyright (c) 2010 - 2011 Espressif System
  3. *
  4. */
  5. #ifndef SPI_REGISTER_H_INCLUDED
  6. #define SPI_REGISTER_H_INCLUDED
  7. #define REG_SPI_BASE(i) (0x60000200-i*0x100)
  8. #define SPI_CMD(i) (REG_SPI_BASE(i) + 0x0)
  9. #define SPI_FLASH_READ BIT31
  10. #define SPI_FLASH_WREN BIT30
  11. #define SPI_FLASH_WRDI BIT29
  12. #define SPI_FLASH_RDID BIT28
  13. #define SPI_FLASH_RDSR BIT27
  14. #define SPI_FLASH_WRSR BIT26
  15. #define SPI_FLASH_PP BIT25
  16. #define SPI_FLASH_SE BIT24
  17. #define SPI_FLASH_BE BIT23
  18. #define SPI_FLASH_CE BIT22
  19. #define SPI_FLASH_RES BIT20
  20. #define SPI_USR (BIT(18))
  21. #define SPI_ADDR(i) (REG_SPI_BASE(i) + 0x4)
  22. #define SPI_CTRL(i) (REG_SPI_BASE(i) + 0x8)
  23. #define SPI_WR_BIT_ORDER (BIT(26))
  24. #define SPI_RD_BIT_ORDER (BIT(25))
  25. #define SPI_QIO_MODE (BIT(24))
  26. #define SPI_DIO_MODE (BIT(23))
  27. #define SPI_QOUT_MODE (BIT(20))
  28. #define SPI_DOUT_MODE (BIT(14))
  29. #define SPI_FASTRD_MODE (BIT(13))
  30. #define SPI_CTRL1(i) (REG_SPI_BASE(i) + 0xc)
  31. #define SPI_CS_HOLD_DELAY 0xf
  32. #define SPI_CS_HOLD_DELAY_S 28
  33. #define SPI_CS_HOLD_DELAY_RES 0xfff
  34. #define SPI_CS_HOLD_DELAY_RES_S 16
  35. #define SPI_RD_STATUS(i) (REG_SPI_BASE(i) + 0x10)
  36. #define SPI_CTRL2(i) (REG_SPI_BASE(i) + 0x14)
  37. #define SPI_CS_DELAY_NUM 0x0000000F
  38. #define SPI_CS_DELAY_NUM_S 28
  39. #define SPI_CS_DELAY_MODE 0x00000003
  40. #define SPI_CS_DELAY_MODE_S 26
  41. #define SPI_MOSI_DELAY_NUM 0x00000007
  42. #define SPI_MOSI_DELAY_NUM_S 23
  43. #define SPI_MOSI_DELAY_MODE 0x00000003
  44. #define SPI_MOSI_DELAY_MODE_S 21
  45. #define SPI_MISO_DELAY_NUM 0x00000007
  46. #define SPI_MISO_DELAY_NUM_S 18
  47. #define SPI_MISO_DELAY_MODE 0x00000003
  48. #define SPI_MISO_DELAY_MODE_S 16
  49. #define SPI_CLOCK(i) (REG_SPI_BASE(i) + 0x18)
  50. #define SPI_CLK_EQU_SYSCLK (BIT(31))
  51. #define SPI_CLKDIV_PRE 0x00001FFF
  52. #define SPI_CLKDIV_PRE_S 18
  53. #define SPI_CLKCNT_N 0x0000003F
  54. #define SPI_CLKCNT_N_S 12
  55. #define SPI_CLKCNT_H 0x0000003F
  56. #define SPI_CLKCNT_H_S 6
  57. #define SPI_CLKCNT_L 0x0000003F
  58. #define SPI_CLKCNT_L_S 0
  59. #define SPI_USER(i) (REG_SPI_BASE(i) + 0x1C)
  60. #define SPI_USR_COMMAND (BIT(31))
  61. #define SPI_USR_ADDR (BIT(30))
  62. #define SPI_USR_DUMMY (BIT(29))
  63. #define SPI_USR_MISO (BIT(28))
  64. #define SPI_USR_MOSI (BIT(27))
  65. #define SPI_USR_MOSI_HIGHPART (BIT(25))
  66. #define SPI_USR_MISO_HIGHPART (BIT(24))
  67. #define SPI_SIO (BIT(16))
  68. #define SPI_FWRITE_QIO (BIT(15))
  69. #define SPI_FWRITE_DIO (BIT(14))
  70. #define SPI_FWRITE_QUAD (BIT(13))
  71. #define SPI_FWRITE_DUAL (BIT(12))
  72. #define SPI_WR_BYTE_ORDER (BIT(11))
  73. #define SPI_RD_BYTE_ORDER (BIT(10))
  74. #define SPI_CK_OUT_EDGE (BIT(7))
  75. #define SPI_CK_I_EDGE (BIT(6))
  76. #define SPI_CS_SETUP (BIT(5))
  77. #define SPI_CS_HOLD (BIT(4))
  78. #define SPI_FLASH_MODE (BIT(2))
  79. #define SPI_USER1(i) (REG_SPI_BASE(i) + 0x20)
  80. #define SPI_USR_ADDR_BITLEN 0x0000003F
  81. #define SPI_USR_ADDR_BITLEN_S 26
  82. #define SPI_USR_MOSI_BITLEN 0x000001FF
  83. #define SPI_USR_MOSI_BITLEN_S 17
  84. #define SPI_USR_MISO_BITLEN 0x000001FF
  85. #define SPI_USR_MISO_BITLEN_S 8
  86. #define SPI_USR_DUMMY_CYCLELEN 0x000000FF
  87. #define SPI_USR_DUMMY_CYCLELEN_S 0
  88. #define SPI_USER2(i) (REG_SPI_BASE(i) + 0x24)
  89. #define SPI_USR_COMMAND_BITLEN 0x0000000F
  90. #define SPI_USR_COMMAND_BITLEN_S 28
  91. #define SPI_USR_COMMAND_VALUE 0x0000FFFF
  92. #define SPI_USR_COMMAND_VALUE_S 0
  93. #define SPI_WR_STATUS(i) (REG_SPI_BASE(i) + 0x28)
  94. #define SPI_PIN(i) (REG_SPI_BASE(i) + 0x2C)
  95. #define SPI_CS2_DIS (BIT(2))
  96. #define SPI_CS1_DIS (BIT(1))
  97. #define SPI_CS0_DIS (BIT(0))
  98. #define SPI_SLAVE(i) (REG_SPI_BASE(i) + 0x30)
  99. #define SPI_SYNC_RESET (BIT(31))
  100. #define SPI_SLAVE_MODE (BIT(30))
  101. #define SPI_SLV_WR_RD_BUF_EN (BIT(29))
  102. #define SPI_SLV_WR_RD_STA_EN (BIT(28))
  103. #define SPI_SLV_CMD_DEFINE (BIT(27))
  104. #define SPI_TRANS_CNT 0x0000000F
  105. #define SPI_TRANS_CNT_S 23
  106. #define SPI_TRANS_DONE_EN (BIT(9))
  107. #define SPI_SLV_WR_STA_DONE_EN (BIT(8))
  108. #define SPI_SLV_RD_STA_DONE_EN (BIT(7))
  109. #define SPI_SLV_WR_BUF_DONE_EN (BIT(6))
  110. #define SPI_SLV_RD_BUF_DONE_EN (BIT(5))
  111. #define SLV_SPI_INT_EN 0x0000001f
  112. #define SLV_SPI_INT_EN_S 5
  113. #define SPI_TRANS_DONE (BIT(4))
  114. #define SPI_SLV_WR_STA_DONE (BIT(3))
  115. #define SPI_SLV_RD_STA_DONE (BIT(2))
  116. #define SPI_SLV_WR_BUF_DONE (BIT(1))
  117. #define SPI_SLV_RD_BUF_DONE (BIT(0))
  118. #define SPI_SLAVE1(i) (REG_SPI_BASE(i) + 0x34)
  119. #define SPI_SLV_STATUS_BITLEN 0x0000001F
  120. #define SPI_SLV_STATUS_BITLEN_S 27
  121. #define SPI_SLV_BUF_BITLEN 0x000001FF
  122. #define SPI_SLV_BUF_BITLEN_S 16
  123. #define SPI_SLV_RD_ADDR_BITLEN 0x0000003F
  124. #define SPI_SLV_RD_ADDR_BITLEN_S 10
  125. #define SPI_SLV_WR_ADDR_BITLEN 0x0000003F
  126. #define SPI_SLV_WR_ADDR_BITLEN_S 4
  127. #define SPI_SLV_WRSTA_DUMMY_EN (BIT(3))
  128. #define SPI_SLV_RDSTA_DUMMY_EN (BIT(2))
  129. #define SPI_SLV_WRBUF_DUMMY_EN (BIT(1))
  130. #define SPI_SLV_RDBUF_DUMMY_EN (BIT(0))
  131. #define SPI_SLAVE2(i) (REG_SPI_BASE(i) + 0x38)
  132. #define SPI_SLV_WRBUF_DUMMY_CYCLELEN 0X000000FF
  133. #define SPI_SLV_WRBUF_DUMMY_CYCLELEN_S 24
  134. #define SPI_SLV_RDBUF_DUMMY_CYCLELEN 0X000000FF
  135. #define SPI_SLV_RDBUF_DUMMY_CYCLELEN_S 16
  136. #define SPI_SLV_WRSTR_DUMMY_CYCLELEN 0X000000FF
  137. #define SPI_SLV_WRSTR_DUMMY_CYCLELEN_S 8
  138. #define SPI_SLV_RDSTR_DUMMY_CYCLELEN 0x000000FF
  139. #define SPI_SLV_RDSTR_DUMMY_CYCLELEN_S 0
  140. #define SPI_SLAVE3(i) (REG_SPI_BASE(i) + 0x3C)
  141. #define SPI_SLV_WRSTA_CMD_VALUE 0x000000FF
  142. #define SPI_SLV_WRSTA_CMD_VALUE_S 24
  143. #define SPI_SLV_RDSTA_CMD_VALUE 0x000000FF
  144. #define SPI_SLV_RDSTA_CMD_VALUE_S 16
  145. #define SPI_SLV_WRBUF_CMD_VALUE 0x000000FF
  146. #define SPI_SLV_WRBUF_CMD_VALUE_S 8
  147. #define SPI_SLV_RDBUF_CMD_VALUE 0x000000FF
  148. #define SPI_SLV_RDBUF_CMD_VALUE_S 0
  149. #define SPI_W0(i) (REG_SPI_BASE(i) +0x40)
  150. #define SPI_W1(i) (REG_SPI_BASE(i) +0x44)
  151. #define SPI_W2(i) (REG_SPI_BASE(i) +0x48)
  152. #define SPI_W3(i) (REG_SPI_BASE(i) +0x4C)
  153. #define SPI_W4(i) (REG_SPI_BASE(i) +0x50)
  154. #define SPI_W5(i) (REG_SPI_BASE(i) +0x54)
  155. #define SPI_W6(i) (REG_SPI_BASE(i) +0x58)
  156. #define SPI_W7(i) (REG_SPI_BASE(i) +0x5C)
  157. #define SPI_W8(i) (REG_SPI_BASE(i) +0x60)
  158. #define SPI_W9(i) (REG_SPI_BASE(i) +0x64)
  159. #define SPI_W10(i) (REG_SPI_BASE(i) +0x68)
  160. #define SPI_W11(i) (REG_SPI_BASE(i) +0x6C)
  161. #define SPI_W12(i) (REG_SPI_BASE(i) +0x70)
  162. #define SPI_W13(i) (REG_SPI_BASE(i) +0x74)
  163. #define SPI_W14(i) (REG_SPI_BASE(i) +0x78)
  164. #define SPI_W15(i) (REG_SPI_BASE(i) +0x7C)
  165. #define SPI_EXT2(i) (REG_SPI_BASE(i) + 0xF8)
  166. #define SPI_EXT3(i) (REG_SPI_BASE(i) + 0xFC)
  167. #define SPI_INT_HOLD_ENA 0x00000003
  168. #define SPI_INT_HOLD_ENA_S 0
  169. #endif // SPI_REGISTER_H_INCLUDED