spi_overlap.c 14 KB

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  1. #include "driver/spi_overlap.h"
  2. #include "driver/spi.h"
  3. #include "gpio.h"
  4. #define SPI_FLASH_READ_MODE_MASK 0x196000
  5. #define WAIT_HSPI_IDLE() while(READ_PERI_REG(SPI_EXT2(HSPI))||(READ_PERI_REG(SPI_CMD(HSPI))&0xfffc0000));
  6. #define CONF_HSPI_CLK_DIV(div) WRITE_PERI_REG(SPI_CLOCK(HSPI), (((div<<1)+1)<<12)+(div<<6)+(div<<1)+1)
  7. #define HSPI_FALLING_EDGE_SAMPLE() SET_PERI_REG_MASK(SPI_USER(HSPI), SPI_CK_OUT_EDGE)
  8. #define HSPI_RISING_EDGE_SAMPLE() CLEAR_PERI_REG_MASK(SPI_USER(HSPI), SPI_CK_OUT_EDGE)
  9. #define ACTIVE_HSPI_CS0 CLEAR_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS0_DIS);\
  10. SET_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS1_DIS |SPI_CS2_DIS)
  11. #define ACTIVE_HSPI_CS1 CLEAR_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS1_DIS);\
  12. SET_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS0_DIS |SPI_CS2_DIS)
  13. #define ACTIVE_HSPI_CS2 CLEAR_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS2_DIS);\
  14. SET_PERI_REG_MASK(SPI_PIN(HSPI), SPI_CS0_DIS |SPI_CS1_DIS)
  15. #define ENABLE_HSPI_DEV_CS() PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2)
  16. #define DISABLE_HSPI_DEV_CS() GPIO_OUTPUT_SET(15, 1);\
  17. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, FUNC_GPIO15)
  18. struct hspi_device_register hspi_dev_reg;
  19. /******************************************************************************
  20. * FunctionName : hspi_overlap_init
  21. * Description : enable hspi and spi module overlap mode
  22. *******************************************************************************/
  23. void ICACHE_FLASH_ATTR
  24. hspi_overlap_init(void)
  25. {
  26. //hspi overlap to spi, two spi masters on cspi
  27. SET_PERI_REG_MASK(HOST_INF_SEL, reg_cspi_overlap);
  28. //set higher priority for spi than hspi
  29. SET_PERI_REG_MASK(SPI_EXT3(SPI),0x1);
  30. SET_PERI_REG_MASK(SPI_EXT3(HSPI),0x3);
  31. SET_PERI_REG_MASK(SPI_USER(HSPI), BIT(5));
  32. }
  33. /******************************************************************************
  34. * FunctionName : hspi_overlap_deinit
  35. * Description : recover hspi and spi module from overlap mode
  36. *******************************************************************************/
  37. void ICACHE_FLASH_ATTR
  38. hspi_overlap_deinit(void)
  39. {
  40. //hspi overlap to spi, two spi masters on cspi
  41. CLEAR_PERI_REG_MASK(HOST_INF_SEL, reg_cspi_overlap);
  42. //set higher priority for spi than hspi
  43. CLEAR_PERI_REG_MASK(SPI_EXT3(SPI),0x1);
  44. CLEAR_PERI_REG_MASK(SPI_EXT3(HSPI),0x3);
  45. CLEAR_PERI_REG_MASK(SPI_USER(HSPI), BIT(5));
  46. }
  47. /******************************************************************************
  48. * FunctionName : spi_reg_backup
  49. * Description : backup SPI normal operation register value and disable CPU cache to modify some flash registers.
  50. * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
  51. *******************************************************************************/
  52. void ICACHE_FLASH_ATTR
  53. spi_reg_backup(uint8 spi_no,uint32* backup_mem)
  54. {
  55. if(spi_no>1) return; //handle invalid input number
  56. backup_mem[PERIPHS_IO_MUX_BACKUP] =READ_PERI_REG(PERIPHS_IO_MUX);
  57. backup_mem[SPI_USER_BACKUP] =READ_PERI_REG(SPI_USER(spi_no));
  58. backup_mem[SPI_CTRL_BACKUP] =READ_PERI_REG(SPI_CTRL(spi_no));
  59. backup_mem[SPI_CLOCK_BACKUP] =READ_PERI_REG(SPI_CLOCK(spi_no));
  60. backup_mem[SPI_USER1_BACKUP] =READ_PERI_REG(SPI_USER1(spi_no));
  61. backup_mem[SPI_USER2_BACKUP] =READ_PERI_REG(SPI_USER2(spi_no));
  62. backup_mem[SPI_CMD_BACKUP] =READ_PERI_REG(SPI_CMD(spi_no));
  63. backup_mem[SPI_PIN_BACKUP] =READ_PERI_REG(SPI_PIN(spi_no));
  64. backup_mem[SPI_SLAVE_BACKUP] =READ_PERI_REG(SPI_SLAVE(spi_no));
  65. }
  66. /******************************************************************************
  67. * FunctionName : spi_reg_recover
  68. * Description : recover SPI normal operation register value and enable CPU cache.
  69. * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
  70. *******************************************************************************/
  71. void ICACHE_FLASH_ATTR
  72. spi_reg_recover(uint8 spi_no,uint32* backup_mem)
  73. {
  74. if(spi_no>1) return; //handle invalid input number
  75. // WRITE_PERI_REG(PERIPHS_IO_MUX, backup_mem[PERIPHS_IO_MUX_BACKUP]);
  76. WRITE_PERI_REG(SPI_USER(spi_no), backup_mem[SPI_USER_BACKUP]);
  77. WRITE_PERI_REG(SPI_CTRL(spi_no), backup_mem[SPI_CTRL_BACKUP]);
  78. WRITE_PERI_REG(SPI_CLOCK(spi_no), backup_mem[SPI_CLOCK_BACKUP]);
  79. WRITE_PERI_REG(SPI_USER1(spi_no), backup_mem[SPI_USER1_BACKUP]);
  80. WRITE_PERI_REG(SPI_USER2(spi_no), backup_mem[SPI_USER2_BACKUP]);
  81. WRITE_PERI_REG(SPI_CMD(spi_no), backup_mem[SPI_CMD_BACKUP]);
  82. WRITE_PERI_REG(SPI_PIN(spi_no), backup_mem[SPI_PIN_BACKUP]);
  83. // WRITE_PERI_REG(SPI_SLAVE(spi_no), backup_mem[SPI_SLAVE_BACKUP]);
  84. }
  85. void ICACHE_FLASH_ATTR
  86. hspi_master_dev_init(uint8 dev_no,uint8 clk_polar,uint8 clk_div)
  87. {
  88. uint32 regtemp;
  89. if((dev_no>3)||(clk_polar>1)||(clk_div>0x1f))
  90. {
  91. os_printf("hspi_master_dev_init parameter is out of range!\n\r");
  92. return;
  93. }
  94. WAIT_HSPI_IDLE();
  95. if(!hspi_dev_reg.hspi_reg_backup_flag){
  96. if(READ_PERI_REG(PERIPHS_IO_MUX)&BIT8){
  97. hspi_dev_reg.spi_io_80m=1;
  98. SET_PERI_REG_MASK(SPI_CLOCK(HSPI),SPI_CLK_EQU_SYSCLK);
  99. }else{
  100. hspi_dev_reg.spi_io_80m=0;
  101. CLEAR_PERI_REG_MASK(SPI_CLOCK(HSPI),SPI_CLK_EQU_SYSCLK);
  102. }
  103. regtemp=READ_PERI_REG(SPI_CTRL(SPI))&SPI_FLASH_READ_MODE_MASK;
  104. CLEAR_PERI_REG_MASK(SPI_CTRL(HSPI), SPI_FLASH_READ_MODE_MASK);
  105. SET_PERI_REG_MASK(SPI_CTRL(HSPI), regtemp);
  106. spi_reg_backup(HSPI, hspi_dev_reg.hspi_flash_reg_backup);
  107. spi_master_init(HSPI);
  108. spi_reg_backup(HSPI, hspi_dev_reg.hspi_dev_reg_backup);
  109. hspi_dev_reg.hspi_reg_backup_flag=1;
  110. // spi_reg_recover(HSPI, hspi_dev_reg.hspi_flash_reg_backup);
  111. hspi_dev_reg.selected_dev_num=HSPI_IDLE;
  112. }
  113. hspi_dev_reg.hspi_dev_conf[dev_no].active=1;
  114. hspi_dev_reg.hspi_dev_conf[dev_no].clk_div=clk_div;
  115. hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar=clk_polar;
  116. switch(dev_no){
  117. case HSPI_CS_DEV :
  118. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);
  119. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);
  120. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2);
  121. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2);
  122. CLEAR_PERI_REG_MASK(PERIPHS_IO_MUX, BIT9);
  123. break;
  124. case SPI_CS1_DEV :
  125. PIN_FUNC_SELECT(PERIPHS_IO_MUX_U0TXD_U, FUNC_SPI_CS1);
  126. if(hspi_dev_reg.spi_io_80m){
  127. os_printf("SPI CS1 device must work at 80Mhz");
  128. }
  129. break;
  130. case SPI_CS2_DEV :
  131. PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_SPI_CS2);
  132. if(hspi_dev_reg.spi_io_80m){
  133. os_printf("SPI CS2 device must work at 80Mhz");
  134. }
  135. break;
  136. default: break;
  137. }
  138. }
  139. void ICACHE_FLASH_ATTR
  140. hspi_dev_sel(uint8 dev_no)
  141. {
  142. uint32 regval;
  143. if(dev_no>3){
  144. os_printf("hspi_dev_sel parameter is out of range!\n\r");
  145. return;
  146. }
  147. if(!hspi_dev_reg.hspi_dev_conf[dev_no].active){
  148. os_printf("device%d has not been initialized!\n\r",dev_no);
  149. return;
  150. }
  151. switch(hspi_dev_reg.selected_dev_num){
  152. case HSPI_CS_DEV:
  153. if((dev_no==SPI_CS1_DEV)||(dev_no==SPI_CS2_DEV)){
  154. WAIT_HSPI_IDLE();
  155. DISABLE_HSPI_DEV_CS();
  156. hspi_overlap_init();
  157. if(hspi_dev_reg.spi_io_80m) {SET_PERI_REG_MASK(SPI_CLOCK(HSPI), SPI_CLK_EQU_SYSCLK);}
  158. else {CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);}
  159. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  160. else {HSPI_RISING_EDGE_SAMPLE();}
  161. if(dev_no==SPI_CS1_DEV) {ACTIVE_HSPI_CS1;}
  162. else {ACTIVE_HSPI_CS2;}
  163. }
  164. else if(dev_no==SPI_CS0_FLASH){
  165. WAIT_HSPI_IDLE();
  166. DISABLE_HSPI_DEV_CS();
  167. hspi_overlap_init();
  168. spi_reg_recover(HSPI, hspi_dev_reg.hspi_flash_reg_backup);
  169. if(hspi_dev_reg.spi_io_80m) {SET_PERI_REG_MASK(SPI_CLOCK(HSPI), SPI_CLK_EQU_SYSCLK);}
  170. HSPI_RISING_EDGE_SAMPLE();
  171. ACTIVE_HSPI_CS0 ;
  172. }
  173. break;
  174. case SPI_CS1_DEV:
  175. if(dev_no==SPI_CS2_DEV){
  176. WAIT_HSPI_IDLE();
  177. if(!hspi_dev_reg.spi_io_80m) {CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);}
  178. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  179. else {HSPI_RISING_EDGE_SAMPLE();}
  180. ACTIVE_HSPI_CS2;
  181. }
  182. else if(dev_no==SPI_CS0_FLASH){
  183. WAIT_HSPI_IDLE();
  184. spi_reg_recover(HSPI, hspi_dev_reg.hspi_flash_reg_backup);
  185. HSPI_RISING_EDGE_SAMPLE();
  186. ACTIVE_HSPI_CS0;
  187. }
  188. else if(dev_no==HSPI_CS_DEV){
  189. WAIT_HSPI_IDLE();
  190. ENABLE_HSPI_DEV_CS();
  191. hspi_overlap_deinit();
  192. CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);
  193. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  194. else {HSPI_RISING_EDGE_SAMPLE();}
  195. ACTIVE_HSPI_CS0;
  196. }
  197. break;
  198. case SPI_CS2_DEV:
  199. if(dev_no==SPI_CS1_DEV){
  200. WAIT_HSPI_IDLE();
  201. if(!hspi_dev_reg.spi_io_80m) {CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);}
  202. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  203. else {HSPI_RISING_EDGE_SAMPLE();}
  204. ACTIVE_HSPI_CS1;
  205. }
  206. else if(dev_no==SPI_CS0_FLASH){
  207. WAIT_HSPI_IDLE();
  208. spi_reg_recover(HSPI, hspi_dev_reg.hspi_flash_reg_backup);
  209. HSPI_RISING_EDGE_SAMPLE();
  210. ACTIVE_HSPI_CS0;
  211. }
  212. else if(dev_no==HSPI_CS_DEV){
  213. WAIT_HSPI_IDLE();
  214. ENABLE_HSPI_DEV_CS();
  215. hspi_overlap_deinit();
  216. CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);
  217. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  218. else {HSPI_RISING_EDGE_SAMPLE();}
  219. ACTIVE_HSPI_CS0;
  220. }
  221. break;
  222. case SPI_CS0_FLASH:
  223. if((dev_no==SPI_CS1_DEV)||(dev_no==SPI_CS2_DEV)){
  224. WAIT_HSPI_IDLE();
  225. spi_reg_recover(HSPI, hspi_dev_reg.hspi_dev_reg_backup);
  226. if(hspi_dev_reg.spi_io_80m) {SET_PERI_REG_MASK(SPI_CLOCK(HSPI), SPI_CLK_EQU_SYSCLK);}
  227. else {CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);}
  228. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  229. else {HSPI_RISING_EDGE_SAMPLE();}
  230. if(dev_no==SPI_CS1_DEV) {ACTIVE_HSPI_CS1;}
  231. else {ACTIVE_HSPI_CS2;}
  232. }
  233. else if(dev_no==HSPI_CS_DEV){
  234. WAIT_HSPI_IDLE();
  235. ENABLE_HSPI_DEV_CS();
  236. hspi_overlap_deinit();
  237. spi_reg_recover(HSPI, hspi_dev_reg.hspi_dev_reg_backup);
  238. CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);
  239. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  240. else {HSPI_RISING_EDGE_SAMPLE();}
  241. ACTIVE_HSPI_CS0;
  242. }
  243. break;
  244. default:
  245. if((dev_no==SPI_CS1_DEV)||(dev_no==SPI_CS2_DEV)){
  246. WAIT_HSPI_IDLE();
  247. DISABLE_HSPI_DEV_CS();
  248. hspi_overlap_init();
  249. spi_reg_recover(HSPI, hspi_dev_reg.hspi_dev_reg_backup);
  250. if(hspi_dev_reg.spi_io_80m) {SET_PERI_REG_MASK(SPI_CLOCK(HSPI), SPI_CLK_EQU_SYSCLK);}
  251. else {CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);}
  252. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  253. else {HSPI_RISING_EDGE_SAMPLE();}
  254. if(dev_no==SPI_CS1_DEV) {ACTIVE_HSPI_CS1;}
  255. else {ACTIVE_HSPI_CS2;}
  256. }
  257. else if(dev_no==SPI_CS0_FLASH){
  258. WAIT_HSPI_IDLE();
  259. DISABLE_HSPI_DEV_CS();
  260. hspi_overlap_init();
  261. spi_reg_recover(HSPI, hspi_dev_reg.hspi_flash_reg_backup);
  262. if(hspi_dev_reg.spi_io_80m) {SET_PERI_REG_MASK(SPI_CLOCK(HSPI), SPI_CLK_EQU_SYSCLK);}
  263. HSPI_RISING_EDGE_SAMPLE();
  264. ACTIVE_HSPI_CS0 ;
  265. }
  266. else if(dev_no==HSPI_CS_DEV){
  267. WAIT_HSPI_IDLE();
  268. ENABLE_HSPI_DEV_CS();
  269. hspi_overlap_deinit();
  270. spi_reg_recover(HSPI, hspi_dev_reg.hspi_dev_reg_backup);
  271. CONF_HSPI_CLK_DIV(hspi_dev_reg.hspi_dev_conf[dev_no].clk_div);
  272. if(hspi_dev_reg.hspi_dev_conf[dev_no].clk_polar) {HSPI_FALLING_EDGE_SAMPLE();}
  273. else {HSPI_RISING_EDGE_SAMPLE();}
  274. ACTIVE_HSPI_CS0;
  275. }
  276. break;
  277. }
  278. hspi_dev_reg.selected_dev_num=dev_no;
  279. }
  280. /******************************************************************************
  281. * FunctionName : spi_read_data
  282. * Description : use hspi to read flash data for stability test
  283. * Parameters : SpiFlashChip * spi-- flash parameter structure pointer
  284. * uint32 flash_addr--flash start address
  285. * uint32 * addr_dest--start address for preped destination memory space
  286. * uint32 byte_length--length of the data which needs to be read from flash
  287. *******************************************************************************/
  288. SpiFlashOpResult ICACHE_FLASH_ATTR
  289. hspi_overlap_read_flash_data(SpiFlashChip * spi, uint32 flash_addr, uint32 * addr_dest, uint32 byte_length)
  290. {
  291. uint32 temp_addr,reg_tmp;
  292. sint32 temp_length;
  293. uint8 i;
  294. uint8 remain_word_num;
  295. hspi_dev_sel(SPI_CS0_FLASH);
  296. //address range check
  297. if ((flash_addr+byte_length) > (spi->chip_size))
  298. {
  299. return SPI_FLASH_RESULT_ERR;
  300. }
  301. temp_addr = flash_addr;
  302. temp_length = byte_length;
  303. while(temp_length > 0)
  304. {
  305. if(temp_length >= SPI_BUFF_BYTE_NUM)
  306. {
  307. // reg_tmp=((temp_addr&0xff)<<16)|(temp_addr&0xff00)|((temp_addr&0xff0000)>>16)|(SPI_BUFF_BYTE_NUM << SPI_FLASH_BYTES_LEN);
  308. reg_tmp= temp_addr |(SPI_BUFF_BYTE_NUM<< SPI_FLASH_BYTES_LEN) ;
  309. WRITE_PERI_REG(SPI_ADDR(HSPI), reg_tmp);
  310. WRITE_PERI_REG(SPI_CMD(HSPI), SPI_FLASH_READ);
  311. while(READ_PERI_REG(SPI_CMD(HSPI)) != 0);
  312. for(i=0; i<(SPI_BUFF_BYTE_NUM>>2);i++)
  313. {
  314. *addr_dest++ = READ_PERI_REG(SPI_W0(HSPI)+i*4);
  315. }
  316. temp_length = temp_length - SPI_BUFF_BYTE_NUM;
  317. temp_addr = temp_addr + SPI_BUFF_BYTE_NUM;
  318. }
  319. else
  320. {
  321. WRITE_PERI_REG(SPI_ADDR(HSPI), temp_addr |(temp_length << SPI_FLASH_BYTES_LEN ));
  322. WRITE_PERI_REG(SPI_CMD(HSPI), SPI_FLASH_READ);
  323. while(READ_PERI_REG(SPI_CMD(HSPI)) != 0);
  324. remain_word_num = (0== (temp_length&0x3))? (temp_length>>2) : (temp_length>>2)+1;
  325. for (i=0; i<remain_word_num; i++)
  326. {
  327. *addr_dest++ = READ_PERI_REG(SPI_W0(HSPI)+i*4);
  328. }
  329. temp_length = 0;
  330. }
  331. }
  332. return SPI_FLASH_RESULT_OK;
  333. }
  334. void ICACHE_FLASH_ATTR
  335. hspi_overlap_flash_init(void)
  336. {
  337. hspi_master_dev_init(SPI_CS0_FLASH,0,0);
  338. spi_flash_set_read_func(hspi_overlap_read_flash_data);
  339. }