spi.c 17 KB

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  1. #include "driver/spi.h"
  2. #include "driver/spi_overlap.h"
  3. #define CACHE_FLASH_CTRL_REG 0x3ff0000C
  4. #define CACHE_FLUSH_START_BIT BIT0
  5. #define CACHE_EMPTY_FLAG_BIT BIT1
  6. /******************************************************************************
  7. * FunctionName : cache_flush
  8. * Description : clear all the cpu cache data for stability test.
  9. *******************************************************************************/
  10. void cache_flush(void)
  11. {
  12. while(READ_PERI_REG(CACHE_FLASH_CTRL_REG)&CACHE_EMPTY_FLAG_BIT) {
  13. CLEAR_PERI_REG_MASK(CACHE_FLASH_CTRL_REG, CACHE_FLUSH_START_BIT);
  14. SET_PERI_REG_MASK(CACHE_FLASH_CTRL_REG, CACHE_FLUSH_START_BIT);
  15. }
  16. while(!(READ_PERI_REG(CACHE_FLASH_CTRL_REG)&CACHE_EMPTY_FLAG_BIT));
  17. CLEAR_PERI_REG_MASK(CACHE_FLASH_CTRL_REG, CACHE_FLUSH_START_BIT);
  18. }
  19. /******************************************************************************
  20. * FunctionName : spi_master_init
  21. * Description : SPI master initial function for common byte units transmission
  22. * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
  23. *******************************************************************************/
  24. void ICACHE_FLASH_ATTR
  25. spi_master_init(uint8 spi_no)
  26. {
  27. uint32 regvalue;
  28. if(spi_no>1) return; //handle invalid input number
  29. SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_CS_SETUP|SPI_CS_HOLD|SPI_USR_COMMAND);
  30. CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE);
  31. WRITE_PERI_REG(SPI_CLOCK(spi_no),
  32. ((3&SPI_CLKCNT_N)<<SPI_CLKCNT_N_S)|
  33. ((1&SPI_CLKCNT_H)<<SPI_CLKCNT_H_S)|
  34. ((3&SPI_CLKCNT_L)<<SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div
  35. }
  36. /******************************************************************************
  37. * FunctionName : spi_lcd_9bit_write
  38. * Description : SPI 9bits transmission function for driving LCD TM035PDZV36
  39. * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
  40. * uint8 high_bit - first high bit of the data, 0 is for "0",the other value 1-255 is for "1"
  41. * uint8 low_8bit- the rest 8bits of the data.
  42. *******************************************************************************/
  43. void ICACHE_FLASH_ATTR
  44. spi_lcd_9bit_write(uint8 spi_no,uint8 high_bit,uint8 low_8bit)
  45. {
  46. uint32 regvalue;
  47. uint8 bytetemp;
  48. if(spi_no>1) return; //handle invalid input number
  49. if(high_bit) bytetemp=(low_8bit>>1)|0x80;
  50. else bytetemp=(low_8bit>>1)&0x7f;
  51. regvalue= ((8&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S)|((uint32)bytetemp); //configure transmission variable,9bit transmission length and first 8 command bit
  52. if(low_8bit&0x01) regvalue|=BIT15; //write the 9th bit
  53. while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR); //waiting for spi module available
  54. WRITE_PERI_REG(SPI_USER2(spi_no), regvalue); //write command and command length into spi reg
  55. SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR); //transmission start
  56. // while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR);
  57. }
  58. /******************************************************************************
  59. * FunctionName : spi_mast_byte_write
  60. * Description : SPI master 1 byte transmission function
  61. * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
  62. * uint8 data- transmitted data
  63. *******************************************************************************/
  64. void ICACHE_FLASH_ATTR
  65. spi_mast_byte_write(uint8 spi_no,uint8 data)
  66. {
  67. uint32 regvalue;
  68. if(spi_no>1) return; //handle invalid input number
  69. while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR);
  70. CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI|SPI_USR_MISO);
  71. //SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1,
  72. // bit15-0 is cmd value.
  73. WRITE_PERI_REG(SPI_USER2(spi_no),
  74. ((7&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S)|((uint32)data));
  75. SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR);
  76. while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR);
  77. }
  78. /******************************************************************************
  79. * FunctionName : spi_byte_write_espslave
  80. * Description : SPI master 1 byte transmission function for esp8266 slave,
  81. * transmit 1byte data to esp8266 slave buffer needs 16bit transmission ,
  82. * first byte is command 0x04 to write slave buffer, second byte is data
  83. * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
  84. * uint8 data- transmitted data
  85. *******************************************************************************/
  86. void ICACHE_FLASH_ATTR
  87. spi_byte_write_espslave(uint8 spi_no,uint8 data)
  88. {
  89. uint32 regvalue;
  90. if(spi_no>1) return; //handle invalid input number
  91. while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR);
  92. SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI);
  93. CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO|SPI_USR_ADDR|SPI_USR_DUMMY);
  94. //SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1,
  95. // bit15-0 is cmd value.
  96. //0x70000000 is for 8bits cmd, 0x04 is eps8266 slave write cmd value
  97. WRITE_PERI_REG(SPI_USER2(spi_no),
  98. ((7&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S)|4);
  99. WRITE_PERI_REG(SPI_W0(spi_no), (uint32)(data));
  100. SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR);
  101. }
  102. /******************************************************************************
  103. * FunctionName : spi_byte_read_espslave
  104. * Description : SPI master 1 byte read function for esp8266 slave,
  105. * read 1byte data from esp8266 slave buffer needs 16bit transmission ,
  106. * first byte is command 0x06 to read slave buffer, second byte is recieved data
  107. * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
  108. * uint8* data- recieved data address
  109. *******************************************************************************/
  110. void ICACHE_FLASH_ATTR
  111. spi_byte_read_espslave(uint8 spi_no,uint8 *data)
  112. {
  113. uint32 regvalue;
  114. if(spi_no>1) return; //handle invalid input number
  115. while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR);
  116. SET_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MISO);
  117. CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_USR_MOSI|SPI_USR_ADDR|SPI_USR_DUMMY);
  118. //SPI_FLASH_USER2 bit28-31 is cmd length,cmd bit length is value(0-15)+1,
  119. // bit15-0 is cmd value.
  120. //0x70000000 is for 8bits cmd, 0x06 is eps8266 slave read cmd value
  121. WRITE_PERI_REG(SPI_USER2(spi_no),
  122. ((7&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S)|6);
  123. SET_PERI_REG_MASK(SPI_CMD(spi_no), SPI_USR);
  124. while(READ_PERI_REG(SPI_CMD(spi_no))&SPI_USR);
  125. *data=(uint8)(READ_PERI_REG(SPI_W0(spi_no))&0xff);
  126. }
  127. /******************************************************************************
  128. * FunctionName : spi_slave_init
  129. * Description : SPI slave mode initial funtion, including mode setting,
  130. * IO setting, transmission interrupt opening, interrupt function registration
  131. * Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
  132. * uint8 data_len - read&write data pack length,using byte as unit,the range is 1-32
  133. *******************************************************************************/
  134. void ICACHE_FLASH_ATTR
  135. spi_slave_init(uint8 spi_no,uint8 data_len)
  136. {
  137. uint32 regvalue;
  138. uint32 data_bit_len;
  139. if(spi_no>1)
  140. return; //handle invalid input number
  141. if(data_len<=1) data_bit_len=7;
  142. else if(data_len>=32) data_bit_len=0xff;
  143. else data_bit_len=(data_len<<3)-1;
  144. //clear bit9,bit8 of reg PERIPHS_IO_MUX
  145. //bit9 should be cleared when HSPI clock doesn't equal CPU clock
  146. //bit8 should be cleared when SPI clock doesn't equal CPU clock
  147. ////WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9//TEST
  148. if(spi_no==SPI){
  149. PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);//configure io to spi mode
  150. PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);//configure io to spi mode
  151. PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);//configure io to spi mode
  152. PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);//configure io to spi mode
  153. }else if(spi_no==HSPI){
  154. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);//configure io to spi mode
  155. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);//configure io to spi mode
  156. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2);//configure io to spi mode
  157. PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDO_U, 2);//configure io to spi mode
  158. }
  159. //regvalue=READ_PERI_REG(SPI_FLASH_SLAVE(spi_no));
  160. //slave mode,slave use buffers which are register "SPI_FLASH_C0~C15", enable trans done isr
  161. //set bit 30 bit 29 bit9,bit9 is trans done isr mask
  162. SET_PERI_REG_MASK( SPI_SLAVE(spi_no),
  163. SPI_SLAVE_MODE|SPI_SLV_WR_RD_BUF_EN|
  164. SPI_SLV_WR_BUF_DONE_EN|SPI_SLV_RD_BUF_DONE_EN|
  165. SPI_SLV_WR_STA_DONE_EN|SPI_SLV_RD_STA_DONE_EN|
  166. SPI_TRANS_DONE_EN);
  167. //disable general trans intr
  168. //CLEAR_PERI_REG_MASK(SPI_SLAVE(spi_no),SPI_TRANS_DONE_EN);
  169. CLEAR_PERI_REG_MASK(SPI_USER(spi_no), SPI_FLASH_MODE);//disable flash operation mode
  170. SET_PERI_REG_MASK(SPI_USER(spi_no),SPI_USR_MISO_HIGHPART);//SLAVE SEND DATA BUFFER IN C8-C15
  171. //////**************RUN WHEN SLAVE RECIEVE*******************///////
  172. //tow lines below is to configure spi timing.
  173. SET_PERI_REG_MASK(SPI_CTRL2(spi_no),(0x2&SPI_MOSI_DELAY_NUM)<<SPI_MOSI_DELAY_NUM_S) ;//delay num
  174. os_printf("SPI_CTRL2 is %08x\n",READ_PERI_REG(SPI_CTRL2(spi_no)));
  175. WRITE_PERI_REG(SPI_CLOCK(spi_no), 0);
  176. /////***************************************************//////
  177. //set 8 bit slave command length, because slave must have at least one bit addr,
  178. //8 bit slave+8bit addr, so master device first 2 bytes can be regarded as a command
  179. //and the following bytes are datas,
  180. //32 bytes input wil be stored in SPI_FLASH_C0-C7
  181. //32 bytes output data should be set to SPI_FLASH_C8-C15
  182. WRITE_PERI_REG(SPI_USER2(spi_no), (0x7&SPI_USR_COMMAND_BITLEN)<<SPI_USR_COMMAND_BITLEN_S); //0x70000000
  183. //set 8 bit slave recieve buffer length, the buffer is SPI_FLASH_C0-C7
  184. //set 8 bit slave status register, which is the low 8 bit of register "SPI_FLASH_STATUS"
  185. SET_PERI_REG_MASK(SPI_SLAVE1(spi_no), ((data_bit_len&SPI_SLV_BUF_BITLEN)<< SPI_SLV_BUF_BITLEN_S)|
  186. ((0x7&SPI_SLV_STATUS_BITLEN)<<SPI_SLV_STATUS_BITLEN_S)|
  187. ((0x7&SPI_SLV_WR_ADDR_BITLEN)<<SPI_SLV_WR_ADDR_BITLEN_S)|
  188. ((0x7&SPI_SLV_RD_ADDR_BITLEN)<<SPI_SLV_RD_ADDR_BITLEN_S));
  189. SET_PERI_REG_MASK(SPI_PIN(spi_no),BIT19);//BIT19
  190. //maybe enable slave transmission liston
  191. SET_PERI_REG_MASK(SPI_CMD(spi_no),SPI_USR);
  192. //register level2 isr function, which contains spi, hspi and i2s events
  193. ETS_SPI_INTR_ATTACH(spi_slave_isr_handler,NULL);
  194. //enable level2 isr, which contains spi, hspi and i2s events
  195. ETS_SPI_INTR_ENABLE();
  196. }
  197. /* =============================================================================================
  198. * code below is for spi slave r/w testcase with 2 r/w state lines connected to the spi master mcu
  199. * replace with your own process functions
  200. * find "add system_os_post here" in spi_slave_isr_handler.
  201. * =============================================================================================
  202. */
  203. #ifdef SPI_SLAVE_DEBUG
  204. /******************************************************************************
  205. * FunctionName : hspi_master_readwrite_repeat
  206. * Description : SPI master test function for reading and writing esp8266 slave buffer,
  207. the function uses HSPI module
  208. *******************************************************************************/
  209. os_timer_t timer2;
  210. void hspi_master_readwrite_repeat(void)
  211. {
  212. static uint8 data=0;
  213. uint8 temp;
  214. os_timer_disarm(&timer2);
  215. spi_byte_read_espslave(HSPI,&temp);
  216. temp++;
  217. spi_byte_write_espslave(HSPI,temp);
  218. os_timer_setfn(&timer2, (os_timer_func_t *)hspi_master_readwrite_repeat, NULL);
  219. os_timer_arm(&timer2, 500, 0);
  220. }
  221. #endif
  222. /******************************************************************************
  223. * FunctionName : spi_slave_isr_handler
  224. * Description : SPI interrupt function, SPI HSPI and I2S interrupt can trig this function
  225. some basic operation like clear isr flag has been done,
  226. and it is availible for adding user coder in the funtion
  227. * Parameters : void *para- function parameter address, which has been registered in function spi_slave_init
  228. *******************************************************************************/
  229. #include "gpio.h"
  230. #include "user_interface.h"
  231. #include "mem.h"
  232. static uint8 spi_data[32] = {0};
  233. static uint8 idx = 0;
  234. static uint8 spi_flg = 0;
  235. #define SPI_MISO
  236. #define SPI_QUEUE_LEN 8
  237. os_event_t * spiQueue;
  238. #define MOSI 0
  239. #define MISO 1
  240. #define STATUS_R_IN_WR 2
  241. #define STATUS_W 3
  242. #define TR_DONE_ALONE 4
  243. #define WR_RD 5
  244. #define DATA_ERROR 6
  245. #define STATUS_R_IN_RD 7
  246. //init the two intr line of slave
  247. //gpio0: wr_ready ,and
  248. //gpio2: rd_ready , controlled by slave
  249. void ICACHE_FLASH_ATTR
  250. gpio_init()
  251. {
  252. PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO0_U, FUNC_GPIO0);
  253. PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO2_U, FUNC_GPIO2);
  254. //PIN_FUNC_SELECT(PERIPHS_IO_MUX_GPIO4_U, FUNC_GPIO4);
  255. GPIO_OUTPUT_SET(0, 1);
  256. GPIO_OUTPUT_SET(2, 0);
  257. //GPIO_OUTPUT_SET(4, 1);
  258. }
  259. void spi_slave_isr_handler(void *para)
  260. {
  261. uint32 regvalue,calvalue;
  262. static uint8 state =0;
  263. uint32 recv_data,send_data;
  264. if(READ_PERI_REG(0x3ff00020)&BIT4){
  265. //following 3 lines is to clear isr signal
  266. CLEAR_PERI_REG_MASK(SPI_SLAVE(SPI), 0x3ff);
  267. }else if(READ_PERI_REG(0x3ff00020)&BIT7){ //bit7 is for hspi isr,
  268. regvalue=READ_PERI_REG(SPI_SLAVE(HSPI));
  269. CLEAR_PERI_REG_MASK(SPI_SLAVE(HSPI),
  270. SPI_TRANS_DONE_EN|
  271. SPI_SLV_WR_STA_DONE_EN|
  272. SPI_SLV_RD_STA_DONE_EN|
  273. SPI_SLV_WR_BUF_DONE_EN|
  274. SPI_SLV_RD_BUF_DONE_EN);
  275. SET_PERI_REG_MASK(SPI_SLAVE(HSPI), SPI_SYNC_RESET);
  276. CLEAR_PERI_REG_MASK(SPI_SLAVE(HSPI),
  277. SPI_TRANS_DONE|
  278. SPI_SLV_WR_STA_DONE|
  279. SPI_SLV_RD_STA_DONE|
  280. SPI_SLV_WR_BUF_DONE|
  281. SPI_SLV_RD_BUF_DONE);
  282. SET_PERI_REG_MASK(SPI_SLAVE(HSPI),
  283. SPI_TRANS_DONE_EN|
  284. SPI_SLV_WR_STA_DONE_EN|
  285. SPI_SLV_RD_STA_DONE_EN|
  286. SPI_SLV_WR_BUF_DONE_EN|
  287. SPI_SLV_RD_BUF_DONE_EN);
  288. if(regvalue&SPI_SLV_WR_BUF_DONE){
  289. GPIO_OUTPUT_SET(0, 0);
  290. idx=0;
  291. while(idx<8){
  292. recv_data=READ_PERI_REG(SPI_W0(HSPI)+(idx<<2));
  293. spi_data[idx<<2] = recv_data&0xff;
  294. spi_data[(idx<<2)+1] = (recv_data>>8)&0xff;
  295. spi_data[(idx<<2)+2] = (recv_data>>16)&0xff;
  296. spi_data[(idx<<2)+3] = (recv_data>>24)&0xff;
  297. idx++;
  298. }
  299. //add system_os_post here
  300. GPIO_OUTPUT_SET(0, 1);
  301. }
  302. if(regvalue&SPI_SLV_RD_BUF_DONE){
  303. //it is necessary to call GPIO_OUTPUT_SET(2, 1), when new data is preped in SPI_W8-15 and needs to be sended.
  304. GPIO_OUTPUT_SET(2, 0);
  305. //add system_os_post here
  306. //system_os_post(USER_TASK_PRIO_1,WR_RD,regvalue);
  307. }
  308. }else if(READ_PERI_REG(0x3ff00020)&BIT9){ //bit7 is for i2s isr,
  309. }
  310. }
  311. #ifdef SPI_SLAVE_DEBUG
  312. void ICACHE_FLASH_ATTR
  313. set_miso_data()
  314. {
  315. if(GPIO_INPUT_GET(2)==0){
  316. WRITE_PERI_REG(SPI_W8(HSPI),0x05040302);
  317. WRITE_PERI_REG(SPI_W9(HSPI),0x09080706);
  318. WRITE_PERI_REG(SPI_W10(HSPI),0x0d0c0b0a);
  319. WRITE_PERI_REG(SPI_W11(HSPI),0x11100f0e);
  320. WRITE_PERI_REG(SPI_W12(HSPI),0x15141312);
  321. WRITE_PERI_REG(SPI_W13(HSPI),0x19181716);
  322. WRITE_PERI_REG(SPI_W14(HSPI),0x1d1c1b1a);
  323. WRITE_PERI_REG(SPI_W15(HSPI),0x21201f1e);
  324. GPIO_OUTPUT_SET(2, 1);
  325. }
  326. }
  327. void ICACHE_FLASH_ATTR
  328. disp_spi_data()
  329. {
  330. uint8 i = 0;
  331. for(i=0;i<32;i++){
  332. os_printf("data %d : 0x%02x\n\r",i,spi_data[i]);
  333. }
  334. //os_printf("d31:0x%02x\n\r",spi_data[31]);
  335. }
  336. void ICACHE_FLASH_ATTR
  337. spi_task(os_event_t *e)
  338. {
  339. uint8 data;
  340. switch(e->sig){
  341. case MOSI:
  342. disp_spi_data();
  343. break;
  344. case STATUS_R_IN_WR :
  345. os_printf("SR ERR in WRPR,Reg:%08x \n",e->par);
  346. break;
  347. case STATUS_W:
  348. os_printf("SW ERR,Reg:%08x\n",e->par);
  349. break;
  350. case TR_DONE_ALONE:
  351. os_printf("TD ALO ERR,Reg:%08x\n",e->par);
  352. break;
  353. case WR_RD:
  354. os_printf("WR&RD ERR,Reg:%08x\n",e->par);
  355. break;
  356. case DATA_ERROR:
  357. os_printf("Data ERR,Reg:%08x\n",e->par);
  358. break;
  359. case STATUS_R_IN_RD :
  360. os_printf("SR ERR in RDPR,Reg:%08x\n",e->par);
  361. break;
  362. default:
  363. break;
  364. }
  365. }
  366. void ICACHE_FLASH_ATTR
  367. spi_task_init(void)
  368. {
  369. spiQueue = (os_event_t*)os_malloc(sizeof(os_event_t)*SPI_QUEUE_LEN);
  370. system_os_task(spi_task,USER_TASK_PRIO_1,spiQueue,SPI_QUEUE_LEN);
  371. }
  372. os_timer_t spi_timer_test;
  373. void ICACHE_FLASH_ATTR
  374. spi_test_init()
  375. {
  376. os_printf("spi init\n\r");
  377. spi_slave_init(HSPI);
  378. os_printf("gpio init\n\r");
  379. gpio_init();
  380. os_printf("spi task init \n\r");
  381. spi_task_init();
  382. #ifdef SPI_MISO
  383. os_printf("spi miso init\n\r");
  384. set_miso_data();
  385. #endif
  386. //os_timer_disarm(&spi_timer_test);
  387. //os_timer_setfn(&spi_timer_test, (os_timer_func_t *)set_miso_data, NULL);//wjl
  388. //os_timer_arm(&spi_timer_test,50,1);
  389. }
  390. #endif