platform.c 24 KB

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  1. // Platform-dependent functions and includes
  2. #include "platform.h"
  3. #include "common.h"
  4. #include "c_stdio.h"
  5. #include "c_string.h"
  6. #include "c_stdlib.h"
  7. #include "llimits.h"
  8. #include "gpio.h"
  9. #include "user_interface.h"
  10. #include "driver/gpio16.h"
  11. #include "driver/i2c_master.h"
  12. #include "driver/spi.h"
  13. #include "driver/uart.h"
  14. #include "driver/sigma_delta.h"
  15. #ifdef GPIO_INTERRUPT_ENABLE
  16. static task_handle_t gpio_task_handle;
  17. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  18. struct gpio_hook_entry {
  19. platform_hook_function func;
  20. uint32_t bits;
  21. };
  22. struct gpio_hook {
  23. struct gpio_hook_entry *entry;
  24. uint32_t all_bits;
  25. uint32_t count;
  26. };
  27. static struct gpio_hook platform_gpio_hook;
  28. #endif
  29. #endif
  30. static const int uart_bitrates[] = {
  31. BIT_RATE_300,
  32. BIT_RATE_600,
  33. BIT_RATE_1200,
  34. BIT_RATE_2400,
  35. BIT_RATE_4800,
  36. BIT_RATE_9600,
  37. BIT_RATE_19200,
  38. BIT_RATE_38400,
  39. BIT_RATE_57600,
  40. BIT_RATE_74880,
  41. BIT_RATE_115200,
  42. BIT_RATE_230400,
  43. BIT_RATE_256000,
  44. BIT_RATE_460800,
  45. BIT_RATE_921600,
  46. BIT_RATE_1843200,
  47. BIT_RATE_3686400
  48. };
  49. int platform_init()
  50. {
  51. // Setup the various forward and reverse mappings for the pins
  52. get_pin_map();
  53. cmn_platform_init();
  54. // All done
  55. return PLATFORM_OK;
  56. }
  57. // ****************************************************************************
  58. // KEY_LED functions
  59. uint8_t platform_key_led( uint8_t level){
  60. uint8_t temp;
  61. gpio16_output_set(1); // set to high first, for reading key low level
  62. gpio16_input_conf();
  63. temp = gpio16_input_get();
  64. gpio16_output_conf();
  65. gpio16_output_set(level);
  66. return temp;
  67. }
  68. // ****************************************************************************
  69. // GPIO functions
  70. /*
  71. * Set GPIO mode to output. Optionally in RAM helper because interrupts are dsabled
  72. */
  73. static void NO_INTR_CODE set_gpio_no_interrupt(uint8 pin, uint8_t push_pull) {
  74. unsigned pnum = pin_num[pin];
  75. ETS_GPIO_INTR_DISABLE();
  76. #ifdef GPIO_INTERRUPT_ENABLE
  77. pin_int_type[pin] = GPIO_PIN_INTR_DISABLE;
  78. #endif
  79. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  80. //disable interrupt
  81. gpio_pin_intr_state_set(GPIO_ID_PIN(pnum), GPIO_PIN_INTR_DISABLE);
  82. //clear interrupt status
  83. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pnum));
  84. // configure push-pull vs open-drain
  85. if (push_pull) {
  86. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  87. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) &
  88. (~ GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE))); //disable open drain;
  89. } else {
  90. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum)),
  91. GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pnum))) |
  92. GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_ENABLE)); //enable open drain;
  93. }
  94. ETS_GPIO_INTR_ENABLE();
  95. }
  96. /*
  97. * Set GPIO mode to interrupt. Optionally RAM helper because interrupts are dsabled
  98. */
  99. #ifdef GPIO_INTERRUPT_ENABLE
  100. static void NO_INTR_CODE set_gpio_interrupt(uint8 pin) {
  101. ETS_GPIO_INTR_DISABLE();
  102. PIN_FUNC_SELECT(pin_mux[pin], pin_func[pin]);
  103. GPIO_DIS_OUTPUT(pin_num[pin]);
  104. gpio_register_set(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  105. GPIO_PIN_INT_TYPE_SET(GPIO_PIN_INTR_DISABLE)
  106. | GPIO_PIN_PAD_DRIVER_SET(GPIO_PAD_DRIVER_DISABLE)
  107. | GPIO_PIN_SOURCE_SET(GPIO_AS_PIN_SOURCE));
  108. ETS_GPIO_INTR_ENABLE();
  109. }
  110. #endif
  111. int platform_gpio_mode( unsigned pin, unsigned mode, unsigned pull )
  112. {
  113. NODE_DBG("Function platform_gpio_mode() is called. pin_mux:%d, func:%d\n", pin_mux[pin], pin_func[pin]);
  114. if (pin >= NUM_GPIO)
  115. return -1;
  116. if(pin == 0){
  117. if(mode==PLATFORM_GPIO_INPUT)
  118. gpio16_input_conf();
  119. else
  120. gpio16_output_conf();
  121. return 1;
  122. }
  123. #ifdef LUA_USE_MODULES_PWM
  124. platform_pwm_close(pin); // closed from pwm module, if it is used in pwm
  125. #endif
  126. if (pull == PLATFORM_GPIO_PULLUP) {
  127. PIN_PULLUP_EN(pin_mux[pin]);
  128. } else {
  129. PIN_PULLUP_DIS(pin_mux[pin]);
  130. }
  131. switch(mode){
  132. case PLATFORM_GPIO_INPUT:
  133. GPIO_DIS_OUTPUT(pin_num[pin]);
  134. /* run on */
  135. case PLATFORM_GPIO_OUTPUT:
  136. set_gpio_no_interrupt(pin, TRUE);
  137. break;
  138. case PLATFORM_GPIO_OPENDRAIN:
  139. set_gpio_no_interrupt(pin, FALSE);
  140. break;
  141. #ifdef GPIO_INTERRUPT_ENABLE
  142. case PLATFORM_GPIO_INT:
  143. set_gpio_interrupt(pin);
  144. break;
  145. #endif
  146. default:
  147. break;
  148. }
  149. return 1;
  150. }
  151. int platform_gpio_write( unsigned pin, unsigned level )
  152. {
  153. // NODE_DBG("Function platform_gpio_write() is called. pin:%d, level:%d\n",GPIO_ID_PIN(pin_num[pin]),level);
  154. if (pin >= NUM_GPIO)
  155. return -1;
  156. if(pin == 0){
  157. gpio16_output_conf();
  158. gpio16_output_set(level);
  159. return 1;
  160. }
  161. GPIO_OUTPUT_SET(GPIO_ID_PIN(pin_num[pin]), level);
  162. }
  163. int platform_gpio_read( unsigned pin )
  164. {
  165. // NODE_DBG("Function platform_gpio_read() is called. pin:%d\n",GPIO_ID_PIN(pin_num[pin]));
  166. if (pin >= NUM_GPIO)
  167. return -1;
  168. if(pin == 0){
  169. // gpio16_input_conf();
  170. return 0x1 & gpio16_input_get();
  171. }
  172. // GPIO_DIS_OUTPUT(pin_num[pin]);
  173. return 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(pin_num[pin]));
  174. }
  175. #ifdef GPIO_INTERRUPT_ENABLE
  176. static void ICACHE_RAM_ATTR platform_gpio_intr_dispatcher (void *dummy){
  177. uint32 j=0;
  178. uint32 gpio_status = GPIO_REG_READ(GPIO_STATUS_ADDRESS);
  179. UNUSED(dummy);
  180. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  181. if (gpio_status & platform_gpio_hook.all_bits) {
  182. for (j = 0; j < platform_gpio_hook.count; j++) {
  183. if (gpio_status & platform_gpio_hook.entry[j].bits)
  184. gpio_status = (platform_gpio_hook.entry[j].func)(gpio_status);
  185. }
  186. }
  187. #endif
  188. /*
  189. * gpio_status is a bit map where bit 0 is set if unmapped gpio pin 0 (pin3) has
  190. * triggered the ISR. bit 1 if unmapped gpio pin 1 (pin10=U0TXD), etc. Since this
  191. * is the ISR, it makes sense to optimize this by doing a fast scan of the status
  192. * and reverse mapping any set bits.
  193. */
  194. for (j = 0; gpio_status>0; j++, gpio_status >>= 1) {
  195. if (gpio_status&1) {
  196. int i = pin_num_inv[j];
  197. if (pin_int_type[i]) {
  198. //disable interrupt
  199. gpio_pin_intr_state_set(GPIO_ID_PIN(j), GPIO_PIN_INTR_DISABLE);
  200. //clear interrupt status
  201. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(j));
  202. uint32 level = 0x1 & GPIO_INPUT_GET(GPIO_ID_PIN(j));
  203. task_post_high (gpio_task_handle, (i<<1) + level);
  204. // We re-enable the interrupt when we execute the callback
  205. }
  206. }
  207. }
  208. }
  209. void platform_gpio_init( task_handle_t gpio_task )
  210. {
  211. gpio_task_handle = gpio_task;
  212. ETS_GPIO_INTR_ATTACH(platform_gpio_intr_dispatcher, NULL);
  213. }
  214. #ifdef GPIO_INTERRUPT_HOOK_ENABLE
  215. /*
  216. * Register an ISR hook to be called from the GPIO ISR for a given GPIO bitmask.
  217. * This routine is only called a few times so has been optimised for size and
  218. * the unregister is a special case when the bits are 0.
  219. *
  220. * Each hook function can only be registered once. If it is re-registered
  221. * then the hooked bits are just updated to the new value.
  222. */
  223. int platform_gpio_register_intr_hook(uint32_t bits, platform_hook_function hook)
  224. {
  225. struct gpio_hook nh, oh = platform_gpio_hook;
  226. int i, j;
  227. if (!hook) {
  228. // Cannot register or unregister null hook
  229. return 0;
  230. }
  231. int delete_slot = -1;
  232. // If hook already registered, just update the bits
  233. for (i=0; i<oh.count; i++) {
  234. if (hook == oh.entry[i].func) {
  235. if (!bits) {
  236. // Unregister if move to zero bits
  237. delete_slot = i;
  238. break;
  239. }
  240. if (bits & (oh.all_bits & ~oh.entry[i].bits)) {
  241. // Attempt to hook an already hooked bit
  242. return 0;
  243. }
  244. // Update the hooked bits (in the right order)
  245. uint32_t old_bits = oh.entry[i].bits;
  246. *(volatile uint32_t *) &oh.entry[i].bits = bits;
  247. *(volatile uint32_t *) &oh.all_bits = (oh.all_bits & ~old_bits) | bits;
  248. return 1;
  249. }
  250. }
  251. // This must be the register new hook / delete old hook
  252. if (delete_slot < 0) {
  253. if (bits & oh.all_bits) {
  254. return 0; // Attempt to hook already hooked bits
  255. }
  256. nh.count = oh.count + 1; // register a new hook
  257. } else {
  258. nh.count = oh.count - 1; // unregister an old hook
  259. }
  260. // These return NULL if the count = 0 so only error check if > 0)
  261. nh.entry = c_malloc( nh.count * sizeof(*(nh.entry)) );
  262. if (nh.count && !(nh.entry)) {
  263. return 0; // Allocation failure
  264. }
  265. for (i=0, j=0; i<oh.count; i++) {
  266. // Don't copy if this is the entry to delete
  267. if (i != delete_slot) {
  268. nh.entry[j++] = oh.entry[i];
  269. }
  270. }
  271. if (delete_slot < 0) { // for a register add the hook to the tail and set the all bits
  272. nh.entry[j].bits = bits;
  273. nh.entry[j].func = hook;
  274. nh.all_bits = oh.all_bits | bits;
  275. } else { // for an unregister clear the matching all bits
  276. nh.all_bits = oh.all_bits & (~oh.entry[delete_slot].bits);
  277. }
  278. ETS_GPIO_INTR_DISABLE();
  279. // This is a structure copy, so interrupts need to be disabled
  280. platform_gpio_hook = nh;
  281. ETS_GPIO_INTR_ENABLE();
  282. c_free(oh.entry);
  283. return 1;
  284. }
  285. #endif // GPIO_INTERRUPT_HOOK_ENABLE
  286. /*
  287. * Initialise GPIO interrupt mode. Optionally in RAM because interrupts are dsabled
  288. */
  289. void NO_INTR_CODE platform_gpio_intr_init( unsigned pin, GPIO_INT_TYPE type )
  290. {
  291. if (platform_gpio_exists(pin)) {
  292. ETS_GPIO_INTR_DISABLE();
  293. //clear interrupt status
  294. GPIO_REG_WRITE(GPIO_STATUS_W1TC_ADDRESS, BIT(pin_num[pin]));
  295. pin_int_type[pin] = type;
  296. //enable interrupt
  297. gpio_pin_intr_state_set(GPIO_ID_PIN(pin_num[pin]), type);
  298. ETS_GPIO_INTR_ENABLE();
  299. }
  300. }
  301. #endif
  302. // ****************************************************************************
  303. // UART
  304. // TODO: Support timeouts.
  305. // UartDev is defined and initialized in rom code.
  306. extern UartDevice UartDev;
  307. uint32_t platform_uart_setup( unsigned id, uint32_t baud, int databits, int parity, int stopbits )
  308. {
  309. switch( baud )
  310. {
  311. case BIT_RATE_300:
  312. case BIT_RATE_600:
  313. case BIT_RATE_1200:
  314. case BIT_RATE_2400:
  315. case BIT_RATE_4800:
  316. case BIT_RATE_9600:
  317. case BIT_RATE_19200:
  318. case BIT_RATE_38400:
  319. case BIT_RATE_57600:
  320. case BIT_RATE_74880:
  321. case BIT_RATE_115200:
  322. case BIT_RATE_230400:
  323. case BIT_RATE_256000:
  324. case BIT_RATE_460800:
  325. case BIT_RATE_921600:
  326. case BIT_RATE_1843200:
  327. case BIT_RATE_3686400:
  328. UartDev.baut_rate = baud;
  329. break;
  330. default:
  331. UartDev.baut_rate = BIT_RATE_9600;
  332. break;
  333. }
  334. switch( databits )
  335. {
  336. case 5:
  337. UartDev.data_bits = FIVE_BITS;
  338. break;
  339. case 6:
  340. UartDev.data_bits = SIX_BITS;
  341. break;
  342. case 7:
  343. UartDev.data_bits = SEVEN_BITS;
  344. break;
  345. case 8:
  346. UartDev.data_bits = EIGHT_BITS;
  347. break;
  348. default:
  349. UartDev.data_bits = EIGHT_BITS;
  350. break;
  351. }
  352. switch (stopbits)
  353. {
  354. case PLATFORM_UART_STOPBITS_1_5:
  355. UartDev.stop_bits = ONE_HALF_STOP_BIT;
  356. break;
  357. case PLATFORM_UART_STOPBITS_2:
  358. UartDev.stop_bits = TWO_STOP_BIT;
  359. break;
  360. default:
  361. UartDev.stop_bits = ONE_STOP_BIT;
  362. break;
  363. }
  364. switch (parity)
  365. {
  366. case PLATFORM_UART_PARITY_EVEN:
  367. UartDev.parity = EVEN_BITS;
  368. UartDev.exist_parity = STICK_PARITY_EN;
  369. break;
  370. case PLATFORM_UART_PARITY_ODD:
  371. UartDev.parity = ODD_BITS;
  372. UartDev.exist_parity = STICK_PARITY_EN;
  373. break;
  374. default:
  375. UartDev.parity = NONE_BITS;
  376. UartDev.exist_parity = STICK_PARITY_DIS;
  377. break;
  378. }
  379. uart_setup(id);
  380. return baud;
  381. }
  382. void platform_uart_get_config(unsigned id, uint32_t *baudp, uint32_t *databitsp, uint32_t *parityp, uint32_t *stopbitsp) {
  383. UartConfig config = uart_get_config(id);
  384. int i;
  385. int offset = config.baut_rate;
  386. for (i = 0; i < sizeof(uart_bitrates) / sizeof(uart_bitrates[0]); i++) {
  387. int diff = config.baut_rate - uart_bitrates[i];
  388. if (diff < 0) {
  389. diff = -diff;
  390. }
  391. if (diff < offset) {
  392. offset = diff;
  393. *baudp = uart_bitrates[i];
  394. }
  395. }
  396. switch( config.data_bits )
  397. {
  398. case FIVE_BITS:
  399. *databitsp = 5;
  400. break;
  401. case SIX_BITS:
  402. *databitsp = 6;
  403. break;
  404. case SEVEN_BITS:
  405. *databitsp = 7;
  406. break;
  407. case EIGHT_BITS:
  408. default:
  409. *databitsp = 8;
  410. break;
  411. }
  412. switch (config.stop_bits)
  413. {
  414. case ONE_HALF_STOP_BIT:
  415. *stopbitsp = PLATFORM_UART_STOPBITS_1_5;
  416. break;
  417. case TWO_STOP_BIT:
  418. *stopbitsp = PLATFORM_UART_STOPBITS_2;
  419. break;
  420. default:
  421. *stopbitsp = PLATFORM_UART_STOPBITS_1;
  422. break;
  423. }
  424. if (config.exist_parity == STICK_PARITY_DIS) {
  425. *parityp = PLATFORM_UART_PARITY_NONE;
  426. } else if (config.parity == EVEN_BITS) {
  427. *parityp = PLATFORM_UART_PARITY_EVEN;
  428. } else {
  429. *parityp = PLATFORM_UART_PARITY_ODD;
  430. }
  431. }
  432. // if set=1, then alternate serial output pins are used. (15=rx, 13=tx)
  433. void platform_uart_alt( int set )
  434. {
  435. uart0_alt( set );
  436. return;
  437. }
  438. // Send: version with and without mux
  439. void platform_uart_send( unsigned id, u8 data )
  440. {
  441. uart_tx_one_char(id, data);
  442. }
  443. // ****************************************************************************
  444. // PWMs
  445. static uint16_t pwms_duty[NUM_PWM] = {0};
  446. void platform_pwm_init()
  447. {
  448. int i;
  449. for(i=0;i<NUM_PWM;i++){
  450. pwms_duty[i] = DUTY(0);
  451. }
  452. pwm_init(500, NULL);
  453. // NODE_DBG("Function pwms_init() is called.\n");
  454. }
  455. // Return the PWM clock
  456. // NOTE: Can't find a function to query for the period set for the timer,
  457. // therefore using the struct.
  458. // This may require adjustment if driver libraries are updated.
  459. uint32_t platform_pwm_get_clock( unsigned pin )
  460. {
  461. // NODE_DBG("Function platform_pwm_get_clock() is called.\n");
  462. if( pin >= NUM_PWM)
  463. return 0;
  464. if(!pwm_exist(pin))
  465. return 0;
  466. return (uint32_t)pwm_get_freq(pin);
  467. }
  468. // Set the PWM clock
  469. uint32_t platform_pwm_set_clock( unsigned pin, uint32_t clock )
  470. {
  471. // NODE_DBG("Function platform_pwm_set_clock() is called.\n");
  472. if( pin >= NUM_PWM)
  473. return 0;
  474. if(!pwm_exist(pin))
  475. return 0;
  476. pwm_set_freq((uint16_t)clock, pin);
  477. pwm_start();
  478. return (uint32_t)pwm_get_freq( pin );
  479. }
  480. uint32_t platform_pwm_get_duty( unsigned pin )
  481. {
  482. // NODE_DBG("Function platform_pwm_get_duty() is called.\n");
  483. if( pin < NUM_PWM){
  484. if(!pwm_exist(pin))
  485. return 0;
  486. // return NORMAL_DUTY(pwm_get_duty(pin));
  487. return pwms_duty[pin];
  488. }
  489. return 0;
  490. }
  491. // Set the PWM duty
  492. uint32_t platform_pwm_set_duty( unsigned pin, uint32_t duty )
  493. {
  494. // NODE_DBG("Function platform_pwm_set_duty() is called.\n");
  495. if ( pin < NUM_PWM)
  496. {
  497. if(!pwm_exist(pin))
  498. return 0;
  499. pwm_set_duty(DUTY(duty), pin);
  500. } else {
  501. return 0;
  502. }
  503. pwm_start();
  504. pwms_duty[pin] = NORMAL_DUTY(pwm_get_duty(pin));
  505. return pwms_duty[pin];
  506. }
  507. uint32_t platform_pwm_setup( unsigned pin, uint32_t frequency, unsigned duty )
  508. {
  509. uint32_t clock;
  510. if ( pin < NUM_PWM)
  511. {
  512. platform_gpio_mode(pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT); // disable gpio interrupt first
  513. if(!pwm_add(pin))
  514. return 0;
  515. // pwm_set_duty(DUTY(duty), pin);
  516. pwm_set_duty(0, pin);
  517. pwms_duty[pin] = duty;
  518. pwm_set_freq((uint16_t)frequency, pin);
  519. } else {
  520. return 0;
  521. }
  522. clock = platform_pwm_get_clock( pin );
  523. if (!pwm_start()) {
  524. return 0;
  525. }
  526. return clock;
  527. }
  528. void platform_pwm_close( unsigned pin )
  529. {
  530. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  531. if ( pin < NUM_PWM)
  532. {
  533. pwm_delete(pin);
  534. pwm_start();
  535. }
  536. }
  537. bool platform_pwm_start( unsigned pin )
  538. {
  539. // NODE_DBG("Function platform_pwm_start() is called.\n");
  540. if ( pin < NUM_PWM)
  541. {
  542. if(!pwm_exist(pin))
  543. return FALSE;
  544. pwm_set_duty(DUTY(pwms_duty[pin]), pin);
  545. return pwm_start();
  546. }
  547. return FALSE;
  548. }
  549. void platform_pwm_stop( unsigned pin )
  550. {
  551. // NODE_DBG("Function platform_pwm_stop() is called.\n");
  552. if ( pin < NUM_PWM)
  553. {
  554. if(!pwm_exist(pin))
  555. return;
  556. pwm_set_duty(0, pin);
  557. pwm_start();
  558. }
  559. }
  560. // *****************************************************************************
  561. // Sigma-Delta platform interface
  562. uint8_t platform_sigma_delta_setup( uint8_t pin )
  563. {
  564. if (pin < 1 || pin > NUM_GPIO)
  565. return 0;
  566. sigma_delta_setup();
  567. // set GPIO output mode for this pin
  568. platform_gpio_mode( pin, PLATFORM_GPIO_OUTPUT, PLATFORM_GPIO_FLOAT );
  569. platform_gpio_write( pin, PLATFORM_GPIO_LOW );
  570. // enable sigma-delta on this pin
  571. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  572. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  573. GPIO_PIN_SOURCE_SET( SIGMA_AS_PIN_SOURCE ));
  574. return 1;
  575. }
  576. uint8_t platform_sigma_delta_close( uint8_t pin )
  577. {
  578. if (pin < 1 || pin > NUM_GPIO)
  579. return 0;
  580. sigma_delta_stop();
  581. // set GPIO input mode for this pin
  582. platform_gpio_mode( pin, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP );
  583. // CONNECT GPIO TO PIN PAD
  584. GPIO_REG_WRITE(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin])),
  585. (GPIO_REG_READ(GPIO_PIN_ADDR(GPIO_ID_PIN(pin_num[pin]))) &(~GPIO_PIN_SOURCE_MASK)) |
  586. GPIO_PIN_SOURCE_SET( GPIO_AS_PIN_SOURCE ));
  587. return 1;
  588. }
  589. void platform_sigma_delta_set_pwmduty( uint8_t duty )
  590. {
  591. uint8_t target = 0, prescale = 0;
  592. target = duty > 128 ? 256 - duty : duty;
  593. prescale = target == 0 ? 0 : target-1;
  594. //freq = 80000 (khz) /256 /duty_target * (prescale+1)
  595. sigma_delta_set_prescale_target( prescale, duty );
  596. }
  597. void platform_sigma_delta_set_prescale( uint8_t prescale )
  598. {
  599. sigma_delta_set_prescale_target( prescale, -1 );
  600. }
  601. void ICACHE_RAM_ATTR platform_sigma_delta_set_target( uint8_t target )
  602. {
  603. sigma_delta_set_prescale_target( -1, target );
  604. }
  605. // *****************************************************************************
  606. // I2C platform interface
  607. uint32_t platform_i2c_setup( unsigned id, uint8_t sda, uint8_t scl, uint32_t speed ){
  608. if (sda >= NUM_GPIO || scl >= NUM_GPIO)
  609. return 0;
  610. // platform_pwm_close(sda);
  611. // platform_pwm_close(scl);
  612. // disable gpio interrupt first
  613. platform_gpio_mode(sda, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // inside this func call platform_pwm_close
  614. platform_gpio_mode(scl, PLATFORM_GPIO_INPUT, PLATFORM_GPIO_PULLUP); // disable gpio interrupt first
  615. i2c_master_gpio_init(sda, scl);
  616. return PLATFORM_I2C_SPEED_SLOW;
  617. }
  618. void platform_i2c_send_start( unsigned id ){
  619. i2c_master_start();
  620. }
  621. void platform_i2c_send_stop( unsigned id ){
  622. i2c_master_stop();
  623. }
  624. int platform_i2c_send_address( unsigned id, uint16_t address, int direction ){
  625. // Convert enum codes to R/w bit value.
  626. // If TX == 0 and RX == 1, this test will be removed by the compiler
  627. if ( ! ( PLATFORM_I2C_DIRECTION_TRANSMITTER == 0 &&
  628. PLATFORM_I2C_DIRECTION_RECEIVER == 1 ) ) {
  629. direction = ( direction == PLATFORM_I2C_DIRECTION_TRANSMITTER ) ? 0 : 1;
  630. }
  631. i2c_master_writeByte( (uint8_t) ((address << 1) | direction ));
  632. // Low-level returns nack (0=acked); we return ack (1=acked).
  633. return ! i2c_master_getAck();
  634. }
  635. int platform_i2c_send_byte( unsigned id, uint8_t data ){
  636. i2c_master_writeByte(data);
  637. // Low-level returns nack (0=acked); we return ack (1=acked).
  638. return ! i2c_master_getAck();
  639. }
  640. int platform_i2c_recv_byte( unsigned id, int ack ){
  641. uint8_t r = i2c_master_readByte();
  642. i2c_master_setAck( !ack );
  643. return r;
  644. }
  645. // *****************************************************************************
  646. // SPI platform interface
  647. uint32_t platform_spi_setup( uint8_t id, int mode, unsigned cpol, unsigned cpha, uint32_t clock_div )
  648. {
  649. spi_master_init( id, cpol, cpha, clock_div );
  650. return 1;
  651. }
  652. int platform_spi_send( uint8_t id, uint8_t bitlen, spi_data_type data )
  653. {
  654. if (bitlen > 32)
  655. return PLATFORM_ERR;
  656. spi_mast_transaction( id, 0, 0, bitlen, data, 0, 0, 0 );
  657. return PLATFORM_OK;
  658. }
  659. spi_data_type platform_spi_send_recv( uint8_t id, uint8_t bitlen, spi_data_type data )
  660. {
  661. if (bitlen > 32)
  662. return 0;
  663. spi_mast_set_mosi( id, 0, bitlen, data );
  664. spi_mast_transaction( id, 0, 0, 0, 0, bitlen, 0, -1 );
  665. return spi_mast_get_miso( id, 0, bitlen );
  666. }
  667. int platform_spi_blkwrite( uint8_t id, size_t len, const uint8_t *data )
  668. {
  669. spi_mast_byte_order( id, SPI_ORDER_LSB );
  670. while (len > 0) {
  671. size_t chunk_len = len > 64 ? 64 : len;
  672. spi_mast_blkset( id, chunk_len * 8, data );
  673. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, 0 );
  674. data = &(data[chunk_len]);
  675. len -= chunk_len;
  676. }
  677. spi_mast_byte_order( id, SPI_ORDER_MSB );
  678. return PLATFORM_OK;
  679. }
  680. int platform_spi_blkread( uint8_t id, size_t len, uint8_t *data )
  681. {
  682. uint8_t mosi_idle[64];
  683. os_memset( (void *)mosi_idle, 0xff, len > 64 ? 64 : len );
  684. spi_mast_byte_order( id, SPI_ORDER_LSB );
  685. while (len > 0 ) {
  686. size_t chunk_len = len > 64 ? 64 : len;
  687. spi_mast_blkset( id, chunk_len * 8, mosi_idle );
  688. spi_mast_transaction( id, 0, 0, 0, 0, chunk_len * 8, 0, -1 );
  689. spi_mast_blkget( id, chunk_len * 8, data );
  690. data = &(data[chunk_len]);
  691. len -= chunk_len;
  692. }
  693. spi_mast_byte_order( id, SPI_ORDER_MSB );
  694. return PLATFORM_OK;
  695. }
  696. int platform_spi_set_mosi( uint8_t id, uint16_t offset, uint8_t bitlen, spi_data_type data )
  697. {
  698. if (offset + bitlen > 512)
  699. return PLATFORM_ERR;
  700. spi_mast_set_mosi( id, offset, bitlen, data );
  701. return PLATFORM_OK;
  702. }
  703. spi_data_type platform_spi_get_miso( uint8_t id, uint16_t offset, uint8_t bitlen )
  704. {
  705. if (offset + bitlen > 512)
  706. return 0;
  707. return spi_mast_get_miso( id, offset, bitlen );
  708. }
  709. int platform_spi_transaction( uint8_t id, uint8_t cmd_bitlen, spi_data_type cmd_data,
  710. uint8_t addr_bitlen, spi_data_type addr_data,
  711. uint16_t mosi_bitlen, uint8_t dummy_bitlen, int16_t miso_bitlen )
  712. {
  713. if ((cmd_bitlen > 16) ||
  714. (addr_bitlen > 32) ||
  715. (mosi_bitlen > 512) ||
  716. (dummy_bitlen > 256) ||
  717. (miso_bitlen > 512))
  718. return PLATFORM_ERR;
  719. spi_mast_transaction( id, cmd_bitlen, cmd_data, addr_bitlen, addr_data, mosi_bitlen, dummy_bitlen, miso_bitlen );
  720. return PLATFORM_OK;
  721. }
  722. // ****************************************************************************
  723. // Flash access functions
  724. /*
  725. * Assumptions:
  726. * > toaddr is INTERNAL_FLASH_WRITE_UNIT_SIZE aligned
  727. * > size is a multiple of INTERNAL_FLASH_WRITE_UNIT_SIZE
  728. */
  729. uint32_t platform_s_flash_write( const void *from, uint32_t toaddr, uint32_t size )
  730. {
  731. SpiFlashOpResult r;
  732. const uint32_t blkmask = INTERNAL_FLASH_WRITE_UNIT_SIZE - 1;
  733. uint32_t *apbuf = NULL;
  734. uint32_t fromaddr = (uint32_t)from;
  735. if( (fromaddr & blkmask ) || (fromaddr >= INTERNAL_FLASH_MAPPED_ADDRESS)) {
  736. apbuf = (uint32_t *)c_malloc(size);
  737. if(!apbuf)
  738. return 0;
  739. c_memcpy(apbuf, from, size);
  740. }
  741. system_soft_wdt_feed ();
  742. r = flash_write(toaddr, apbuf?(uint32 *)apbuf:(uint32 *)from, size);
  743. if(apbuf)
  744. c_free(apbuf);
  745. if(SPI_FLASH_RESULT_OK == r)
  746. return size;
  747. else{
  748. NODE_ERR( "ERROR in flash_write: r=%d at %08X\n", ( int )r, ( unsigned )toaddr);
  749. return 0;
  750. }
  751. }
  752. /*
  753. * Assumptions:
  754. * > fromaddr is INTERNAL_FLASH_READ_UNIT_SIZE aligned
  755. * > size is a multiple of INTERNAL_FLASH_READ_UNIT_SIZE
  756. */
  757. uint32_t platform_s_flash_read( void *to, uint32_t fromaddr, uint32_t size )
  758. {
  759. if (size==0)
  760. return 0;
  761. SpiFlashOpResult r;
  762. system_soft_wdt_feed ();
  763. const uint32_t blkmask = (INTERNAL_FLASH_READ_UNIT_SIZE - 1);
  764. if( ((uint32_t)to) & blkmask )
  765. {
  766. uint32_t size2=size-INTERNAL_FLASH_READ_UNIT_SIZE;
  767. uint32* to2=(uint32*)((((uint32_t)to)&(~blkmask))+INTERNAL_FLASH_READ_UNIT_SIZE);
  768. r = flash_read(fromaddr, to2, size2);
  769. if(SPI_FLASH_RESULT_OK == r)
  770. {
  771. os_memmove(to,to2,size2);
  772. char back[ INTERNAL_FLASH_READ_UNIT_SIZE ] __attribute__ ((aligned(INTERNAL_FLASH_READ_UNIT_SIZE)));
  773. r=flash_read(fromaddr+size2,(uint32*)back,INTERNAL_FLASH_READ_UNIT_SIZE);
  774. os_memcpy((uint8_t*)to+size2,back,INTERNAL_FLASH_READ_UNIT_SIZE);
  775. }
  776. }
  777. else
  778. r = flash_read(fromaddr, (uint32 *)to, size);
  779. if(SPI_FLASH_RESULT_OK == r)
  780. return size;
  781. else{
  782. NODE_ERR( "ERROR in flash_read: r=%d at %08X\n", ( int )r, ( unsigned )fromaddr);
  783. return 0;
  784. }
  785. }
  786. int platform_flash_erase_sector( uint32_t sector_id )
  787. {
  788. system_soft_wdt_feed ();
  789. return flash_erase( sector_id ) == SPI_FLASH_RESULT_OK ? PLATFORM_OK : PLATFORM_ERR;
  790. }
  791. uint32_t platform_flash_mapped2phys (uint32_t mapped_addr)
  792. {
  793. uint32_t cache_ctrl = READ_PERI_REG(CACHE_FLASH_CTRL_REG);
  794. if (!(cache_ctrl & CACHE_FLASH_ACTIVE))
  795. return -1;
  796. bool b0 = (cache_ctrl & CACHE_FLASH_MAPPED0) ? 1 : 0;
  797. bool b1 = (cache_ctrl & CACHE_FLASH_MAPPED1) ? 1 : 0;
  798. uint32_t meg = (b1 << 1) | b0;
  799. return mapped_addr - INTERNAL_FLASH_MAPPED_ADDRESS + meg * 0x100000;
  800. }