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@@ -31,82 +31,71 @@
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* @author Johny Mattsson <jmattsson@dius.com.au>
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*/
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-#include "user_exceptions.h"
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-
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-#define LOAD_MASK 0x00f00fu
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-#define L8UI_MATCH 0x000002u
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-#define L16UI_MATCH 0x001002u
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-#define L16SI_MATCH 0x009002u
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-
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-
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-void load_non_32_wide_handler (struct exception_frame *ef, uint32_t cause)
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-{
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- /* If this is not EXCCAUSE_LOAD_STORE_ERROR you're doing it wrong! */
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- (void)cause;
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-
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- uint32_t epc1 = ef->epc;
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- uint32_t excvaddr;
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- uint32_t insn;
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- asm (
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- "rsr %0, EXCVADDR;" /* read out the faulting address */
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- "movi a4, ~3;" /* prepare a mask for the EPC */
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- "and a4, a4, %2;" /* apply mask for 32bit aligned base */
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- "l32i a5, a4, 0;" /* load part 1 */
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- "l32i a6, a4, 4;" /* load part 2 */
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- "ssa8l %2;" /* set up shift register for src op */
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- "src %1, a6, a5;" /* right shift to get faulting instruction */
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- :"=r"(excvaddr), "=r"(insn)
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- :"r"(epc1)
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- :"a4", "a5", "a6"
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- );
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-
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- uint32_t valmask = 0;
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- uint32_t what = insn & LOAD_MASK;
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-
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- if (what == L8UI_MATCH)
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- valmask = 0xffu;
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- else if (what == L16UI_MATCH || what == L16SI_MATCH)
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- valmask = 0xffffu;
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- else
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- {
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-die:
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- /* Turns out we couldn't fix this, trigger a system break instead
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- * and hang if the break doesn't get handled. This is effectively
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- * what would happen if the default handler was installed. */
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- asm ("break 1, 1");
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- while (1) {}
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- }
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-
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- /* Load, shift and mask down to correct size */
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- uint32_t val = (*(uint32_t *)(excvaddr & ~0x3));
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- val >>= (excvaddr & 0x3) * 8;
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- val &= valmask;
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+/* Minimal handler function for 8/16bit loads from the mapped SPI flash.
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+ * Called from the overridden UserExceptionVector on exception cause 3.
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+ */
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+asm(
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+".section \".iram0.text\"\n"
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+" .align 4\n"
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+"store_mask:\n"
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+" .word 0x004000\n" /* bit 14 is set on store instructions (see note ^) */
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+"align_mask:\n"
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+" .word ~3\n" /* mask to get 32bit alignment of addresses */
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+".type cause3_handler,@function\n"
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+"cause3_handler:\n"
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+" wsr a2, EXCSAVE2\n" /* free up a2 for use too */
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+" rsr a2, EPC1\n" /* get the program counter that caused the exception */
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+" ssa8l a2\n" /* prepare to extract the (unaligned) instruction */
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+" l32r a0, align_mask\n"/* prepare mask for 32bit alignment */
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+" and a2, a2, a0\n" /* get aligned base address of instruction */
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+" l32i a0, a2, 0\n" /* load first part */
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+" l32i a2, a2, 4\n" /* load second part */
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+" src a0, a2, a0\n" /* faulting instruction now in a0 */
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+" l32r a2, store_mask\n"
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+" and a0, a0, a2\n" /* test for store bit */
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+" bnez a0, 1f\n" /* it's a store, we don't do stores, get out */
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- /* Sign-extend for L16SI, if applicable */
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- if (what == L16SI_MATCH && (val & 0x8000))
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- val |= 0xffff0000;
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+"" /* As it turns out, the ESP8266 happily does 8/16bit */
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+ /* loads from the mapped SPI flash, but then raises an */
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+ /* exception anyway; we can simply increment the */
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+ /* program counter and be our merry way, safe in */
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+ /* the knowledge that the loads have already been done.*/
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+ /* Note that this only applies to the SPI flash, not */
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+ /* internal ROM or IRAM - if we ever want to support */
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+ /* those we'll need to add the appropriate loading */
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+ /* logic here. For now I see no need for such support. */
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- int regno = (insn & 0x0000f0u) >> 4;
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- if (regno == 1)
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- goto die; /* we can't support loading into a1, just die */
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- else if (regno != 0)
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- --regno; /* account for skipped a1 in exception_frame */
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+" rsr a2, EPC1\n" /* read the program counter again */
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+" addi a2, a2, 3\n" /* advance program counter past faulting instruction */
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+" wsr a2, EPC1\n" /* and store it back */
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+" rsr a2, EXCSAVE2\n" /* restore a2 */
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+" rsr a0, EXCSAVE1\n" /* restore a0 */
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+" rfe\n" /* and done! */
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+"1:rsr a2, EXCSAVE2\n" /* we're about to chain, so restore the a2 we clobbered*/
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+" ret\n" /* and hop back into the exception vector code */
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+);
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+/* Note ^) Except for the S32E instruction, but that's not applicable here,
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+ * so we can happily ignore it.
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+ */
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- ef->a_reg[regno] = val; /* carry out the load */
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- ef->epc += 3; /* resume at following instruction */
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-}
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-/**
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- * The SDK's user_main function installs a debugging handler regardless
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- * of whether there's a proper handler installed for EXCCAUSE_LOAD_STORE_ERROR,
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- * which of course breaks everything if we allow that to go through. As such,
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- * we use the linker to wrap that call and stop the SDK from shooting itself in
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- * its proverbial foot.
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+/* Our sneaky override of the UserExceptionVector to allow us to handle 8/16bit
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+ * loads from SPI flash. MUST BE >= 32bytes compiled, as the next vector starts
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+ * there.
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*/
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-exception_handler_fn TEXT_SECTION_ATTR
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-__wrap__xtos_set_exception_handler (uint32_t cause, exception_handler_fn fn)
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-{
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- if (cause != EXCCAUSE_LOAD_STORE_ERROR)
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- __real__xtos_set_exception_handler (cause, fn);
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-}
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+asm(
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+".section \".UserExceptionVectorOverride.text\"\n"
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+".type _UserExceptionVectorOverride,@function\n"
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+".globl _UserExceptionVectorOverride\n"
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+"_UserExceptionVectorOverride:\n"
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+" wsr a0, EXCSAVE1\n" /* free up a0 for a while */
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+" rsr a0, EXCCAUSE\n" /* get the exception cause */
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+" bnei a0, 3, 2f\n" /* if not EXCCAUSE_LOAD_STORE_ERROR, chain to rtos */
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+" j 1f\n" /* jump past noncode bytes for cause3_handler addr */
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+" .align 4\n" /* proper alignment for literals */
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+" .literal_position\n" /* the linker will put cause3_handler addr here */
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+"1:call0 cause3_handler\n" /* handle loads and rfe, stores will return here */
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+"2:rsr a0, EXCSAVE1\n" /* restore a0 before we chain */
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+" j _UserExceptionVector\n" /* and off we go to rtos */
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+);
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