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@@ -19,13 +19,13 @@ void spi_lcd_mode_init(uint8 spi_no)
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if(spi_no>1) return; //handle invalid input number
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//bit9 of PERIPHS_IO_MUX should be cleared when HSPI clock doesn't equal CPU clock
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//bit8 of PERIPHS_IO_MUX should be cleared when SPI clock doesn't equal CPU clock
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- if(spi_no==SPI){
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+ if(spi_no==SPI_SPI){
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WRITE_PERI_REG(PERIPHS_IO_MUX, 0x005); //clear bit9,and bit8
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);//configure io to spi mode
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- }else if(spi_no==HSPI){
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+ }else if(spi_no==SPI_HSPI){
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WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);//configure io to spi mode
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@@ -93,10 +93,10 @@ uint32_t spi_set_clkdiv(uint8 spi_no, uint32_t clock_div)
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WRITE_PERI_REG(SPI_CLOCK(spi_no), SPI_CLK_EQU_SYSCLK); // 80Mhz speed
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}
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- if(spi_no==SPI){
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+ if(spi_no==SPI_SPI){
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WRITE_PERI_REG(PERIPHS_IO_MUX, 0x005 | (clock_div <= 1 ? 0x100 : 0));
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}
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- else if(spi_no==HSPI){
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+ else if(spi_no==SPI_HSPI){
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WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105 | (clock_div <= 1 ? 0x200 : 0));
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}
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@@ -144,13 +144,13 @@ void spi_master_init(uint8 spi_no, unsigned cpol, unsigned cpha, uint32_t clock_
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spi_set_clkdiv(spi_no, clock_div);
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- if(spi_no==SPI){
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+ if(spi_no==SPI_SPI){
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);//configure io to spi mode
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}
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- else if(spi_no==HSPI){
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+ else if(spi_no==SPI_HSPI){
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2);//configure io to spi mode
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@@ -179,8 +179,16 @@ void spi_mast_byte_order(uint8 spi_no, uint8 order)
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*******************************************************************************/
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void spi_mast_blkset(uint8 spi_no, size_t bitlen, const uint8 *data)
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{
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+ size_t aligned_len = bitlen >> 3;
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+
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while(READ_PERI_REG(SPI_CMD(spi_no)) & SPI_USR);
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- os_memcpy((void *)SPI_W0(spi_no), (const void *)data, bitlen >> 3);
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+
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+ if (aligned_len % 4) {
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+ // length for memcpy needs to be aligned to uint32 bounday
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+ // otherwise single byte writes are issued to the register and corrupt data
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+ aligned_len += 4 - (aligned_len % 4);
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+ }
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+ os_memcpy((void *)SPI_W0(spi_no), (const void *)data, aligned_len);
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}
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/******************************************************************************
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@@ -188,12 +196,29 @@ void spi_mast_blkset(uint8 spi_no, size_t bitlen, const uint8 *data)
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* Description : Copy a block of data from the MISO FIFO
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* Parameters : uint8 spi_no - SPI module number, Only "SPI" and "HSPI" are valid
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* size_t bitlen - number of bits to copy, multiple of 8
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- * uint8 *data - pointer to data buffer
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+ * uint8 *data - pointer to data buffer, the buffer must be able to
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+ * accept a multiple of 4*8 bits
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*******************************************************************************/
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void spi_mast_blkget(uint8 spi_no, size_t bitlen, uint8 *data)
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{
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+ size_t aligned_len = bitlen >> 3;
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+
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while(READ_PERI_REG(SPI_CMD(spi_no)) & SPI_USR);
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- os_memcpy((void *)data, (void *)SPI_W0(spi_no), bitlen >> 3);
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+
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+ if (aligned_len % 4) {
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+ // length for memcpy needs to be aligned to uint32 bounday
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+ // otherwise single byte reads are issued to the register and corrupt data
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+ aligned_len += 4 - (aligned_len % 4);
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+ }
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+ os_memcpy((void *)data, (void *)SPI_W0(spi_no), aligned_len);
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+}
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+
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+static uint32 swap_endianess(uint32 n)
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+{
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+ return ((n & 0xff) << 24) |
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+ ((n & 0xff00) << 8) |
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+ ((n & 0xff0000UL) >> 8) |
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+ ((n & 0xff000000UL) >> 24);
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}
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/******************************************************************************
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@@ -208,8 +233,8 @@ void spi_mast_blkget(uint8 spi_no, size_t bitlen, uint8 *data)
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*******************************************************************************/
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void spi_mast_set_mosi(uint8 spi_no, uint16 offset, uint8 bitlen, uint32 data)
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{
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- uint8 wn, shift;
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spi_buf_t spi_buf;
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+ uint8 wn, shift;
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if (spi_no > 1)
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return; // handle invalid input number
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@@ -226,8 +251,10 @@ void spi_mast_set_mosi(uint8 spi_no, uint16 offset, uint8 bitlen, uint32 data)
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// transfer Wn to buf
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spi_buf.word[1] = READ_PERI_REG(SPI_W0(spi_no) + wn*4);
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+ spi_buf.word[1] = swap_endianess(spi_buf.word[1]);
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if (wn < 15) {
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spi_buf.word[0] = READ_PERI_REG(SPI_W0(spi_no) + (wn+1)*4);
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+ spi_buf.word[0] = swap_endianess(spi_buf.word[0]);
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}
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shift = 64 - (offset & 0x1f) - bitlen;
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@@ -235,9 +262,9 @@ void spi_mast_set_mosi(uint8 spi_no, uint16 offset, uint8 bitlen, uint32 data)
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spi_buf.dword |= (uint64)data << shift;
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if (wn < 15) {
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- WRITE_PERI_REG(SPI_W0(spi_no) + (wn+1)*4, spi_buf.word[0]);
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+ WRITE_PERI_REG(SPI_W0(spi_no) + (wn+1)*4, swap_endianess(spi_buf.word[0]));
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}
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- WRITE_PERI_REG(SPI_W0(spi_no) + wn*4, spi_buf.word[1]);
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+ WRITE_PERI_REG(SPI_W0(spi_no) + wn*4, swap_endianess(spi_buf.word[1]));
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return;
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}
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@@ -269,8 +296,10 @@ uint32 spi_mast_get_miso(uint8 spi_no, uint16 offset, uint8 bitlen)
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// transfer Wn to buf
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spi_buf.word[1] = READ_PERI_REG(SPI_W0(spi_no) + wn*4);
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+ spi_buf.word[1] = swap_endianess(spi_buf.word[1]);
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if (wn < 15) {
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spi_buf.word[0] = READ_PERI_REG(SPI_W0(spi_no) + (wn+1)*4);
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+ spi_buf.word[0] = swap_endianess(spi_buf.word[0]);
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}
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result = (uint32)(spi_buf.dword >> (64 - ((offset & 0x1f) + bitlen)));
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@@ -419,12 +448,12 @@ void spi_slave_init(uint8 spi_no)
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//bit9 should be cleared when HSPI clock doesn't equal CPU clock
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//bit8 should be cleared when SPI clock doesn't equal CPU clock
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////WRITE_PERI_REG(PERIPHS_IO_MUX, 0x105); //clear bit9//TEST
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- if(spi_no==SPI){
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+ if(spi_no==SPI_SPI){
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, 1);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, 1);//configure io to spi mode
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- }else if(spi_no==HSPI){
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+ }else if(spi_no==SPI_HSPI){
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTDI_U, 2);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTCK_U, 2);//configure io to spi mode
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PIN_FUNC_SELECT(PERIPHS_IO_MUX_MTMS_U, 2);//configure io to spi mode
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@@ -511,10 +540,10 @@ void hspi_master_readwrite_repeat(void)
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uint8 temp;
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os_timer_disarm(&timer2);
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- spi_byte_read_espslave(HSPI,&temp);
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+ spi_byte_read_espslave(SPI_HSPI,&temp);
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temp++;
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- spi_byte_write_espslave(HSPI,temp);
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+ spi_byte_write_espslave(SPI_HSPI,temp);
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os_timer_setfn(&timer2, (os_timer_func_t *)hspi_master_readwrite_repeat, NULL);
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os_timer_arm(&timer2, 500, 0);
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}
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@@ -570,23 +599,23 @@ void spi_slave_isr_handler(void *para)
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if(READ_PERI_REG(0x3ff00020)&BIT4){
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//following 3 lines is to clear isr signal
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- CLEAR_PERI_REG_MASK(SPI_SLAVE(SPI), 0x3ff);
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+ CLEAR_PERI_REG_MASK(SPI_SLAVE(SPI_SPI), 0x3ff);
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}else if(READ_PERI_REG(0x3ff00020)&BIT7){ //bit7 is for hspi isr,
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- regvalue=READ_PERI_REG(SPI_SLAVE(HSPI));
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- CLEAR_PERI_REG_MASK(SPI_SLAVE(HSPI),
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+ regvalue=READ_PERI_REG(SPI_SLAVE(SPI_HSPI));
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+ CLEAR_PERI_REG_MASK(SPI_SLAVE(SPI_HSPI),
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SPI_TRANS_DONE_EN|
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SPI_SLV_WR_STA_DONE_EN|
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SPI_SLV_RD_STA_DONE_EN|
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SPI_SLV_WR_BUF_DONE_EN|
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SPI_SLV_RD_BUF_DONE_EN);
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- SET_PERI_REG_MASK(SPI_SLAVE(HSPI), SPI_SYNC_RESET);
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- CLEAR_PERI_REG_MASK(SPI_SLAVE(HSPI),
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+ SET_PERI_REG_MASK(SPI_SLAVE(SPI_HSPI), SPI_SYNC_RESET);
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+ CLEAR_PERI_REG_MASK(SPI_SLAVE(SPI_HSPI),
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SPI_TRANS_DONE|
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SPI_SLV_WR_STA_DONE|
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SPI_SLV_RD_STA_DONE|
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SPI_SLV_WR_BUF_DONE|
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SPI_SLV_RD_BUF_DONE);
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- SET_PERI_REG_MASK(SPI_SLAVE(HSPI),
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+ SET_PERI_REG_MASK(SPI_SLAVE(SPI_HSPI),
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SPI_TRANS_DONE_EN|
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SPI_SLV_WR_STA_DONE_EN|
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SPI_SLV_RD_STA_DONE_EN|
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@@ -597,7 +626,7 @@ void spi_slave_isr_handler(void *para)
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GPIO_OUTPUT_SET(0, 0);
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idx=0;
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while(idx<8){
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- recv_data=READ_PERI_REG(SPI_W0(HSPI)+(idx<<2));
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+ recv_data=READ_PERI_REG(SPI_W0(SPI_HSPI)+(idx<<2));
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spi_data[idx<<2] = recv_data&0xff;
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spi_data[(idx<<2)+1] = (recv_data>>8)&0xff;
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spi_data[(idx<<2)+2] = (recv_data>>16)&0xff;
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@@ -627,15 +656,15 @@ void ICACHE_FLASH_ATTR
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set_miso_data()
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{
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if(GPIO_INPUT_GET(2)==0){
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- WRITE_PERI_REG(SPI_W8(HSPI),0x05040302);
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- WRITE_PERI_REG(SPI_W9(HSPI),0x09080706);
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- WRITE_PERI_REG(SPI_W10(HSPI),0x0d0c0b0a);
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- WRITE_PERI_REG(SPI_W11(HSPI),0x11100f0e);
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-
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- WRITE_PERI_REG(SPI_W12(HSPI),0x15141312);
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- WRITE_PERI_REG(SPI_W13(HSPI),0x19181716);
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- WRITE_PERI_REG(SPI_W14(HSPI),0x1d1c1b1a);
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- WRITE_PERI_REG(SPI_W15(HSPI),0x21201f1e);
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+ WRITE_PERI_REG(SPI_W8(SPI_HSPI),0x05040302);
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+ WRITE_PERI_REG(SPI_W9(SPI_HSPI),0x09080706);
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+ WRITE_PERI_REG(SPI_W10(SPI_HSPI),0x0d0c0b0a);
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+ WRITE_PERI_REG(SPI_W11(SPI_HSPI),0x11100f0e);
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+
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+ WRITE_PERI_REG(SPI_W12(SPI_HSPI),0x15141312);
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+ WRITE_PERI_REG(SPI_W13(SPI_HSPI),0x19181716);
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+ WRITE_PERI_REG(SPI_W14(SPI_HSPI),0x1d1c1b1a);
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+ WRITE_PERI_REG(SPI_W15(SPI_HSPI),0x21201f1e);
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GPIO_OUTPUT_SET(2, 1);
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}
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}
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@@ -697,7 +726,7 @@ void ICACHE_FLASH_ATTR
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spi_test_init()
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{
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os_printf("spi init\n\r");
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- spi_slave_init(HSPI);
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+ spi_slave_init(SPI_HSPI);
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os_printf("gpio init\n\r");
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gpio_init();
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os_printf("spi task init \n\r");
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