mach3.c 9.6 KB

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  1. /*
  2. * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
  3. * See the copyright notice in the ACK home directory, in the file "Copyright".
  4. */
  5. #define RCSID3 "$Id$"
  6. /*
  7. ** Zilog z8000 keywords
  8. */
  9. 0, R8, 8, "RL0",
  10. 0, R8, 0, "RH0",
  11. 0, R8, 9, "RL1",
  12. 0, R8, 1, "RH1",
  13. 0, R8, 10, "RL2",
  14. 0, R8, 2, "RH2",
  15. 0, R8, 11, "RL3",
  16. 0, R8, 3, "RH3",
  17. 0, R8, 12, "RL4",
  18. 0, R8, 4, "RH4",
  19. 0, R8, 13, "RL5",
  20. 0, R8, 5, "RH5",
  21. 0, R8, 14, "RL6",
  22. 0, R8, 6, "RH6",
  23. 0, R8, 15, "RL7",
  24. 0, R8, 7, "RH7",
  25. /* Special format for some byte-registers. Not really available on
  26. ** the z8000 but designed to ease writing a z8000-backend-table.
  27. ** LR[0..7] are equivalent with RL[0..7].
  28. */
  29. 0, R8, 8, "LR0",
  30. 0, R8, 9, "LR1",
  31. 0, R8, 10, "LR2",
  32. 0, R8, 11, "LR3",
  33. 0, R8, 12, "LR4",
  34. 0, R8, 13, "LR5",
  35. 0, R8, 14, "LR6",
  36. 0, R8, 15, "LR7",
  37. 0, R16, 0, "R0",
  38. 0, R16, 1, "R1",
  39. 0, R16, 2, "R2",
  40. 0, R16, 3, "R3",
  41. 0, R16, 4, "R4",
  42. 0, R16, 5, "R5",
  43. 0, R16, 6, "R6",
  44. 0, R16, 7, "R7",
  45. 0, R16, 8, "R8",
  46. 0, R16, 9, "R9",
  47. 0, R16, 10, "R10",
  48. 0, R16, 11, "R11",
  49. 0, R16, 12, "R12",
  50. 0, R16, 13, "R13",
  51. 0, R16, 14, "R14",
  52. 0, R16, 15, "R15",
  53. 0, R32, 0, "RR0",
  54. 0, R32, 2, "RR2",
  55. 0, R32, 4, "RR4",
  56. 0, R32, 6, "RR6",
  57. 0, R32, 8, "RR8",
  58. 0, R32, 10, "RR10",
  59. 0, R32, 12, "RR12",
  60. 0, R32, 14, "RR14",
  61. 0, R64, 0, "RQ0",
  62. 0, R64, 4, "RQ4",
  63. 0, R64, 8, "RQ8",
  64. 0, R64, 12, "RQ12",
  65. 0, CC, 14, "NZ",
  66. 0, CC, 15, "NC",
  67. 0, CC, 13, "PL",
  68. 0, CC, 5, "MI",
  69. 0, CC, 14, "NE",
  70. 0, CC, 6, "EQ",
  71. 0, CC, 4, "OV",
  72. 0, CC, 12, "NOV",
  73. 0, CC, 4, "PE",
  74. 0, CC, 12, "PO",
  75. 0, CC, 9, "GE",
  76. 0, CC, 1, "LT",
  77. 0, CC, 10, "GT",
  78. 0, CC, 2, "LE",
  79. 0, CC, 15, "UGE",
  80. 0, CC, 7, "ULT",
  81. 0, CC, 11, "UGT",
  82. 0, CC, 3, "ULE",
  83. 0, FLAG, 0x80, "C",
  84. 0, FLAG, 0x40, "Z",
  85. 0, FLAG, 0x20, "S",
  86. 0, FLAG, 0x10, "P",
  87. 0, FLAG, 0x10, "V",
  88. 0, INTCB, 2, "VI",
  89. 0, INTCB, 1, "NVI",
  90. 0, CTLRFLAGS, 1, "FLAGS",
  91. 0, CTLR, 2, "FCW",
  92. 0, CTLR, 3, "REFRESH",
  93. 0, CTLR, 4, "PSAPSEG",
  94. 0, CTLR, 5, "PSAPOFF",
  95. 0, CTLR, 6, "NSPSEG",
  96. 0, CTLR, 7, "NSPOFF",
  97. 0, CTLR, 5, "PSAP",
  98. 0, CTLR, 7, "NSP",
  99. /* TYPE_11a23 */
  100. 0, F1_1F2_3, 0x1F00, "call",
  101. 0, F1_1F2_3, 0x3900, "ldps",
  102. /* TYPE_11b23 */
  103. 0, F1_1F2_3, 0x0D08, "clr",
  104. 0, F1_1F2_3, 0x0C08, "clrb",
  105. 0, F1_1F2_3, 0x0D00, "com",
  106. 0, F1_1F2_3, 0x0C00, "comb",
  107. 0, F1_1F2_3, 0x0D02, "neg",
  108. 0, F1_1F2_3, 0x0C02, "negb",
  109. 0, F1_1F2_3, 0x0D04, "test",
  110. 0, F1_1F2_3, 0x0C04, "testb",
  111. 0, F1_1F2_3, 0x1C08, "testl",
  112. 0, F1_1F2_3, 0x0D06, "tset",
  113. 0, F1_1F2_3, 0x0C06, "tsetb",
  114. 0, F1_1a, 0xB000, "dab",
  115. 0, F1_1a, 0xB10A, "exts",
  116. 0, F1_1a, 0xB100, "extsb",
  117. 0, F1_1a, 0xB107, "extsl",
  118. 0, F1_1b, 0xB300, "rl",
  119. 0, F1_1b, 0xB200, "rlb",
  120. 0, F1_1b, 0xB308, "rlc",
  121. 0, F1_1b, 0xB208, "rlcb",
  122. 0, F1_1b, 0xB304, "rr",
  123. 0, F1_1b, 0xB204, "rrb",
  124. 0, F1_1b, 0xB30C, "rrc",
  125. 0, F1_1b, 0xB20C, "rrcb",
  126. /* TYPE_12 */
  127. 0, F1_2, 0x2B00, "dec",
  128. 0, F1_2, 0x2A00, "decb",
  129. 0, F1_2, 0x2900, "inc",
  130. 0, F1_2, 0x2800, "incb",
  131. 0, LDK, 0xBD00, "ldk",
  132. /* TYPE_1263 */
  133. 0, F1_2F6_3, 0x2700, "bit",
  134. 0, F1_2F6_3, 0x2600, "bitb",
  135. 0, F1_2F6_3, 0x2300, "res",
  136. 0, F1_2F6_3, 0x2200, "resb",
  137. 0, F1_2F6_3, 0x2500, "set",
  138. 0, F1_2F6_3, 0x2400, "setb",
  139. /* TYPE_jp */
  140. 0, JP, 0x1E00, "jp",
  141. 0, TCC, 0xAF00, "tcc",
  142. 0, TCC, 0xAE00, "tccb",
  143. /* TYPE_21a */
  144. 0, F2_1, 0x2D00, "ex",
  145. 0, F2_1, 0x2C00, "exb",
  146. /* TYPE_21b */
  147. 0, F2_1, 0x3500, "adc",
  148. 0, F2_1, 0x3400, "adcb",
  149. 0, F2_1, 0x3E00, "rldb",
  150. 0, F2_1, 0x3C00, "rrdb",
  151. 0, F2_1, 0x3700, "sbc",
  152. 0, F2_1, 0x3600, "sbcb",
  153. /* TYPE_2151.
  154. ** Depending on their operands the cp-instructions might
  155. ** have an opcode of 0x201 more then listed below. This is
  156. ** added at the appropriate place.
  157. ** The difference in opcode between byte-,word- and long-
  158. ** instructions of the F2_1F5_1 group is as follows:
  159. ** If bit 8 is on it is a word instruction; If it is not a
  160. ** word instruction and bit 12 is on it is a long instruction,
  161. ** else it is a byte instruction. This information is used
  162. ** when one of the operands is of type IM.
  163. */
  164. 0, F2_1F5_1, 0x0100, "add",
  165. 0, F2_1F5_1, 0x0000, "addb",
  166. 0, F2_1F5_1, 0x1600, "addl",
  167. 0, F2_1F5_1, 0x0700, "and",
  168. 0, F2_1F5_1, 0x0600, "andb",
  169. 0, F2_1F5_1, 0x1B00, "div",
  170. 0, F2_1F5_1, 0x1A00, "divl",
  171. 0, F2_1F5_1, 0x1900, "mult",
  172. 0, F2_1F5_1, 0x1800, "multl",
  173. 0, F2_1F5_1, 0x0500, "or",
  174. 0, F2_1F5_1, 0x0400, "orb",
  175. 0, F2_1F5_1, 0x0300, "sub",
  176. 0, F2_1F5_1, 0x0200, "subb",
  177. 0, F2_1F5_1, 0x1200, "subl",
  178. 0, F2_1F5_1, 0x0900, "xor",
  179. 0, F2_1F5_1, 0x0800, "xorb",
  180. 0, F2_1F5_1, 0x0B00, "cp",
  181. 0, F2_1F5_1, 0x0A00, "cpb",
  182. 0, F2_1F5_1, 0x1000, "cpl",
  183. 0, LDA, 0, "lda",
  184. /* TYPE_pop */
  185. 0, POP, 0x1700, "pop",
  186. 0, POP, 0x1500, "popl",
  187. /* TYPE_push */
  188. 0, PUSH, 0x1300, "push",
  189. 0, PUSH, 0x1100, "pushl",
  190. /* TYPE_ld */
  191. 0, LD, 0x0100, "ld",
  192. 0, LD, 0, "ldb",
  193. 0, LDL, 0, "ldl",
  194. 0, DJNZ, 0xF080, "djnz",
  195. 0, DJNZ, 0xF000, "dbjnz",
  196. 0, JR, 0xE000, "jr",
  197. 0, CALR, 0xD000, "calr",
  198. /* Depending on their operands the LDR-instructions might
  199. ** have an opcode of 0x200 more then listed below. This is
  200. ** or-ed in at the appropriate place.
  201. */
  202. 0, LDR, 0x3100, "ldr",
  203. 0, LDR, 0x3000, "ldrb",
  204. 0, LDR, 0x3500, "ldrl",
  205. 0, LDAR, 0x3400, "ldar",
  206. 0, F5_1L, 0xB309, "sla",
  207. 0, F5_1L, 0xB209, "slab",
  208. 0, F5_1L, 0xB30D, "slal",
  209. 0, F5_1L, 0xB301, "sll",
  210. 0, F5_1L, 0xB201, "sllb",
  211. 0, F5_1L, 0xB305, "slll",
  212. 0, F5_1R, 0xB309, "sra",
  213. 0, F5_1R, 0xB209, "srab",
  214. 0, F5_1R, 0xB30D, "sral",
  215. 0, F5_1R, 0xB301, "srl",
  216. 0, F5_1R, 0xB201, "srlb",
  217. 0, F5_1R, 0xB305, "srll",
  218. /* Depending on its operands the LDM-instruction might have
  219. ** an opcode of 8 more then listed below. This is added at the
  220. ** appropriate place.
  221. ** TYPE_ldm
  222. */
  223. 0, LDM, 0x1C01, "ldm",
  224. /* For the F6.4 instructions below the yylval-column contains
  225. ** the opcode for the instruction. However the third hexa-digit
  226. ** should be 0; But this is the opcode which must be put into
  227. ** the second word of the instruction!
  228. */
  229. 0, F6_4, 0x3B88, "ind",
  230. 0, F6_4, 0x3A88, "indb",
  231. 0, F6_4, 0x3B08, "indr",
  232. 0, F6_4, 0x3A08, "indrb",
  233. 0, F6_4, 0x3B80, "ini",
  234. 0, F6_4, 0x3A80, "inib",
  235. 0, F6_4, 0x3B00, "inir",
  236. 0, F6_4, 0x3A00, "inirb",
  237. 0, F6_4, 0xBB89, "ldd",
  238. 0, F6_4, 0xBA89, "lddb",
  239. 0, F6_4, 0xBB09, "lddr",
  240. 0, F6_4, 0xBA09, "lddrb",
  241. 0, F6_4, 0xBB81, "ldi",
  242. 0, F6_4, 0xBA81, "ldib",
  243. 0, F6_4, 0xBB01, "ldir",
  244. 0, F6_4, 0xBA01, "ldirb",
  245. 0, F6_4, 0x3B0A, "otdr",
  246. 0, F6_4, 0x3A0A, "otdrb",
  247. 0, F6_4, 0x3B02, "otir",
  248. 0, F6_4, 0x3A02, "otirb",
  249. 0, F6_4, 0x3B8A, "outd",
  250. 0, F6_4, 0x3A8A, "outdb",
  251. 0, F6_4, 0x3B82, "outi",
  252. 0, F6_4, 0x3A82, "outib",
  253. 0, F6_4, 0x3B89, "sind",
  254. 0, F6_4, 0x3A89, "sindb",
  255. 0, F6_4, 0x3B09, "sindr",
  256. 0, F6_4, 0x3A09, "sindrb",
  257. 0, F6_4, 0x3B81, "sini",
  258. 0, F6_4, 0x3A81, "sinib",
  259. 0, F6_4, 0x3B01, "sinir",
  260. 0, F6_4, 0x3A01, "sinirb",
  261. 0, F6_4, 0x3B0B, "sotdr",
  262. 0, F6_4, 0x3A0B, "sotdrb",
  263. 0, F6_4, 0x3B03, "sotir",
  264. 0, F6_4, 0x3A03, "sotirb",
  265. 0, F6_4, 0x3B8B, "soutd",
  266. 0, F6_4, 0x3A8B, "soutdb",
  267. 0, F6_4, 0x3B83, "souti",
  268. 0, F6_4, 0x3A83, "soutib",
  269. 0, F6_4, 0xB808, "trdb",
  270. 0, F6_4, 0xB80C, "trdrb",
  271. 0, F6_4, 0xB800, "trib",
  272. 0, F6_4, 0xB804, "trirb",
  273. 0, F6_4, 0xB80A, "trtdb",
  274. 0, F6_4, 0xB8EE, "trtdrb",
  275. 0, F6_4, 0xB802, "trtib",
  276. 0, F6_4, 0xB8E6, "trtirb",
  277. /* From the F6.5 instructions below the last eight ('string'-
  278. ** instructions) want an 'ir' as operand; The others want a 'r'.
  279. ** In the opcode for the string-instructions bit 1 is on, which
  280. ** indicates the difference.
  281. */
  282. 0, F6_5, 0xBB08, "cpd",
  283. 0, F6_5, 0xBA08, "cpdb",
  284. 0, F6_5, 0xBB0C, "cpdr",
  285. 0, F6_5, 0xBA0C, "cpdrb",
  286. 0, F6_5, 0xBB00, "cpi",
  287. 0, F6_5, 0xBA00, "cpib",
  288. 0, F6_5, 0xBB04, "cpir",
  289. 0, F6_5, 0xBA04, "cpirb",
  290. 0, F6_5, 0xBB0A, "cpsd",
  291. 0, F6_5, 0xBA0A, "cpsdb",
  292. 0, F6_5, 0xBB0E, "cpsdr",
  293. 0, F6_5, 0xBA0E, "cpsdrb",
  294. 0, F6_5, 0xBB02, "cpsi",
  295. 0, F6_5, 0xBA02, "cpsib",
  296. 0, F6_5, 0xBB06, "cpsir",
  297. 0, F6_5, 0xBA06, "cpsirb",
  298. 0, F6_6, 0xB30B, "sda",
  299. 0, F6_6, 0xB20B, "sdab",
  300. 0, F6_6, 0xB30F, "sdal",
  301. 0, F6_6, 0xB303, "sdl",
  302. 0, F6_6, 0xB203, "sdlb",
  303. 0, F6_6, 0xB307, "sdll",
  304. /* The instructions in\b and out\b have two different opcodes
  305. ** depending on their operands (...). Therefore the opcodes
  306. ** below are not complete. The rest is or-ed in at the ap-
  307. ** propriate place!
  308. ** rest | r and da r and ir
  309. ** ---------------------------------
  310. ** in\b | 0xA04 0xC00
  311. ** out\b | 0xA06 OxE00
  312. ** Furthermore the 'special'-instructions don't allow an 'ir'
  313. ** as operand. In their opcode bit 0 is on, which indicates
  314. ** the difference with the other instructions of this group.
  315. */
  316. 0, IN, 0x3100, "in",
  317. 0, IN, 0x3000, "inb",
  318. 0, IN, 0x3B05, "sin",
  319. 0, IN, 0x3A05, "sinb",
  320. 0, OUT, 0x3100, "out",
  321. 0, OUT, 0x3000, "outb",
  322. 0, OUT, 0x3B07, "sout",
  323. 0, OUT, 0x3A07, "soutb",
  324. /* Depending on their operands the LDCTL-instructions might
  325. ** have an opcode of 8 more then listed below. This is or-ed
  326. ** in at the appropriate place.
  327. */
  328. 0, LDCTL, 0x7D00, "ldctl",
  329. 0, LDCTLB, 0x8C00, "ldctlb",
  330. 0, MREQ, 0x7B0D, "mreq",
  331. 0, F9_1, 0x8D05, "comflg",
  332. 0, F9_1, 0x8D03, "resflg",
  333. 0, F9_1, 0x8D01, "setflg",
  334. 0, F9_2, 0x7C00, "di",
  335. 0, F9_2, 0x7C04, "ei",
  336. 0, F9_3, 0x7A00, "halt",
  337. 0, F9_3, 0x7B00, "iret",
  338. 0, F9_3, 0x7B0A, "mbit",
  339. 0, F9_3, 0x7B09, "mres",
  340. 0, F9_3, 0x7B08, "mset",
  341. 0, F9_3, 0x8D07, "nop",
  342. /* Rest of the opcode-0x200 is or-ed in at the appropriate place
  343. */
  344. 0, RET, 0x9E00, "ret",
  345. 0, SC, 0x7F00, "sc",