mach3.c 12 KB

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  1. /*
  2. * (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands.
  3. * See the copyright notice in the ACK home directory, in the file "Copyright".
  4. */
  5. #define RCSID3 "$Id$"
  6. /*
  7. * VAX-11 keywords
  8. */
  9. 0, REG, 0, "r0",
  10. 0, REG, 1, "r1",
  11. 0, REG, 2, "r2",
  12. 0, REG, 3, "r3",
  13. 0, REG, 4, "r4",
  14. 0, REG, 5, "r5",
  15. 0, REG, 6, "r6",
  16. 0, REG, 7, "r7",
  17. 0, REG, 8, "r8",
  18. 0, REG, 9, "r9",
  19. 0, REG, 10, "r10",
  20. 0, REG, 11, "r11",
  21. 0, REG, 12, "r12",
  22. 0, REG, 12, "ap",
  23. 0, REG, 13, "r13",
  24. 0, REG, 13, "fp",
  25. 0, REG, 14, "r14",
  26. 0, REG, 14, "sp",
  27. 0, REG, 15, "r15",
  28. 0, REG, 15, "pc",
  29. /* For immediate mode, we need the size as specified by the instruction.
  30. Ordinary operands are therefore encoded as _w, _b, and _l to indicate
  31. size.
  32. For now, immediate floating point and immediate values of size > 4 are not
  33. implemented. _u is used for this.
  34. The valu_t field is used for the opcode. Most opcodes take one byte.
  35. The ones that don't take two bytes.
  36. */
  37. /* integer arithmetic and logical instructions */
  38. 0, OP2_w_w, 0x58, "adawi",
  39. 0, OP2_b_b, 0x80, "addb2",
  40. 0, OP3_b_b_b, 0x81, "addb3",
  41. 0, OP2_w_w, 0xa0, "addw2",
  42. 0, OP3_w_w_w, 0xa1, "addw3",
  43. 0, OP2_l_l, 0xc0, "addl2",
  44. 0, OP3_l_l_l, 0xc1, "addl3",
  45. 0, OP2_l_l, 0xd8, "adwc",
  46. 0, OP3_b_l_l, 0x78, "ashl",
  47. 0, OP3_b_u_u, 0x79, "ashq",
  48. 0, OP2_b_b, 0x8a, "bicb2",
  49. 0, OP3_b_b_b, 0x8b, "bicb3",
  50. 0, OP2_w_w, 0xaa, "bicw2",
  51. 0, OP3_w_w_w, 0xab, "bicw3",
  52. 0, OP2_l_l, 0xca, "bicl2",
  53. 0, OP3_l_l_l, 0xcb, "bicl3",
  54. 0, OP2_b_b, 0x88, "bisb2",
  55. 0, OP3_b_b_b, 0x89, "bisb3",
  56. 0, OP2_w_w, 0xa8, "bisw2",
  57. 0, OP3_w_w_w, 0xa9, "bisw3",
  58. 0, OP2_l_l, 0xc8, "bisl2",
  59. 0, OP3_l_l_l, 0xc9, "bisl3",
  60. 0, OP2_b_b, 0x93, "bitb",
  61. 0, OP2_w_w, 0xb3, "bitw",
  62. 0, OP2_l_l, 0xd3, "bitl",
  63. 0, OP1_X, 0x94|(1L<<16), "clrb",
  64. 0, OP1_X, 0xb4|(2L<<16), "clrw",
  65. 0, OP1_X, 0xd4|(4L<<16), "clrl",
  66. 0, OP1_u, 0x7c, "clrq",
  67. 0, OP1_u, 0x7cfd, "clro",
  68. 0, OP2_b_b, 0x91, "cmpb",
  69. 0, OP2_w_w, 0xb1, "cmpw",
  70. 0, OP2_l_l, 0xd1, "cmpl",
  71. 0, OP2_b_w, 0x99, "cvtbw",
  72. 0, OP2_b_l, 0x98, "cvtbl",
  73. 0, OP2_w_b, 0x33, "cvtwb",
  74. 0, OP2_w_l, 0x32, "cvtwl",
  75. 0, OP2_l_b, 0xf6, "cvtlb",
  76. 0, OP2_l_w, 0xf7, "cvtlw",
  77. 0, OP1_X, 0x97|(1L<<16), "decb",
  78. 0, OP1_X, 0xb7|(2L<<16), "decw",
  79. 0, OP1_X, 0xd7|(4L<<16), "decl",
  80. 0, OP2_b_b, 0x86, "divb2",
  81. 0, OP3_b_b_b, 0x87, "divb3",
  82. 0, OP2_w_w, 0xa6, "divw2",
  83. 0, OP3_w_w_w, 0xa7, "divw3",
  84. 0, OP2_l_l, 0xc6, "divl2",
  85. 0, OP3_l_l_l, 0xc7, "divl3",
  86. 0, OP4_l_u_l_l, 0x7b, "ediv",
  87. 0, OP4_l_l_l_u, 0x7a, "emul",
  88. 0, OP1_X, 0x96|(1L<<16), "incb",
  89. 0, OP1_X, 0xb6|(2L<<16), "incw",
  90. 0, OP1_X, 0xd6|(4L<<16), "incl",
  91. 0, OP2_b_b, 0x92, "mcomb",
  92. 0, OP2_w_w, 0xb2, "mcomw",
  93. 0, OP2_l_l, 0xd2, "mcoml",
  94. 0, OP2_b_b, 0x8e, "mnegb",
  95. 0, OP2_w_w, 0xae, "mnegw",
  96. 0, OP2_l_l, 0xce, "mnegl",
  97. 0, OP2_b_b, 0x90, "movb",
  98. 0, OP2_w_w, 0xb0, "movw",
  99. 0, OP2_l_l, 0xd0, "movl",
  100. 0, OP2_u_u, 0x7d, "movq",
  101. 0, OP2_u_u, 0x7dfd, "movo",
  102. 0, OP2_b_w, 0x9b, "movzbw",
  103. 0, OP2_b_l, 0x9a, "movzbl",
  104. 0, OP2_w_l, 0x3c, "movzwl",
  105. 0, OP2_b_b, 0x84, "mulb2",
  106. 0, OP3_b_b_b, 0x85, "mulb3",
  107. 0, OP2_w_w, 0xa4, "mulw2",
  108. 0, OP3_w_w_w, 0xa5, "mulw3",
  109. 0, OP2_l_l, 0xc4, "mull2",
  110. 0, OP3_l_l_l, 0xc5, "mull3",
  111. 0, OP1_X, 0xdd|(4L<<16), "pushl",
  112. 0, OP3_b_l_l, 0x9c, "rotl",
  113. 0, OP2_l_l, 0xd9, "sbwc",
  114. 0, OP2_b_b, 0x82, "subb2",
  115. 0, OP3_b_b_b, 0x83, "subb3",
  116. 0, OP2_w_w, 0xa2, "subw2",
  117. 0, OP3_w_w_w, 0xa3, "subw3",
  118. 0, OP2_l_l, 0xc2, "subl2",
  119. 0, OP3_l_l_l, 0xc3, "subl3",
  120. 0, OP1_X, 0x95|(1L<<16), "tstb",
  121. 0, OP1_X, 0xb5|(2L<<16), "tstw",
  122. 0, OP1_X, 0xd5|(4L<<16), "tstl",
  123. 0, OP2_b_b, 0x8c, "xorb2",
  124. 0, OP3_b_b_b, 0x8d, "xorb3",
  125. 0, OP2_w_w, 0xac, "xorw2",
  126. 0, OP3_w_w_w, 0xad, "xorw3",
  127. 0, OP2_l_l, 0xcc, "xorl2",
  128. 0, OP3_l_l_l, 0xcd, "xorl3",
  129. /* Address instructions */
  130. 0, OP2_A_l, 0x9e, "movab",
  131. 0, OP2_A_l, 0x3e, "movaw",
  132. 0, OP2_A_l, 0xde, "moval",
  133. 0, OP2_A_l, 0xde, "movaf",
  134. 0, OP2_A_l, 0x7e, "movaq",
  135. 0, OP2_A_l, 0x7e, "movad",
  136. 0, OP2_A_l, 0x7e, "movag",
  137. 0, OP2_A_l, 0x7efd, "movah",
  138. 0, OP2_A_l, 0x7efd, "movao",
  139. 0, OP1_A, 0x9f, "pushab",
  140. 0, OP1_A, 0x3f, "pushaw",
  141. 0, OP1_A, 0xdf, "pushal",
  142. 0, OP1_A, 0xdf, "pushaf",
  143. 0, OP1_A, 0x7f, "pushaq",
  144. 0, OP1_A, 0x7f, "pushad",
  145. 0, OP1_A, 0x7f, "pushag",
  146. 0, OP1_A, 0x7ffd, "pushah",
  147. 0, OP1_A, 0x7ffd, "pushao",
  148. /* Variable length bit-field instructions */
  149. 0, OP4_l_b_V_l, 0xec, "cmpv",
  150. 0, OP4_l_b_V_l, 0xed, "cmpzv",
  151. 0, OP4_l_b_V_l, 0xee, "extv",
  152. 0, OP4_l_b_V_l, 0xef, "extzv",
  153. 0, OP4_l_b_V_l, 0xeb, "ffc",
  154. 0, OP4_l_b_V_l, 0xea, "ffs",
  155. 0, OP4_l_l_b_V, 0xf0, "insv",
  156. /* Control instructions */
  157. 0, OP4_b_b_b_Bw, 0x9d, "acbb",
  158. 0, OP4_w_w_w_Bw, 0x3d, "acbw",
  159. 0, OP4_l_l_l_Bw, 0xf1, "acbl",
  160. 0, OP4_u_u_u_Bw, 0x4f, "acbf",
  161. 0, OP4_u_u_u_Bw, 0x6f, "acbd",
  162. 0, OP4_u_u_u_Bw, 0x4ffd, "acbg",
  163. 0, OP4_u_u_u_Bw, 0x6ffd, "acbh",
  164. 0, OP3_l_l_Bb, 0xf3, "aobleq",
  165. 0, OP3_l_l_Bb, 0xf2, "aoblss",
  166. 0, OP1_BX, 0x14|(1L<<16), "bgtr",
  167. 0, OP1_BX, 0x15|(1L<<16), "bleq",
  168. 0, OP1_BX, 0x12|(1L<<16), "bneq",
  169. 0, OP1_BX, 0x12|(1L<<16), "bnequ",
  170. 0, OP1_BX, 0x13|(1L<<16), "beql",
  171. 0, OP1_BX, 0x13|(1L<<16), "beqlu",
  172. 0, OP1_BX, 0x18|(1L<<16), "bgeq",
  173. 0, OP1_BX, 0x19|(1L<<16), "blss",
  174. 0, OP1_BX, 0x1a|(1L<<16), "bgtru",
  175. 0, OP1_BX, 0x1b|(1L<<16), "blequ",
  176. 0, OP1_BX, 0x1c|(1L<<16), "bvc",
  177. 0, OP1_BX, 0x1d|(1L<<16), "bvs",
  178. 0, OP1_BX, 0x1e|(1L<<16), "bgequ",
  179. 0, OP1_BX, 0x1e|(1L<<16), "bcc",
  180. 0, OP1_BX, 0x1f|(1L<<16), "blssu",
  181. 0, OP1_BX, 0x1f|(1L<<16), "bcs",
  182. 0, OP3_l_V_Bb, 0xe0, "bbs",
  183. 0, OP3_l_V_Bb, 0xe1, "bbc",
  184. 0, OP3_l_V_Bb, 0xe2, "bbss",
  185. 0, OP3_l_V_Bb, 0xe3, "bbcs",
  186. 0, OP3_l_V_Bb, 0xe4, "bbsc",
  187. 0, OP3_l_V_Bb, 0xe5, "bbcc",
  188. 0, OP3_l_V_Bb, 0xe6, "bbssi",
  189. 0, OP3_l_V_Bb, 0xe7, "bbcci",
  190. 0, OP2_l_Bb, 0xe8, "blbs",
  191. 0, OP2_l_Bb, 0xe9, "blbc",
  192. 0, OP1_Be, 0x14, "jgtr",
  193. 0, OP1_Be, 0x15, "jleq",
  194. 0, OP1_Be, 0x12, "jneq",
  195. 0, OP1_Be, 0x12, "jnequ",
  196. 0, OP1_Be, 0x13, "jeql",
  197. 0, OP1_Be, 0x13, "jeqlu",
  198. 0, OP1_Be, 0x18, "jgeq",
  199. 0, OP1_Be, 0x19, "jlss",
  200. 0, OP1_Be, 0x1a, "jgtru",
  201. 0, OP1_Be, 0x1b, "jlequ",
  202. 0, OP1_Be, 0x1c, "jvc",
  203. 0, OP1_Be, 0x1d, "jvs",
  204. 0, OP1_Be, 0x1e, "jgequ",
  205. 0, OP1_Be, 0x1e, "jcc",
  206. 0, OP1_Be, 0x1f, "jlssu",
  207. 0, OP1_Be, 0x1f, "jcs",
  208. 0, OP2_l_Be, 0xe8, "jlbs",
  209. 0, OP2_l_Be, 0xe9, "jlbc",
  210. 0, OP3_l_V_Be, 0xe0, "jbs",
  211. 0, OP3_l_V_Be, 0xe1, "jbc",
  212. 0, OP3_l_V_Be, 0xe2, "jbss",
  213. 0, OP3_l_V_Be, 0xe3, "jbcs",
  214. 0, OP3_l_V_Be, 0xe4, "jbsc",
  215. 0, OP3_l_V_Be, 0xe5, "jbcc",
  216. 0, OP3_l_V_Be, 0xe6, "jbssi",
  217. 0, OP3_l_V_Be, 0xe7, "jbcci",
  218. 0, OP1_Bx, 0x11, "br",
  219. 0, OP1_BX, 0x11|(1L<<16), "brb",
  220. 0, OP1_BX, 0x31|(2L<<16), "brw",
  221. 0, OP1_Be, 0x11, "jbr",
  222. 0, OP1_Bx, 0x10, "bsb",
  223. 0, OP1_BX, 0x10|(1L<<16), "bsbb",
  224. 0, OP1_BX, 0x30|(2L<<16), "bsbw",
  225. 0, CASE_X_X_X, 0x8f|(1L<<16), "caseb",
  226. 0, CASE_X_X_X, 0xaf|(2L<<16), "casew",
  227. 0, CASE_X_X_X, 0xcf|(4L<<16), "casel",
  228. 0, OP1_A, 0x17, "jmp",
  229. 0, OP1_A, 0x16, "jsb",
  230. 0, OP0, 0x05, "rsb",
  231. 0, OP2_l_Bb, 0xf4, "sobgeq",
  232. 0, OP2_l_Bb, 0xf5, "sobgtr",
  233. /* Procedure call instructions */
  234. 0, OP2_A_A, 0xfa, "callg",
  235. 0, OP2_l_A, 0xfb, "calls",
  236. 0, OP0, 0x04, "ret",
  237. /* Miscellaneous instructions */
  238. 0, OP1_X, 0xb9|(2L<<16), "bicpsw",
  239. 0, OP1_X, 0xb8|(2L<<16), "bispsw",
  240. 0, OP0, 0x03, "bpt",
  241. 0, OP0, 0x00, "halt",
  242. 0, OP6_l_l_l_l_l_l,0x0a, "index",
  243. 0, OP1_X, 0xdc|(4L<<16), "movpsl",
  244. 0, OP0, 0x01, "nop",
  245. 0, OP1_X, 0xba|(2L<<16), "popr",
  246. 0, OP1_X, 0xbb|(2L<<16), "pushr",
  247. 0, OP0, 0xfc, "xfc",
  248. /* Queue instructions */
  249. 0, OP2_A_A, 0x5c, "insqhi",
  250. 0, OP2_A_A, 0x5d, "insqti",
  251. 0, OP2_A_A, 0x0e, "insque",
  252. 0, OP2_A_l, 0x5e, "remqhi",
  253. 0, OP2_A_l, 0x5f, "remqti",
  254. 0, OP2_A_l, 0x0f, "remque",
  255. /* Floating point instructions */
  256. 0, OP2_u_u, 0x40, "addf2",
  257. 0, OP3_u_u_u, 0x41, "addf3",
  258. 0, OP2_u_u, 0x60, "addd2",
  259. 0, OP3_u_u_u, 0x61, "addd3",
  260. 0, OP2_u_u, 0x40fd, "addg2",
  261. 0, OP3_u_u_u, 0x41fd, "addg3",
  262. 0, OP2_u_u, 0x60fd, "addh2",
  263. 0, OP3_u_u_u, 0x61fd, "addh3",
  264. 0, OP1_u, 0xd4, "clrf",
  265. 0, OP1_u, 0x7c, "clrd",
  266. 0, OP1_u, 0x7c, "clrg",
  267. 0, OP1_u, 0x7cfd, "clrh",
  268. 0, OP2_u_u, 0x51, "cmpf",
  269. 0, OP2_u_u, 0x71, "cmpd",
  270. 0, OP2_u_u, 0x51fd, "cmpg",
  271. 0, OP2_u_u, 0x71fd, "cmph",
  272. 0, OP2_b_u, 0x4c, "cvtbf",
  273. 0, OP2_b_u, 0x6c, "cvtbd",
  274. 0, OP2_b_u, 0x4cfd, "cvtbg",
  275. 0, OP2_b_u, 0x6cfd, "cvtbh",
  276. 0, OP2_w_u, 0x4d, "cvtwf",
  277. 0, OP2_w_u, 0x6d, "cvtwd",
  278. 0, OP2_w_u, 0x4dfd, "cvtwg",
  279. 0, OP2_w_u, 0x6dfd, "cvtwh",
  280. 0, OP2_l_u, 0x4e, "cvtlf",
  281. 0, OP2_l_u, 0x6e, "cvtld",
  282. 0, OP2_l_u, 0x4efd, "cvtlg",
  283. 0, OP2_l_u, 0x6efd, "cvtlh",
  284. 0, OP2_u_b, 0x48, "cvtfb",
  285. 0, OP2_u_b, 0x68, "cvtdb",
  286. 0, OP2_u_b, 0x48fd, "cvtgb",
  287. 0, OP2_u_b, 0x68fd, "cvthb",
  288. 0, OP2_u_w, 0x49, "cvtfw",
  289. 0, OP2_u_w, 0x69, "cvtdw",
  290. 0, OP2_u_w, 0x49fd, "cvtgw",
  291. 0, OP2_u_w, 0x69fd, "cvthw",
  292. 0, OP2_u_l, 0x4a, "cvtfl",
  293. 0, OP2_u_l, 0x6a, "cvtdl",
  294. 0, OP2_u_l, 0x4afd, "cvtgl",
  295. 0, OP2_u_l, 0x6afd, "cvthl",
  296. 0, OP2_u_l, 0x4b, "cvtrfl",
  297. 0, OP2_u_l, 0x6b, "cvtrdl",
  298. 0, OP2_u_l, 0x4bfd, "cvtrgl",
  299. 0, OP2_u_l, 0x6bfd, "cvtrhl",
  300. 0, OP2_u_u, 0x56, "cvtfd",
  301. 0, OP2_u_u, 0x99fd, "cvtfg",
  302. 0, OP2_u_u, 0x98fd, "cvtfh",
  303. 0, OP2_u_u, 0x76, "cvtdf",
  304. 0, OP2_u_u, 0x32fd, "cvtdh",
  305. 0, OP2_u_u, 0x33fd, "cvtgf",
  306. 0, OP2_u_u, 0x56fd, "cvtgh",
  307. 0, OP2_u_u, 0xf6fd, "cvthf",
  308. 0, OP2_u_u, 0xf7fd, "cvthd",
  309. 0, OP2_u_u, 0x76fd, "cvthg",
  310. 0, OP2_u_u, 0x46, "divf2",
  311. 0, OP3_u_u_u, 0x47, "divf3",
  312. 0, OP2_u_u, 0x66, "divd2",
  313. 0, OP3_u_u_u, 0x67, "divd3",
  314. 0, OP2_u_u, 0x46fd, "divg2",
  315. 0, OP3_u_u_u, 0x47fd, "divg3",
  316. 0, OP2_u_u, 0x66fd, "divh2",
  317. 0, OP3_u_u_u, 0x67fd, "divh3",
  318. 0, OP5_u_b_u_l_u, 0x54, "emodf",
  319. 0, OP5_u_b_u_l_u, 0x74, "emodd",
  320. 0, OP5_u_w_u_l_u, 0x54fd, "emodg",
  321. 0, OP5_u_w_u_l_u, 0x74fd, "emodh",
  322. 0, OP2_u_u, 0x52, "mnegf",
  323. 0, OP2_u_u, 0x72, "mnegd",
  324. 0, OP2_u_u, 0x52fd, "mnegg",
  325. 0, OP2_u_u, 0x72fd, "mnegh",
  326. 0, OP2_u_u, 0x50, "movf",
  327. 0, OP2_u_u, 0x70, "movd",
  328. 0, OP2_u_u, 0x50fd, "movg",
  329. 0, OP2_u_u, 0x70fd, "movh",
  330. 0, OP2_u_u, 0x44, "mulf2",
  331. 0, OP3_u_u_u, 0x45, "mulf3",
  332. 0, OP2_u_u, 0x64, "muld2",
  333. 0, OP3_u_u_u, 0x65, "muld3",
  334. 0, OP2_u_u, 0x44fd, "mulg2",
  335. 0, OP3_u_u_u, 0x45fd, "mulg3",
  336. 0, OP2_u_u, 0x64fd, "mulh2",
  337. 0, OP3_u_u_u, 0x65fd, "mulh3",
  338. 0, OP3_u_w_A, 0x55, "polyf",
  339. 0, OP3_u_w_A, 0x75, "polyd",
  340. 0, OP3_u_w_A, 0x55fd, "polyg",
  341. 0, OP3_u_w_A, 0x75fd, "polyh",
  342. 0, OP2_u_u, 0x42, "subf2",
  343. 0, OP3_u_u_u, 0x43, "subf3",
  344. 0, OP2_u_u, 0x62, "subd2",
  345. 0, OP3_u_u_u, 0x63, "subd3",
  346. 0, OP2_u_u, 0x42fd, "subg2",
  347. 0, OP3_u_u_u, 0x43fd, "subg3",
  348. 0, OP2_u_u, 0x62fd, "subh2",
  349. 0, OP3_u_u_u, 0x63fd, "subh3",
  350. 0, OP1_u, 0x53, "tstf",
  351. 0, OP1_u, 0x73, "tstd",
  352. 0, OP1_u, 0x53fd, "tstg",
  353. 0, OP1_u, 0x73fd, "tsth",
  354. /* Character string instructions */
  355. 0, OP3_w_A_A, 0x29, "cmpc3",
  356. 0, OP5_w_A_b_w_A, 0x2d, "cmpc5",
  357. 0, OP3_b_w_A, 0x3a, "locc",
  358. 0, OP4_w_A_w_A, 0x39, "matchc",
  359. 0, OP3_w_A_A, 0x28, "movc3",
  360. 0, OP5_w_A_b_w_A, 0x2c, "movc5",
  361. 0, OP6_w_A_b_A_w_A,0x2e, "movtc",
  362. 0, OP6_w_A_b_A_w_A,0x2f, "movtuc",
  363. 0, OP4_w_A_A_b, 0x2a, "scanc",
  364. 0, OP3_b_w_A, 0x3b, "skpc",
  365. 0, OP4_w_A_A_b, 0x2b, "spanc",
  366. /* Cyclic redundancy check instructions */
  367. 0, OP4_A_l_w_A, 0x0b, "crc",
  368. /* Decimal string instructions */
  369. 0, OP4_w_A_w_A, 0x20, "addp4",
  370. 0, OP6_w_A_w_A_w_A,0x21, "addp6",
  371. 0, OP6_b_w_A_b_w_A,0xf8, "ashp",
  372. 0, OP3_w_A_A, 0x35, "cmpp3",
  373. 0, OP4_w_A_w_A, 0x37, "cmpp4",
  374. 0, OP3_l_w_A, 0xf9, "cvtlp",
  375. 0, OP3_w_A_l, 0x36, "cvtpl",
  376. 0, OP4_w_A_w_A, 0x08, "cvtps",
  377. 0, OP5_w_A_A_w_A, 0x24, "cvtpt",
  378. 0, OP4_w_A_w_A, 0x09, "cvtsp",
  379. 0, OP5_w_A_A_w_A, 0x26, "cvttp",
  380. 0, OP6_w_A_w_A_w_A,0x27, "divp",
  381. 0, OP3_w_A_A, 0x34, "movp",
  382. 0, OP6_w_A_w_A_w_A,0x25, "mulp",
  383. 0, OP4_w_A_w_A, 0x22, "subp4",
  384. 0, OP6_w_A_w_A_w_A,0x23, "subp6",
  385. /* Edit instruction */
  386. 0, OP4_w_A_A_A, 0x38, "editpc",
  387. /* Other VAX-11 instructions */
  388. /* BSD 4.3 adb has a different opinion of the bugw and bugl instructions:
  389. it thinks that an addressing mode byte is required. However, according
  390. to the VAX-11 Architecture Reference Manual, Revision 6.1, 1982, the
  391. access type is b, which means that the operand is a branch displacement.
  392. */
  393. 0, OP1_BX, 0xfeff|(2L<<16),"bugw",
  394. 0, OP1_BX, 0xfdff|(4L<<16),"bugl",
  395. 0, OP3_b_w_A, 0x0c, "prober",
  396. 0, OP3_b_w_A, 0x0d, "probew",
  397. 0, OP0, 0x02, "rei",
  398. 0, OP1_X, 0xbc|(2L<<16), "chmk",
  399. 0, OP1_X, 0xbd|(2L<<16), "chme",
  400. 0, OP1_X, 0xbe|(2L<<16), "chms",
  401. 0, OP1_X, 0xbf|(2L<<16), "chmu",
  402. 0, OP0, 0x06, "ldpctx",
  403. 0, OP0, 0x07, "svpctx",
  404. 0, OP2_l_l, 0xda, "mtpr",
  405. 0, OP2_l_l, 0xdb, "mfpr",