mach3.c 2.7 KB

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  1. /*
  2. * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
  3. * See the copyright notice in the ACK home directory, in the file "Copyright".
  4. */
  5. #define RCSID3 "$Id$"
  6. /*
  7. * Motorola 6805 keywords
  8. */
  9. /*
  10. * The X register
  11. */
  12. 0, X, 0, "x",
  13. /*
  14. * Bit test and branch
  15. */
  16. 0, BBRANCH, 0x00, "brset",
  17. 0, BBRANCH, 0x01, "brclr",
  18. /*
  19. * Bit manipulation
  20. */
  21. 0, BIT, 0x10, "bset",
  22. 0, BIT, 0x11, "bclr",
  23. /*
  24. * Branches
  25. */
  26. 0, BRANCH, 0x20, "bra",
  27. 0, BRANCH, 0x21, "brn",
  28. 0, BRANCH, 0x22, "bhi",
  29. 0, BRANCH, 0x23, "bls",
  30. 0, BRANCH, 0x24, "bcc",
  31. 0, BRANCH, 0x25, "bcs",
  32. 0, BRANCH, 0x26, "bne",
  33. 0, BRANCH, 0x27, "beq",
  34. 0, BRANCH, 0x28, "bhcc",
  35. 0, BRANCH, 0x29, "bhcs",
  36. 0, BRANCH, 0x2a, "bpl",
  37. 0, BRANCH, 0x2b, "bmi",
  38. 0, BRANCH, 0x2c, "bmc",
  39. 0, BRANCH, 0x2d, "bms",
  40. 0, BRANCH, 0x2e, "bil",
  41. 0, BRANCH, 0x2f, "bih",
  42. /*
  43. * Read modify write on anything but registers
  44. */
  45. 0, RMR, 0x30, "neg",
  46. 0, RMR, 0x33, "com",
  47. 0, RMR, 0x34, "lsr",
  48. 0, RMR, 0x36, "ror",
  49. 0, RMR, 0x36, "asr",
  50. 0, RMR, 0x38, "lsl",
  51. 0, RMR, 0x39, "rol",
  52. 0, RMR, 0x3a, "dec",
  53. 0, RMR, 0x3c, "inc",
  54. 0, RMR, 0x3d, "tst",
  55. 0, RMR, 0x3f, "clr",
  56. /*
  57. * Implied stuff
  58. */
  59. 0, NOARG, 0x80, "rti",
  60. 0, NOARG, 0x81, "rts",
  61. 0, NOARG, 0x83, "swi",
  62. 0, NOARG, 0x97, "tax",
  63. 0, NOARG, 0x98, "clc",
  64. 0, NOARG, 0x99, "sec",
  65. 0, NOARG, 0x9a, "cli",
  66. 0, NOARG, 0x9b, "sei",
  67. 0, NOARG, 0x9c, "rsp",
  68. 0, NOARG, 0x9d, "nop",
  69. 0, NOARG, 0x9f, "txa",
  70. /*
  71. * Register memory.
  72. * Warning. Some imediate opcodes excluded in parser actions.
  73. */
  74. 0, RM, 0xa0, "sub",
  75. 0, RM, 0xa1, "cmp",
  76. 0, RM, 0xa2, "sbc",
  77. 0, RM, 0xa3, "cpx",
  78. 0, RM, 0xa4, "and",
  79. 0, RM, 0xa5, "bit",
  80. 0, RM, 0xa6, "lda",
  81. 0, RM, 0xa7, "sta",
  82. 0, RM, 0xa8, "eor",
  83. 0, RM, 0xa9, "adc",
  84. 0, RM, 0xaa, "ora",
  85. 0, RM, 0xab, "add",
  86. 0, RM, 0xac, "jmp",
  87. 0, BRANCH, 0xad, "bsr",
  88. 0, RM, 0xad, "jsr",
  89. 0, RM, 0xae, "ldx",
  90. 0, RM, 0xaf, "stx",
  91. /*
  92. * Branch synonyms
  93. */
  94. 0, BRANCH, 0x24, "bhs", /* bcc */
  95. 0, BRANCH, 0x25, "blo", /* bcs */
  96. /*
  97. * Brain damaged concatenated opcodes for RMR on registers
  98. */
  99. 0, NOARG, 0x40, "nega",
  100. 0, NOARG, 0x43, "coma",
  101. 0, NOARG, 0x44, "lsra",
  102. 0, NOARG, 0x46, "rora",
  103. 0, NOARG, 0x47, "asra",
  104. 0, NOARG, 0x48, "lsla",
  105. 0, NOARG, 0x49, "rola",
  106. 0, NOARG, 0x4a, "deca",
  107. 0, NOARG, 0x4c, "inca",
  108. 0, NOARG, 0x4d, "tsta",
  109. 0, NOARG, 0x4f, "clra",
  110. 0, NOARG, 0x50, "negx",
  111. 0, NOARG, 0x53, "comx",
  112. 0, NOARG, 0x54, "lsrx",
  113. 0, NOARG, 0x56, "rorx",
  114. 0, NOARG, 0x57, "asrx",
  115. 0, NOARG, 0x58, "lslx",
  116. 0, NOARG, 0x59, "rolx",
  117. 0, NOARG, 0x5a, "decx",
  118. 0, NOARG, 0x5c, "incx",
  119. 0, NOARG, 0x5d, "tstx",
  120. 0, NOARG, 0x5f, "clrx",
  121. /*
  122. * CMOS support
  123. */
  124. 0, CMOS, 0, ".cmos",
  125. 0, CMOS, 0x8e, "stop",
  126. 0, CMOS, 0x8f, "wait",